mirror of https://github.com/anrieff/libcpuid
DB: add Intel Cascade Lake
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@ -402,6 +402,14 @@ const struct match_entry_t cpudb_intel[] = {
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{ 6, 14, 13, -1, 158, 6, -1, -1, NC, CORE_|_I_|_5 , 0, "Coffee Lake-R (Core i5)" },
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{ 6, 14, 11, -1, 158, 4, -1, -1, NC, CORE_|_I_|_3 , 0, "Coffee Lake-R (Core i3)" },
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/* Cascade Lake CPUs (2019, 2nd Xeon Scalable gen, 14nm) => https://en.wikichip.org/wiki/intel/microarchitectures/cascade_lake */
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{ 6, 5, 7, -1, 85, -1, -1, -1, NC, CORE_|_I_|_9 , _10xxx, "Cascade Lake-X (Core i9)" },
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{ 6, 5, -1, -1, 85, -1, -1, -1, NC, XEON_|_W_ , _x2xx, "Cascade Lake-W (Xeon W)" },
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{ 6, 5, -1, -1, 85, -1, -1, -1, NC, XEON_|_PLATINIUM_, _x2xx, "Cascade Lake-SP (Xeon Platinum)" },
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{ 6, 5, -1, -1, 85, -1, -1, -1, NC, XEON_|_GOLD_ , _x2xx, "Cascade Lake-SP (Xeon Gold)" },
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{ 6, 5, -1, -1, 85, -1, -1, -1, NC, XEON_|_SILVER_ , _x2xx, "Cascade Lake-SP (Xeon Silver)" },
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{ 6, 5, -1, -1, 85, -1, -1, -1, NC, XEON_|_BRONZE_ , _x2xx, "Cascade Lake-SP (Xeon Bronze)" },
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/* Comet Lake CPUs (10th gen, 14nm): */
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{ 6, 5, -1, -1, 165, 10, -1, -1, NC, CORE_|_I_|_9 , 0, "Comet Lake (Core i9)" },
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{ 6, 5, -1, -1, 165, 8, -1, -1, NC, CORE_|_I_|_7 , 0, "Comet Lake (Core i7)" },
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