From d212585d513a132696446d8bb759b6608b68c057 Mon Sep 17 00:00:00 2001 From: Xorg Date: Sat, 11 Mar 2017 15:44:40 +0100 Subject: [PATCH 1/6] Align some misaligned brackets in databases --- libcpuid/recog_amd.c | 8 ++++---- libcpuid/recog_intel.c | 19 +++++++++---------- 2 files changed, 13 insertions(+), 14 deletions(-) diff --git a/libcpuid/recog_amd.c b/libcpuid/recog_amd.c index 2e6c8a9..26f10f5 100644 --- a/libcpuid/recog_amd.c +++ b/libcpuid/recog_amd.c @@ -238,11 +238,11 @@ const struct match_entry_t cpudb_amd[] = { { 15, 0, -1, 21, 30, 2, 1024, -1, FUSION_A , 0, "Kaveri X2" }, { 15, 0, -1, 21, 30, 4, 1024, -1, FUSION_A , 0, "Kaveri X4" }, /* 2014 CPUs: Puma architecture: Beema and Mullins */ - { 15, 0, -1, 22, 30, 2, 1024, -1, FUSION_E , 0, "Mullins X2" }, - { 15, 0, -1, 22, 30, 4, 1024, -1, FUSION_A , 0, "Mullins X4" }, + { 15, 0, -1, 22, 30, 2, 1024, -1, FUSION_E , 0, "Mullins X2" }, + { 15, 0, -1, 22, 30, 4, 1024, -1, FUSION_A , 0, "Mullins X4" }, /* 2015 CPUs: Excavator architecture: Carrizo */ - { 15, 1, -1, 21, 60, 2, 1024, -1, FUSION_A , 0, "Carrizo X2" }, - { 15, 1, -1, 21, 60, 4, 1024, -1, FUSION_A , 0, "Carrizo X4" }, + { 15, 1, -1, 21, 60, 2, 1024, -1, FUSION_A , 0, "Carrizo X2" }, + { 15, 1, -1, 21, 60, 4, 1024, -1, FUSION_A , 0, "Carrizo X4" }, /* 2015 CPUs: Steamroller architecture: Godavari */ //TODO /* 2016 CPUs: Excavator architecture: Bristol Ridge */ diff --git a/libcpuid/recog_intel.c b/libcpuid/recog_intel.c index 06c7d9c..1b9dcaf 100644 --- a/libcpuid/recog_intel.c +++ b/libcpuid/recog_intel.c @@ -210,7 +210,7 @@ const struct match_entry_t cpudb_intel[] = { { 6, 7, -1, -1, 23, 1, -1, -1, CORE_SOLO , 0, "Unknown Core 45nm" }, { 6, 7, -1, -1, 23, 1, -1, -1, CORE_DUO , 0, "Unknown Core 45nm" }, - { 6, 7, -1, -1, 23, 2, 1024, -1, WOLFDALE , 0, "Celeron Wolfdale 1M" }, + { 6, 7, -1, -1, 23, 2, 1024, -1, WOLFDALE , 0, "Celeron Wolfdale 1M" }, { 6, 7, -1, -1, 23, 2, 2048, -1, WOLFDALE , 0, "Wolfdale (Core 2 Duo) 2M" }, { 6, 7, -1, -1, 23, 2, 3072, -1, WOLFDALE , 0, "Wolfdale (Core 2 Duo) 3M" }, { 6, 7, -1, -1, 23, 2, 6144, -1, WOLFDALE , 0, "Wolfdale (Core 2 Duo) 6M" }, @@ -271,9 +271,9 @@ const struct match_entry_t cpudb_intel[] = { /* Ivy Bridge CPUs (22nm): */ { 6, 10, -1, -1, 58, -1, -1, -1, XEON , 0, "Ivy Bridge (Xeon)" }, - { 6, 10, -1, -1, 58, 4, -1, -1, CORE_IVY7 , 0, "Ivy Bridge (Core i7)" }, - { 6, 10, -1, -1, 58, 4, -1, -1, CORE_IVY5 , 0, "Ivy Bridge (Core i5)" }, - { 6, 10, -1, -1, 58, 2, -1, -1, CORE_IVY3 , 0, "Ivy Bridge (Core i3)" }, + { 6, 10, -1, -1, 58, 4, -1, -1, CORE_IVY7 , 0, "Ivy Bridge (Core i7)" }, + { 6, 10, -1, -1, 58, 4, -1, -1, CORE_IVY5 , 0, "Ivy Bridge (Core i5)" }, + { 6, 10, -1, -1, 58, 2, -1, -1, CORE_IVY3 , 0, "Ivy Bridge (Core i3)" }, { 6, 10, -1, -1, 58, 2, -1, -1, PENTIUM , 0, "Ivy Bridge (Pentium)" }, { 6, 10, -1, -1, 58, 1, -1, -1, CELERON , 0, "Ivy Bridge (Celeron)" }, { 6, 10, -1, -1, 58, 2, -1, -1, CELERON , 0, "Ivy Bridge (Celeron)" }, @@ -281,12 +281,12 @@ const struct match_entry_t cpudb_intel[] = { /* Haswell CPUs (22nm): */ { 6, 12, -1, -1, 60, -1, -1, -1, XEON , 0, "Haswell (Xeon)" }, - { 6, 12, -1, -1, 60, 4, -1, -1, CORE_HASWELL7 , 0, "Haswell (Core i7)" }, - { 6, 5, -1, -1, 69, 4, -1, -1, CORE_HASWELL7 , 0, "Haswell (Core i7)" }, + { 6, 12, -1, -1, 60, 4, -1, -1, CORE_HASWELL7 , 0, "Haswell (Core i7)" }, + { 6, 5, -1, -1, 69, 4, -1, -1, CORE_HASWELL7 , 0, "Haswell (Core i7)" }, { 6, 12, -1, -1, 60, 4, -1, -1, CORE_HASWELL5 , 0, "Haswell (Core i5)" }, { 6, 5, -1, -1, 69, 4, -1, -1, CORE_HASWELL5 , 0, "Haswell (Core i5)" }, { 6, 12, -1, -1, 60, 2, -1, -1, CORE_HASWELL3 , 0, "Haswell (Core i3)" }, - { 6, 5, -1, -1, 69, 2, -1, -1, CORE_HASWELL3 , 0, "Haswell (Core i3)" }, + { 6, 5, -1, -1, 69, 2, -1, -1, CORE_HASWELL3 , 0, "Haswell (Core i3)" }, { 6, 12, -1, -1, 60, 2, -1, -1, PENTIUM , 0, "Haswell (Pentium)" }, { 6, 12, -1, -1, 60, 2, -1, -1, CELERON , 0, "Haswell (Celeron)" }, { 6, 12, -1, -1, 60, 1, -1, -1, CELERON , 0, "Haswell (Celeron)" }, @@ -315,9 +315,8 @@ const struct match_entry_t cpudb_intel[] = { { 6, 14, -1, -1, 94, 4, -1, -1, PENTIUM , 0, "Skylake (Pentium)" }, /* Itaniums */ - { 7, -1, -1, -1, -1, 1, -1, -1, NO_CODE , 0, "Itanium" }, - { 15, -1, -1, 16, -1, 1, -1, -1, NO_CODE , 0, "Itanium 2" }, - + { 7, -1, -1, -1, -1, 1, -1, -1, NO_CODE , 0, "Itanium" }, + { 15, -1, -1, 16, -1, 1, -1, -1, NO_CODE , 0, "Itanium 2" }, }; From 9f391244bc88bea377f2cac2c4704f02becf7a6f Mon Sep 17 00:00:00 2001 From: Xorg Date: Sat, 11 Mar 2017 16:55:19 +0100 Subject: [PATCH 2/6] Recognise more Intel CPUs, fix Skylake detection --- libcpuid/intel_code_t.h | 10 ++++++---- libcpuid/recog_intel.c | 44 +++++++++++++++++++++++++++++++++++------ 2 files changed, 44 insertions(+), 10 deletions(-) diff --git a/libcpuid/intel_code_t.h b/libcpuid/intel_code_t.h index c50ec9c..3710231 100644 --- a/libcpuid/intel_code_t.h +++ b/libcpuid/intel_code_t.h @@ -77,7 +77,9 @@ CODE(CORE_BROADWELL3), /* 14nm Core-iX, Broadwell */ CODE(CORE_BROADWELL5), CODE(CORE_BROADWELL7), - CODE(CORE_SKYLAKE3), /* 14nm Core-iX, Skylake */ - CODE(CORE_SKYLAKE5), - CODE(CORE_SKYLAKE7), - + CODE(CORE_SKYLAKEI3), /* 14nm Core-iX, Skylake */ + CODE(CORE_SKYLAKEI5), + CODE(CORE_SKYLAKEI7), + CODE(CORE_SKYLAKEM3), + CODE(CORE_SKYLAKEM5), + CODE(CORE_SKYLAKEM7), diff --git a/libcpuid/recog_intel.c b/libcpuid/recog_intel.c index 1b9dcaf..299387c 100644 --- a/libcpuid/recog_intel.c +++ b/libcpuid/recog_intel.c @@ -302,17 +302,33 @@ const struct match_entry_t cpudb_intel[] = { { 6, 13, -1, -1, 61, 2, -1, -1, PENTIUM , 0, "Broadwell-U (Pentium)" }, { 6, 13, -1, -1, 61, 2, -1, -1, CELERON , 0, "Broadwell-U (Celeron)" }, { 6, 13, -1, -1, 61, 2, -1, -1, NA , 0, "Broadwell-U (Core M)" }, + { 6, 15, -1, -1, 79, -1, -1, -1, XEON , 0, "Broadwell-E (Xeon)" }, { 6, 15, -1, -1, 79, 2, -1, -1, CORE_BROADWELL3 , 0, "Broadwell-E (Core i3)" }, { 6, 15, -1, -1, 79, 2, -1, -1, CORE_BROADWELL5 , 0, "Broadwell-E (Core i5)" }, { 6, 15, -1, -1, 79, 4, -1, -1, CORE_BROADWELL5 , 0, "Broadwell-E (Core i5)" }, { 6, 15, -1, -1, 79, 2, -1, -1, CORE_BROADWELL7 , 0, "Broadwell-E (Core i7)" }, { 6, 15, -1, -1, 79, 4, -1, -1, CORE_BROADWELL7 , 0, "Broadwell-E (Core i7)" }, - + /* Skylake CPUs (14nm): */ - { 6, 14, -1, -1, 94, 4, -1, -1, CORE_BROADWELL7 , 0, "Skylake (Core i7)" }, - { 6, 14, -1, -1, 94, 4, -1, -1, CORE_BROADWELL5 , 0, "Skylake (Core i5)" }, - { 6, 14, -1, -1, 94, 4, -1, -1, CORE_BROADWELL3 , 0, "Skylake (Core i3)" }, - { 6, 14, -1, -1, 94, 4, -1, -1, PENTIUM , 0, "Skylake (Pentium)" }, + { 6, 14, -1, -1, 94, -1, -1, -1, XEON , 0, "Skylake (Xeon)" }, + { 6, 14, -1, -1, 94, 4, -1, -1, CORE_SKYLAKEI7 , 0, "Skylake (Core i7)" }, + { 6, 14, -1, -1, 94, 4, -1, -1, CORE_SKYLAKEI5 , 0, "Skylake (Core i5)" }, + { 6, 14, -1, -1, 94, 2, -1, -1, CORE_SKYLAKEI3 , 0, "Skylake (Core i3)" }, + { 6, 14, -1, -1, 94, 2, -1, -1, PENTIUM , 0, "Skylake (Pentium)" }, + { 6, 14, -1, -1, 78, 2, -1, -1, PENTIUM , 0, "Skylake (Pentium)" }, + { 6, 14, -1, -1, 94, 2, -1, -1, CELERON , 0, "Skylake (Celeron)" }, + { 6, 14, -1, -1, 78, 2, -1, -1, CELERON , 0, "Skylake (Celeron)" }, + { 6, 14, -1, -1, 78, 2, -1, -1, CORE_SKYLAKEM7 , 0, "Skylake (Core m7)" }, + { 6, 14, -1, -1, 78, 2, -1, -1, CORE_SKYLAKEM5 , 0, "Skylake (Core m5)" }, + { 6, 14, -1, -1, 78, 2, -1, -1, CORE_SKYLAKEM3 , 0, "Skylake (Core m3)" }, + + /* Kaby Lake CPUs (14nm): */ + { 6, 14, -1, -1, 158, 4, -1, -1, CORE_SKYLAKEI7 , 0, "Kaby Lake (Core i7)" }, + { 6, 14, -1, -1, 158, 4, -1, -1, CORE_SKYLAKEI5 , 0, "Kaby Lake (Core i5)" }, + { 6, 14, -1, -1, 158, 2, -1, -1, CORE_SKYLAKEI3 , 0, "Kaby Lake (Core i3)" }, + { 6, 14, -1, -1, 158, 2, -1, -1, PENTIUM , 0, "Kaby Lake (Pentium)" }, + { 6, 14, -1, -1, 158, 2, -1, -1, CELERON , 0, "Kaby Lake (Celeron)" }, + { 6, 14, -1, -1, 158, 2, -1, -1, CORE_SKYLAKEM3 , 0, "Kaby Lake (Core m3)" }, /* Itaniums */ { 7, -1, -1, -1, -1, 1, -1, -1, NO_CODE , 0, "Itanium" }, @@ -653,7 +669,23 @@ static intel_code_t get_brand_code(struct cpu_id_t* data) /* if it has RTM, then it is at least a Broadwell-E or Skylake */ if (data->flags[CPU_FEATURE_RDSEED]) core_ix_base = CORE_BROADWELL3; - + /* if it has SGX, then it is at least Skylake */ + if (data->sgx.present) + core_ix_base = CORE_SKYLAKEI3; + + switch (bs[i + 9]) { + case '3': code = core_ix_base + 0; break; + case '5': code = core_ix_base + 1; break; + case '7': code = core_ix_base + 2; break; + } + } + if ((i = match_pattern(bs, "Core(TM) m[357]")) != 0) { + /* Core m3, Core m5 or Core m7 */ + need_matchtable = 0; + + /* introduced in Skylake: Core m3 6Y30, Core m5 6Y54, Core m5 6Y57 and Core m7 6Y75 */ + core_ix_base = CORE_SKYLAKEM3; + switch (bs[i + 9]) { case '3': code = core_ix_base + 0; break; case '5': code = core_ix_base + 1; break; From 76d5892bbee7d88e97f17dbaa78726035fca18ce Mon Sep 17 00:00:00 2001 From: Xorg Date: Sat, 11 Mar 2017 19:19:02 +0100 Subject: [PATCH 3/6] Reorganise AMD CPUs/APUs by family, fix wrong extended family --- libcpuid/recog_amd.c | 82 ++++++++++++++++++++++---------------------- 1 file changed, 41 insertions(+), 41 deletions(-) diff --git a/libcpuid/recog_amd.c b/libcpuid/recog_amd.c index 26f10f5..d75d394 100644 --- a/libcpuid/recog_amd.c +++ b/libcpuid/recog_amd.c @@ -184,8 +184,8 @@ const struct match_entry_t cpudb_amd[] = { { 15, -1, -1, 15, 0x68, 2, 512, -1, TURION_X2 , 0, "Turion X2 (Tyler/512K)" }, { 15, -1, -1, 17, 3, 2, 512, -1, TURION_X2 , 0, "Turion X2 (Griffin/512K)" }, { 15, -1, -1, 17, 3, 2, 1024, -1, TURION_X2 , 0, "Turion X2 (Griffin/1024K)" }, - - /* K9 Architecture */ + + /* K10 Architecture (2007) */ { 15, -1, -1, 16, -1, 1, -1, -1, PHENOM , 0, "Unknown AMD Phenom" }, { 15, 2, -1, 16, -1, 1, -1, -1, PHENOM , 0, "Phenom" }, { 15, 2, -1, 16, -1, 3, -1, -1, PHENOM , 0, "Phenom X3 (Toliman)" }, @@ -206,66 +206,66 @@ const struct match_entry_t cpudb_amd[] = { { 15, 5, -1, 16, 5, 4, 512, -1, PHENOM2 , 0, "Phenom II X4 (Deneb)" }, { 15, 4, -1, 16, 10, 4, 512, -1, PHENOM2 , 0, "Phenom II X4 (Zosma)" }, { 15, 4, -1, 16, 10, 6, 512, -1, PHENOM2 , 0, "Phenom II X6 (Thuban)" }, - + /* Athlon II derivates: */ { 15, 6, -1, 16, 6, 2, 512, -1, ATHLON , 0, "Athlon II (Champlain)" }, { 15, 6, -1, 16, 6, 2, 512, -1, ATHLON_64_X2 , 0, "Athlon II X2 (Regor)" }, { 15, 6, -1, 16, 6, 2, 1024, -1, ATHLON_64_X2 , 0, "Athlon II X2 (Regor)" }, { 15, 5, -1, 16, 5, 3, 512, -1, ATHLON_64_X3 , 0, "Athlon II X3 (Rana)" }, { 15, 5, -1, 16, 5, 4, 512, -1, ATHLON_64_X4 , 0, "Athlon II X4 (Propus)" }, - - /* 2011 CPUs: K10 architecture: Llano */ + /* Llano APUs (2011): */ { 15, 1, -1, 18, 1, 2, 512, -1, FUSION_EA , 0, "Llano X2" }, { 15, 1, -1, 18, 1, 2, 1024, -1, FUSION_EA , 0, "Llano X2" }, { 15, 1, -1, 18, 1, 3, 1024, -1, FUSION_EA , 0, "Llano X3" }, { 15, 1, -1, 18, 1, 4, 1024, -1, FUSION_EA , 0, "Llano X4" }, - /* 2011 CPUs: Bobcat architecture: Ontario, Zacate, Desna, Hondo */ + + /* Family 14h: Bobcat Architecture (2011) */ { 15, 2, -1, 20, -1, 1, 512, -1, FUSION_C , 0, "Brazos Ontario" }, { 15, 2, -1, 20, -1, 2, 512, -1, FUSION_C , 0, "Brazos Ontario (Dual-core)" }, { 15, 1, -1, 20, -1, 1, 512, -1, FUSION_E , 0, "Brazos Zacate" }, { 15, 1, -1, 20, -1, 2, 512, -1, FUSION_E , 0, "Brazos Zacate (Dual-core)" }, { 15, 2, -1, 20, -1, 2, 512, -1, FUSION_Z , 0, "Brazos Desna (Dual-core)" }, - /* 2012 CPUs: Piledriver architecture: Trinity and Richland */ - { 15, 0, -1, 21, 10, 2, 1024, -1, FUSION_A , 0, "Trinity X2" }, - { 15, 0, -1, 21, 16, 2, 1024, -1, FUSION_A , 0, "Trinity X2" }, - { 15, 0, -1, 21, 10, 4, 1024, -1, FUSION_A , 0, "Trinity X4" }, - { 15, 0, -1, 21, 16, 4, 1024, -1, FUSION_A , 0, "Trinity X4" }, - { 15, 3, -1, 21, 13, 2, 1024, -1, FUSION_A , 0, "Richland X2" }, - { 15, 3, -1, 21, 13, 4, 1024, -1, FUSION_A , 0, "Richland X4" }, - /* 2013 CPUs: Jaguar architecture: Kabini and Temash */ - { 15, 0, -1, 22, 0, 2, 1024, -1, FUSION_A , 0, "Kabini X2" }, - { 15, 0, -1, 22, 0, 4, 1024, -1, FUSION_A , 0, "Kabini X4" }, - /* 2014 CPUs: Steamroller architecture: Kaveri */ - { 15, 0, -1, 21, 30, 2, 1024, -1, FUSION_A , 0, "Kaveri X2" }, - { 15, 0, -1, 21, 30, 4, 1024, -1, FUSION_A , 0, "Kaveri X4" }, - /* 2014 CPUs: Puma architecture: Beema and Mullins */ - { 15, 0, -1, 22, 30, 2, 1024, -1, FUSION_E , 0, "Mullins X2" }, - { 15, 0, -1, 22, 30, 4, 1024, -1, FUSION_A , 0, "Mullins X4" }, - /* 2015 CPUs: Excavator architecture: Carrizo */ - { 15, 1, -1, 21, 60, 2, 1024, -1, FUSION_A , 0, "Carrizo X2" }, - { 15, 1, -1, 21, 60, 4, 1024, -1, FUSION_A , 0, "Carrizo X4" }, - /* 2015 CPUs: Steamroller architecture: Godavari */ - //TODO - /* 2016 CPUs: Excavator architecture: Bristol Ridge */ - //TODO - - /* Newer Opterons: */ - { 15, 9, -1, 22, 9, 8, -1, -1, OPTERON_GENERIC , 0, "Magny-Cours Opteron" }, - - /* Bulldozer CPUs: */ + + /* Family 15h: Bulldozer Architecture (2011) */ { 15, -1, -1, 21, 0, 4, 2048, -1, NO_CODE , 0, "Bulldozer X2" }, { 15, -1, -1, 21, 1, 4, 2048, -1, NO_CODE , 0, "Bulldozer X2" }, { 15, -1, -1, 21, 1, 6, 2048, -1, NO_CODE , 0, "Bulldozer X3" }, { 15, -1, -1, 21, 1, 8, 2048, -1, NO_CODE , 0, "Bulldozer X4" }, - /* Piledriver CPUs: */ + /* 2nd-gen, Piledriver core (2012): */ { 15, -1, -1, 21, 2, 4, 2048, -1, NO_CODE , 0, "Vishera X2" }, { 15, -1, -1, 21, 2, 6, 2048, -1, NO_CODE , 0, "Vishera X3" }, { 15, -1, -1, 21, 2, 8, 2048, -1, NO_CODE , 0, "Vishera X4" }, - /* Steamroller CPUs: */ - //TODO - /* Excavator CPUs: */ - //TODO - /* Zen CPUs: */ - //TODO + { 15, 0, -1, 21, 16, 2, 1024, -1, FUSION_A , 0, "Trinity X2" }, + { 15, 0, -1, 21, 16, 4, 1024, -1, FUSION_A , 0, "Trinity X4" }, + { 15, 3, -1, 21, 19, 2, 1024, -1, FUSION_A , 0, "Richland X2" }, + { 15, 3, -1, 21, 19, 4, 1024, -1, FUSION_A , 0, "Richland X4" }, + /* 3rd-gen, Steamroller core (2014): */ + { 15, 0, -1, 21, 48, 2, 1024, -1, FUSION_A , 0, "Kaveri X2" }, + { 15, 0, -1, 21, 48, 4, 1024, -1, FUSION_A , 0, "Kaveri X4" }, + { 15, 8, -1, 21, 56, 4, 1024, -1, FUSION_A , 0, "Godavari X4" }, + /* 4th-gen, Excavator core (2015): */ + { 15, 1, -1, 21, 96, 2, 1024, -1, FUSION_A , 0, "Carrizo X2" }, + { 15, 1, -1, 21, 96, 4, 1024, -1, FUSION_A , 0, "Carrizo X4" }, + { 15, 5, -1, 21, 101, 2, 1024, -1, FUSION_A , 0, "Bristol Ridge X2" }, + { 15, 5, -1, 21, 101, 4, 1024, -1, FUSION_A , 0, "Bristol Ridge X4" }, + { 15, 0, -1, 21, 112, 2, 1024, -1, FUSION_A , 0, "Stoney Ridge X2" }, + { 15, 0, -1, 21, 112, 2, 1024, -1, FUSION_E , 0, "Stoney Ridge X2" }, + + /* Family 16h: Jaguar Architecture (2013) */ + { 15, 0, -1, 22, 0, 2, 1024, -1, FUSION_A , 0, "Kabini X2" }, + { 15, 0, -1, 22, 0, 4, 1024, -1, FUSION_A , 0, "Kabini X4" }, + /* 2nd-gen, Puma core (2013): */ + { 15, 0, -1, 22, 48, 2, 1024, -1, FUSION_E , 0, "Mullins X2" }, + { 15, 0, -1, 22, 48, 4, 1024, -1, FUSION_A , 0, "Mullins X4" }, + + /* Family 17h: Zen Architecture (2017) */ + //{ 15, -1, -1, 23, 1, 8, -1, -1, NO_CODE , 0, "Ryzen 7" }, //FIXME + //{ 15, -1, -1, 23, 1, 6, -1, -1, NO_CODE , 0, "Ryzen 5" }, //TBA + //{ 15, -1, -1, 23, 1, 4, -1, -1, NO_CODE , 0, "Ryzen 5" }, //TBA + //{ 15, -1, -1, 23, 1, 4, -1, -1, NO_CODE , 0, "Ryzen 3" }, //TBA + //{ 15, -1, -1, 23, 1, 4, -1, -1, NO_CODE , 0, "Raven Ridge" }, //TBA + + /* Newer Opterons: */ + { 15, 9, -1, 22, 9, 8, -1, -1, OPTERON_GENERIC , 0, "Magny-Cours Opteron" }, }; From 8f94a9d88ac8acaeb931dc1d18d4bd6a978b5753 Mon Sep 17 00:00:00 2001 From: Xorg Date: Sun, 12 Mar 2017 09:29:49 +0100 Subject: [PATCH 4/6] Partially revert 9f391244bc88bea377f2cac2c4704f02becf7a6f about Skylake Core i[357] changes --- libcpuid/intel_code_t.h | 6 +++--- libcpuid/recog_intel.c | 15 ++++++--------- 2 files changed, 9 insertions(+), 12 deletions(-) diff --git a/libcpuid/intel_code_t.h b/libcpuid/intel_code_t.h index 3710231..9b272f2 100644 --- a/libcpuid/intel_code_t.h +++ b/libcpuid/intel_code_t.h @@ -77,9 +77,9 @@ CODE(CORE_BROADWELL3), /* 14nm Core-iX, Broadwell */ CODE(CORE_BROADWELL5), CODE(CORE_BROADWELL7), - CODE(CORE_SKYLAKEI3), /* 14nm Core-iX, Skylake */ - CODE(CORE_SKYLAKEI5), - CODE(CORE_SKYLAKEI7), + CODE(CORE_SKYLAKE3), /* 14nm Core-iX, Skylake */ + CODE(CORE_SKYLAKE5), + CODE(CORE_SKYLAKE7), CODE(CORE_SKYLAKEM3), CODE(CORE_SKYLAKEM5), CODE(CORE_SKYLAKEM7), diff --git a/libcpuid/recog_intel.c b/libcpuid/recog_intel.c index 299387c..9e1bc4d 100644 --- a/libcpuid/recog_intel.c +++ b/libcpuid/recog_intel.c @@ -311,9 +311,9 @@ const struct match_entry_t cpudb_intel[] = { /* Skylake CPUs (14nm): */ { 6, 14, -1, -1, 94, -1, -1, -1, XEON , 0, "Skylake (Xeon)" }, - { 6, 14, -1, -1, 94, 4, -1, -1, CORE_SKYLAKEI7 , 0, "Skylake (Core i7)" }, - { 6, 14, -1, -1, 94, 4, -1, -1, CORE_SKYLAKEI5 , 0, "Skylake (Core i5)" }, - { 6, 14, -1, -1, 94, 2, -1, -1, CORE_SKYLAKEI3 , 0, "Skylake (Core i3)" }, + { 6, 14, -1, -1, 94, 4, -1, -1, CORE_BROADWELL7 , 0, "Skylake (Core i7)" }, + { 6, 14, -1, -1, 94, 4, -1, -1, CORE_BROADWELL5 , 0, "Skylake (Core i5)" }, + { 6, 14, -1, -1, 94, 2, -1, -1, CORE_BROADWELL3 , 0, "Skylake (Core i3)" }, { 6, 14, -1, -1, 94, 2, -1, -1, PENTIUM , 0, "Skylake (Pentium)" }, { 6, 14, -1, -1, 78, 2, -1, -1, PENTIUM , 0, "Skylake (Pentium)" }, { 6, 14, -1, -1, 94, 2, -1, -1, CELERON , 0, "Skylake (Celeron)" }, @@ -323,9 +323,9 @@ const struct match_entry_t cpudb_intel[] = { { 6, 14, -1, -1, 78, 2, -1, -1, CORE_SKYLAKEM3 , 0, "Skylake (Core m3)" }, /* Kaby Lake CPUs (14nm): */ - { 6, 14, -1, -1, 158, 4, -1, -1, CORE_SKYLAKEI7 , 0, "Kaby Lake (Core i7)" }, - { 6, 14, -1, -1, 158, 4, -1, -1, CORE_SKYLAKEI5 , 0, "Kaby Lake (Core i5)" }, - { 6, 14, -1, -1, 158, 2, -1, -1, CORE_SKYLAKEI3 , 0, "Kaby Lake (Core i3)" }, + { 6, 14, -1, -1, 158, 4, -1, -1, CORE_BROADWELL7 , 0, "Kaby Lake (Core i7)" }, + { 6, 14, -1, -1, 158, 4, -1, -1, CORE_BROADWELL5 , 0, "Kaby Lake (Core i5)" }, + { 6, 14, -1, -1, 158, 2, -1, -1, CORE_BROADWELL3 , 0, "Kaby Lake (Core i3)" }, { 6, 14, -1, -1, 158, 2, -1, -1, PENTIUM , 0, "Kaby Lake (Pentium)" }, { 6, 14, -1, -1, 158, 2, -1, -1, CELERON , 0, "Kaby Lake (Celeron)" }, { 6, 14, -1, -1, 158, 2, -1, -1, CORE_SKYLAKEM3 , 0, "Kaby Lake (Core m3)" }, @@ -669,9 +669,6 @@ static intel_code_t get_brand_code(struct cpu_id_t* data) /* if it has RTM, then it is at least a Broadwell-E or Skylake */ if (data->flags[CPU_FEATURE_RDSEED]) core_ix_base = CORE_BROADWELL3; - /* if it has SGX, then it is at least Skylake */ - if (data->sgx.present) - core_ix_base = CORE_SKYLAKEI3; switch (bs[i + 9]) { case '3': code = core_ix_base + 0; break; From 803a0624794ab6cea86fba3b9af34322b321e0d9 Mon Sep 17 00:00:00 2001 From: Xorg Date: Sun, 12 Mar 2017 09:32:28 +0100 Subject: [PATCH 5/6] Doesn't specify l2_cache value for Llano CPUs and newer --- libcpuid/recog_amd.c | 65 ++++++++++++++++++++++---------------------- 1 file changed, 32 insertions(+), 33 deletions(-) diff --git a/libcpuid/recog_amd.c b/libcpuid/recog_amd.c index d75d394..cb95066 100644 --- a/libcpuid/recog_amd.c +++ b/libcpuid/recog_amd.c @@ -213,49 +213,48 @@ const struct match_entry_t cpudb_amd[] = { { 15, 5, -1, 16, 5, 3, 512, -1, ATHLON_64_X3 , 0, "Athlon II X3 (Rana)" }, { 15, 5, -1, 16, 5, 4, 512, -1, ATHLON_64_X4 , 0, "Athlon II X4 (Propus)" }, /* Llano APUs (2011): */ - { 15, 1, -1, 18, 1, 2, 512, -1, FUSION_EA , 0, "Llano X2" }, - { 15, 1, -1, 18, 1, 2, 1024, -1, FUSION_EA , 0, "Llano X2" }, - { 15, 1, -1, 18, 1, 3, 1024, -1, FUSION_EA , 0, "Llano X3" }, - { 15, 1, -1, 18, 1, 4, 1024, -1, FUSION_EA , 0, "Llano X4" }, + { 15, 1, -1, 18, 1, 2, -1, -1, FUSION_EA , 0, "Llano X2" }, + { 15, 1, -1, 18, 1, 3, -1, -1, FUSION_EA , 0, "Llano X3" }, + { 15, 1, -1, 18, 1, 4, -1, -1, FUSION_EA , 0, "Llano X4" }, /* Family 14h: Bobcat Architecture (2011) */ - { 15, 2, -1, 20, -1, 1, 512, -1, FUSION_C , 0, "Brazos Ontario" }, - { 15, 2, -1, 20, -1, 2, 512, -1, FUSION_C , 0, "Brazos Ontario (Dual-core)" }, - { 15, 1, -1, 20, -1, 1, 512, -1, FUSION_E , 0, "Brazos Zacate" }, - { 15, 1, -1, 20, -1, 2, 512, -1, FUSION_E , 0, "Brazos Zacate (Dual-core)" }, - { 15, 2, -1, 20, -1, 2, 512, -1, FUSION_Z , 0, "Brazos Desna (Dual-core)" }, + { 15, 2, -1, 20, -1, 1, -1, -1, FUSION_C , 0, "Brazos Ontario" }, + { 15, 2, -1, 20, -1, 2, -1, -1, FUSION_C , 0, "Brazos Ontario (Dual-core)" }, + { 15, 1, -1, 20, -1, 1, -1, -1, FUSION_E , 0, "Brazos Zacate" }, + { 15, 1, -1, 20, -1, 2, -1, -1, FUSION_E , 0, "Brazos Zacate (Dual-core)" }, + { 15, 2, -1, 20, -1, 2, -1, -1, FUSION_Z , 0, "Brazos Desna (Dual-core)" }, /* Family 15h: Bulldozer Architecture (2011) */ - { 15, -1, -1, 21, 0, 4, 2048, -1, NO_CODE , 0, "Bulldozer X2" }, - { 15, -1, -1, 21, 1, 4, 2048, -1, NO_CODE , 0, "Bulldozer X2" }, - { 15, -1, -1, 21, 1, 6, 2048, -1, NO_CODE , 0, "Bulldozer X3" }, - { 15, -1, -1, 21, 1, 8, 2048, -1, NO_CODE , 0, "Bulldozer X4" }, + { 15, -1, -1, 21, 0, 4, -1, -1, NO_CODE , 0, "Bulldozer X2" }, + { 15, -1, -1, 21, 1, 4, -1, -1, NO_CODE , 0, "Bulldozer X2" }, + { 15, -1, -1, 21, 1, 6, -1, -1, NO_CODE , 0, "Bulldozer X3" }, + { 15, -1, -1, 21, 1, 8, -1, -1, NO_CODE , 0, "Bulldozer X4" }, /* 2nd-gen, Piledriver core (2012): */ - { 15, -1, -1, 21, 2, 4, 2048, -1, NO_CODE , 0, "Vishera X2" }, - { 15, -1, -1, 21, 2, 6, 2048, -1, NO_CODE , 0, "Vishera X3" }, - { 15, -1, -1, 21, 2, 8, 2048, -1, NO_CODE , 0, "Vishera X4" }, - { 15, 0, -1, 21, 16, 2, 1024, -1, FUSION_A , 0, "Trinity X2" }, - { 15, 0, -1, 21, 16, 4, 1024, -1, FUSION_A , 0, "Trinity X4" }, - { 15, 3, -1, 21, 19, 2, 1024, -1, FUSION_A , 0, "Richland X2" }, - { 15, 3, -1, 21, 19, 4, 1024, -1, FUSION_A , 0, "Richland X4" }, + { 15, -1, -1, 21, 2, 4, -1, -1, NO_CODE , 0, "Vishera X2" }, + { 15, -1, -1, 21, 2, 6, -1, -1, NO_CODE , 0, "Vishera X3" }, + { 15, -1, -1, 21, 2, 8, -1, -1, NO_CODE , 0, "Vishera X4" }, + { 15, 0, -1, 21, 16, 2, -1, -1, FUSION_A , 0, "Trinity X2" }, + { 15, 0, -1, 21, 16, 4, -1, -1, FUSION_A , 0, "Trinity X4" }, + { 15, 3, -1, 21, 19, 2, -1, -1, FUSION_A , 0, "Richland X2" }, + { 15, 3, -1, 21, 19, 4, -1, -1, FUSION_A , 0, "Richland X4" }, /* 3rd-gen, Steamroller core (2014): */ - { 15, 0, -1, 21, 48, 2, 1024, -1, FUSION_A , 0, "Kaveri X2" }, - { 15, 0, -1, 21, 48, 4, 1024, -1, FUSION_A , 0, "Kaveri X4" }, - { 15, 8, -1, 21, 56, 4, 1024, -1, FUSION_A , 0, "Godavari X4" }, + { 15, 0, -1, 21, 48, 2, -1, -1, FUSION_A , 0, "Kaveri X2" }, + { 15, 0, -1, 21, 48, 4, -1, -1, FUSION_A , 0, "Kaveri X4" }, + { 15, 8, -1, 21, 56, 4, -1, -1, FUSION_A , 0, "Godavari X4" }, /* 4th-gen, Excavator core (2015): */ - { 15, 1, -1, 21, 96, 2, 1024, -1, FUSION_A , 0, "Carrizo X2" }, - { 15, 1, -1, 21, 96, 4, 1024, -1, FUSION_A , 0, "Carrizo X4" }, - { 15, 5, -1, 21, 101, 2, 1024, -1, FUSION_A , 0, "Bristol Ridge X2" }, - { 15, 5, -1, 21, 101, 4, 1024, -1, FUSION_A , 0, "Bristol Ridge X4" }, - { 15, 0, -1, 21, 112, 2, 1024, -1, FUSION_A , 0, "Stoney Ridge X2" }, - { 15, 0, -1, 21, 112, 2, 1024, -1, FUSION_E , 0, "Stoney Ridge X2" }, + { 15, 1, -1, 21, 96, 2, -1, -1, FUSION_A , 0, "Carrizo X2" }, + { 15, 1, -1, 21, 96, 4, -1, -1, FUSION_A , 0, "Carrizo X4" }, + { 15, 5, -1, 21, 101, 2, -1, -1, FUSION_A , 0, "Bristol Ridge X2" }, + { 15, 5, -1, 21, 101, 4, -1, -1, FUSION_A , 0, "Bristol Ridge X4" }, + { 15, 0, -1, 21, 112, 2, -1, -1, FUSION_A , 0, "Stoney Ridge X2" }, + { 15, 0, -1, 21, 112, 2, -1, -1, FUSION_E , 0, "Stoney Ridge X2" }, /* Family 16h: Jaguar Architecture (2013) */ - { 15, 0, -1, 22, 0, 2, 1024, -1, FUSION_A , 0, "Kabini X2" }, - { 15, 0, -1, 22, 0, 4, 1024, -1, FUSION_A , 0, "Kabini X4" }, + { 15, 0, -1, 22, 0, 2, -1, -1, FUSION_A , 0, "Kabini X2" }, + { 15, 0, -1, 22, 0, 4, -1, -1, FUSION_A , 0, "Kabini X4" }, /* 2nd-gen, Puma core (2013): */ - { 15, 0, -1, 22, 48, 2, 1024, -1, FUSION_E , 0, "Mullins X2" }, - { 15, 0, -1, 22, 48, 4, 1024, -1, FUSION_A , 0, "Mullins X4" }, + { 15, 0, -1, 22, 48, 2, -1, -1, FUSION_E , 0, "Mullins X2" }, + { 15, 0, -1, 22, 48, 4, -1, -1, FUSION_A , 0, "Mullins X4" }, /* Family 17h: Zen Architecture (2017) */ //{ 15, -1, -1, 23, 1, 8, -1, -1, NO_CODE , 0, "Ryzen 7" }, //FIXME From bb4141a25a0942f2e40b250765b3598df8745be6 Mon Sep 17 00:00:00 2001 From: Xorg Date: Sun, 12 Mar 2017 09:34:26 +0100 Subject: [PATCH 6/6] Enforce Python 2.7 in tests --- tests/run_tests.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/run_tests.py b/tests/run_tests.py index 5e5c97e..1b4f16c 100755 --- a/tests/run_tests.py +++ b/tests/run_tests.py @@ -1,4 +1,4 @@ -#!/usr/bin/python +#!/usr/bin/env python2.7 from __future__ import with_statement import os, sys, re, random