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https://github.com/anrieff/libcpuid
synced 2024-12-16 16:35:45 +00:00
Better support for AVX, AVX2, BMI1 and BMI2 instruction set detection.
- Detect AVX and AVX2 on both Intel and AMD CPUs - Detect BMI1 and BMI2 instruction sets (BMI2 is only on Haswell, BMI1 is also present on Bulldozers). - Fix tests to reflect changes.
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325904f498
commit
046d2ca2ab
6 changed files with 16 additions and 10 deletions
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@ -189,8 +189,14 @@ static void load_features_common(struct cpu_raw_data_t* raw, struct cpu_id_t* da
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{ 19, CPU_FEATURE_SSE4_1 },
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{ 21, CPU_FEATURE_X2APIC },
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{ 23, CPU_FEATURE_POPCNT },
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{ 28, CPU_FEATURE_AVX },
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{ 29, CPU_FEATURE_F16C },
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};
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const struct feature_map_t matchtable_ebx7[] = {
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{ 3, CPU_FEATURE_BMI1 },
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{ 5, CPU_FEATURE_AVX2 },
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{ 8, CPU_FEATURE_BMI2 },
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};
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const struct feature_map_t matchtable_edx81[] = {
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{ 11, CPU_FEATURE_SYSCALL },
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{ 27, CPU_FEATURE_RDTSCP },
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@ -206,6 +212,9 @@ static void load_features_common(struct cpu_raw_data_t* raw, struct cpu_id_t* da
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match_features(matchtable_edx1, COUNT_OF(matchtable_edx1), raw->basic_cpuid[1][3], data);
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match_features(matchtable_ecx1, COUNT_OF(matchtable_ecx1), raw->basic_cpuid[1][2], data);
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}
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if (raw->basic_cpuid[0][0] >= 7) {
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match_features(matchtable_ebx7, COUNT_OF(matchtable_ebx7), raw->basic_cpuid[7][1], data);
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}
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if (raw->ext_cpuid[0][0] >= 0x80000001) {
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match_features(matchtable_edx81, COUNT_OF(matchtable_edx81), raw->ext_cpuid[1][3], data);
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match_features(matchtable_ecx81, COUNT_OF(matchtable_ecx81), raw->ext_cpuid[1][2], data);
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@ -578,6 +587,8 @@ const char* cpu_feature_str(cpu_feature_t feature)
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{ CPU_FEATURE_PFI, "pfi" },
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{ CPU_FEATURE_PA, "pa" },
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{ CPU_FEATURE_AVX2, "avx2" },
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{ CPU_FEATURE_BMI1, "bmi1" },
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{ CPU_FEATURE_BMI2, "bmi2" },
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};
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unsigned i, n = COUNT_OF(matchtable);
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if (n != NUM_CPU_FEATURES) {
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@ -355,6 +355,8 @@ typedef enum {
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CPU_FEATURE_PFI, /*!< Processor Feedback Interface support */
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CPU_FEATURE_PA, /*!< Processor accumulator */
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CPU_FEATURE_AVX2, /*!< AVX2 instructions */
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CPU_FEATURE_BMI1, /*!< BMI1 instructions */
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CPU_FEATURE_BMI2, /*!< BMI2 instructions */
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/* termination: */
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NUM_CPU_FEATURES,
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} cpu_feature_t;
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@ -359,12 +359,8 @@ static void load_intel_features(struct cpu_raw_data_t* raw, struct cpu_id_t* dat
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{ 25, CPU_FEATURE_AES },
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{ 26, CPU_FEATURE_XSAVE },
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{ 27, CPU_FEATURE_OSXSAVE },
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{ 28, CPU_FEATURE_AVX },
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{ 30, CPU_FEATURE_RDRAND },
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};
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const struct feature_map_t matchtable_ebx7[] = {
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{ 5, CPU_FEATURE_AVX2 },
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};
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const struct feature_map_t matchtable_edx81[] = {
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{ 20, CPU_FEATURE_XD },
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};
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@ -372,9 +368,6 @@ static void load_intel_features(struct cpu_raw_data_t* raw, struct cpu_id_t* dat
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match_features(matchtable_edx1, COUNT_OF(matchtable_edx1), raw->basic_cpuid[1][3], data);
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match_features(matchtable_ecx1, COUNT_OF(matchtable_ecx1), raw->basic_cpuid[1][2], data);
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}
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if (raw->basic_cpuid[0][0] >= 7) {
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match_features(matchtable_ebx7, COUNT_OF(matchtable_ebx7), raw->basic_cpuid[7][1], data);
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}
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if (raw->ext_cpuid[0][0] >= 1) {
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match_features(matchtable_edx81, COUNT_OF(matchtable_edx81), raw->ext_cpuid[1][3], data);
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}
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@ -90,4 +90,4 @@ intel_fn11[3]=00000000 00000000 00000000 00000000
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64
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128 (authoritative)
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Bulldozer X4
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fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni monitor ssse3 cx16 sse4_1 syscall popcnt mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd 100mhzsteps hwpstate constant_tsc xop fma4 cpb
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fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni monitor ssse3 cx16 sse4_1 syscall popcnt avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd 100mhzsteps hwpstate constant_tsc xop fma4 cpb
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@ -90,4 +90,4 @@ intel_fn11[3]=00000000 00000000 00000000 00000000
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64
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128 (authoritative)
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Vishera X4
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fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni monitor ssse3 cx16 sse4_1 syscall popcnt mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd 100mhzsteps hwpstate constant_tsc xop fma3 fma4 f16c cpb aperfmperf
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fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni monitor ssse3 cx16 sse4_1 syscall popcnt avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd 100mhzsteps hwpstate constant_tsc xop fma3 fma4 f16c cpb aperfmperf bmi1
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@ -90,4 +90,4 @@ intel_fn11[3]=00000000 00000000 00000003 00000001
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64
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128 (non-authoritative)
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Haswell (Core i3)
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fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 syscall xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm constant_tsc fma3 f16c rdrand avx2
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fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 syscall xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm constant_tsc fma3 f16c rdrand avx2 bmi1 bmi2
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