From 074c7c9f77e9317a7e7a33193c0d97fc207b4dc3 Mon Sep 17 00:00:00 2001 From: Veselin Georgiev Date: Tue, 18 Nov 2008 12:46:50 +0000 Subject: [PATCH] Finished AMD recognition code porting, needs testing git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@11 3b4be424-7ac5-41d7-8526-f4ddcb85d872 --- libcpuid/cpuid_main.c | 34 +++---- libcpuid/libcpuid.h | 29 +++--- libcpuid/recog_amd.c | 184 ++++++++++++++++++++++++++++++++++- libcpuid/recog_intel.c | 212 ++++++++++++++++++++--------------------- 4 files changed, 319 insertions(+), 140 deletions(-) diff --git a/libcpuid/cpuid_main.c b/libcpuid/cpuid_main.c index 78f7bc0..6f5b7da 100644 --- a/libcpuid/cpuid_main.c +++ b/libcpuid/cpuid_main.c @@ -204,26 +204,26 @@ static int cpuid_basic_identify(struct cpu_raw_data_t* raw, struct cpu_id_t* dat data->vendor_str[12] = 0; /* Determine vendor: */ const struct { cpu_vendor_t vendor; char match[16]; } - matchtable[NUM_VENDORS] = { + matchtable[NUM_CPU_VENDORS] = { /* source: http://www.sandpile.org/ia32/cpuid.htm */ - { INTEL , "GenuineIntel" }, - { AMD , "AuthenticAMD" }, - { CYRIX , "CyrixInstead" }, - { NEXGEN , "NexGenDriven" }, - { TRANSMETA , "GenuineTMx86" }, - { UMC , "UMC UMC UMC " }, - { CENTAUR , "CentaurHauls" }, - { RISE , "RiseRiseRise" }, - { SIS , "SiS SiS SiS " }, - { NSC , "Geode by NSC" }, + { VENDOR_INTEL , "GenuineIntel" }, + { VENDOR_AMD , "AuthenticAMD" }, + { VENDOR_CYRIX , "CyrixInstead" }, + { VENDOR_NEXGEN , "NexGenDriven" }, + { VENDOR_TRANSMETA , "GenuineTMx86" }, + { VENDOR_UMC , "UMC UMC UMC " }, + { VENDOR_CENTAUR , "CentaurHauls" }, + { VENDOR_RISE , "RiseRiseRise" }, + { VENDOR_SIS , "SiS SiS SiS " }, + { VENDOR_NSC , "Geode by NSC" }, }; - data->vendor = UNKNOWN; - for (i = 0; i < NUM_VENDORS; i++) + data->vendor = VENDOR_UNKNOWN; + for (i = 0; i < NUM_CPU_VENDORS; i++) if (!strcmp(data->vendor_str, matchtable[i].match)) { data->vendor = matchtable[i].vendor; break; } - if (data->vendor == UNKNOWN) + if (data->vendor == VENDOR_UNKNOWN) return set_error(ERR_CPU_UNKN); int basic = raw->basic_cpuid[0][0]; if (basic >= 1) { @@ -382,10 +382,10 @@ int cpu_identify(struct cpu_raw_data_t* raw, struct cpu_id_t* data) if ((r = cpuid_basic_identify(raw, data)) < 0) return set_error(r); switch (data->vendor) { - case INTEL: + case VENDOR_INTEL: r = cpuid_identify_intel(raw, data); break; - case AMD: + case VENDOR_AMD: r = cpuid_identify_amd(raw, data); break; default: @@ -473,7 +473,7 @@ const char* cpu_feature_str(cpu_feature_t feature) { CPU_FEATURE_CONSTANT_TSC, "constant_tsc" }, }; unsigned i, n = COUNT_OF(matchtable); - if (n != CPU_NUM_FEATURES) { + if (n != NUM_CPU_FEATURES) { warnf("Warning: incomplete library, feature matchtable size differs from the actual number of features.\n"); } for (i = 0; i < n; i++) diff --git a/libcpuid/libcpuid.h b/libcpuid/libcpuid.h index 279cce6..2d3c031 100644 --- a/libcpuid/libcpuid.h +++ b/libcpuid/libcpuid.h @@ -52,21 +52,21 @@ extern "C" { * @brief CPU vendor, as guessed from the Vendor String. */ enum _cpu_vendor_t { - INTEL = 0, - AMD, - CYRIX, - NEXGEN, - TRANSMETA, - UMC, - CENTAUR, - RISE, - SIS, - NSC, + VENDOR_INTEL = 0, + VENDOR_AMD, + VENDOR_CYRIX, + VENDOR_NEXGEN, + VENDOR_TRANSMETA, + VENDOR_UMC, + VENDOR_CENTAUR, + VENDOR_RISE, + VENDOR_SIS, + VENDOR_NSC, - NUM_VENDORS, - UNKNOWN = -1, + NUM_CPU_VENDORS, + VENDOR_UNKNOWN = -1, }; -#define NUM_VENDORS NUM_VENDORS +#define NUM_CPU_VENDORS NUM_CPU_VENDORS typedef enum _cpu_vendor_t cpu_vendor_t; /** @@ -277,7 +277,6 @@ enum _cpu_feature_t { CPU_FEATURE_XSAVE, /*!< XSAVE/XRSTOR/etc instructions supported */ CPU_FEATURE_OSXSAVE, /*!< non-privileged copy of OSXSAVE supported */ CPU_FEATURE_AVX, /*!< Advanced vector extensions supported */ - // AMD specific: CPU_FEATURE_MMXEXT, /*!< AMD MMX-extended instructions supported */ CPU_FEATURE_3DNOW, /*!< AMD 3DNow! instructions supported */ CPU_FEATURE_3DNOWEXT, /*!< AMD 3DNow! extended instructions supported */ @@ -297,7 +296,7 @@ enum _cpu_feature_t { CPU_FEATURE_WDT, /*!< Watchdog timer support */ CPU_FEATURE_CONSTANT_TSC, /*!< TSC ticks at constant rate */ // termination: - CPU_NUM_FEATURES, + NUM_CPU_FEATURES, }; typedef enum _cpu_feature_t cpu_feature_t; diff --git a/libcpuid/recog_amd.c b/libcpuid/recog_amd.c index 7f52b15..917aa84 100644 --- a/libcpuid/recog_amd.c +++ b/libcpuid/recog_amd.c @@ -24,12 +24,135 @@ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +#include +#include #include "libcpuid.h" #include "recog_amd.h" #include "libcpuid_util.h" -/* -*/ +enum _amd_code_t { + NA, + NO_CODE, + OPTERON_GENERIC, + OPTERON_800, + ATHLON_XP, + ATHLON_XP_BARTON, + ATHLON_XP_M, + ATHLON_XP_M_LV, + ATHLON_64, + ATHLON_64_MANCHESTER, + ATHLON_MP, + MOBILE_ATHLON64, + ATHLON_FX, + DURON, + DURON_MP, + MOBILE_DURON, + SEMPRON, + MOBILE_SEMPRON, + OPTERON_SINGLECORE, + OPTERON_DUALCORE, + OPTERON_800_DUALCORE, + MOBILE_TURION, + ATHLON_64_512K, + ATHLON_64_1024K, + ATHLON_64_X2_512K, + ATHLON_64_X2_1024K, + ATHLON_64_FX, + TURION_64_512K, + TURION_64_1024K, + TURION_X2_512K, + TURION_X2_1024K, + SEMPRON_64_128K, + SEMPRON_64_256K, +}; +typedef enum _amd_code_t amd_code_t; + +const struct match_entry_t cpudb_amd[] = { + { -1, -1, -1, -1, -1, NO_CODE, "Unknown AMD CPU" }, + + /* 486 and the likes */ + { 4, -1, -1, -1, -1, NO_CODE, "Unknown AMD 486" }, + { 4, 3, -1, -1, -1, NO_CODE, "AMD 486DX2" }, + { 4, 7, -1, -1, -1, NO_CODE, "AMD 486DX2WB" }, + { 4, 8, -1, -1, -1, NO_CODE, "AMD 486DX4" }, + { 4, 9, -1, -1, -1, NO_CODE, "AMD 486DX4WB" }, + + /* Pentia clones */ + { 5, -1, -1, -1, -1, NO_CODE, "Unknown AMD 586" }, + { 5, 0, -1, -1, -1, NO_CODE, "K5" }, + { 5, 1, -1, -1, -1, NO_CODE, "K5" }, + { 5, 2, -1, -1, -1, NO_CODE, "K5" }, + { 5, 3, -1, -1, -1, NO_CODE, "K5" }, + + /* The K6 */ + { 5, 6, -1, -1, -1, NO_CODE, "K6" }, + { 5, 7, -1, -1, -1, NO_CODE, "K6" }, + + { 5, 8, -1, -1, -1, NO_CODE, "K6-2" }, + { 5, 9, -1, -1, -1, NO_CODE, "K6-III" }, + { 5, 10, -1, -1, -1, NO_CODE, "Unknown K6" }, + { 5, 11, -1, -1, -1, NO_CODE, "Unknown K6" }, + { 5, 12, -1, -1, -1, NO_CODE, "Unknown K6" }, + { 5, 13, -1, -1, -1, NO_CODE, "K6-2+" }, + + /* Athlon et al. */ + { 6, 1, -1, -1, -1, NO_CODE, "Athlon (Slot-A)" }, + { 6, 2, -1, -1, -1, NO_CODE, "Athlon (Slot-A)" }, + { 6, 3, -1, -1, -1, NO_CODE, "Duron (Spitfire)" }, + { 6, 4, -1, -1, -1, NO_CODE, "Athlon (ThunderBird)" }, + + { 6, 6, -1, -1, -1, NO_CODE, "Unknown Athlon" }, + { 6, 6, -1, -1, -1, ATHLON_64, "Athlon (Palomino)" }, + { 6, 6, -1, -1, -1, ATHLON_MP, "Athlon MP (Palomino)" }, + { 6, 6, -1, -1, -1, DURON, "Duron (Palomino)" }, + { 6, 6, -1, -1, -1, ATHLON_XP, "Athlon XP" }, + + { 6, 7, -1, -1, -1, NO_CODE, "Unknown Athlon XP" }, + { 6, 7, -1, -1, -1, DURON, "Duron (Morgan)" }, + + { 6, 8, -1, -1, -1, NO_CODE, "Athlon XP" }, + { 6, 8, -1, -1, -1, ATHLON_64, "Athlon XP" }, + { 6, 8, -1, -1, -1, ATHLON_XP, "Athlon XP" }, + { 6, 8, -1, -1, -1, DURON, "Duron (Applebred)" }, + { 6, 8, -1, -1, -1, SEMPRON, "Sempron (Thoroughbred)" }, + { 6, 8, -1, -1, -1, SEMPRON_64_128K, "Sempron (Thoroughbred)" }, + { 6, 8, -1, -1, -1, SEMPRON_64_256K, "Sempron (Thoroughbred)" }, + { 6, 8, -1, -1, -1, ATHLON_MP, "Athlon MP (Thoroughbred)" }, + { 6, 8, -1, -1, -1, ATHLON_XP_M, "Mobile Athlon (Thoroughbred)" }, + { 6, 8, -1, -1, -1, ATHLON_XP_M_LV, "Mobile Athlon (Thoroughbred)" }, + + { 6, 10, -1, -1, -1, NO_CODE, "Athlon XP (Barton)" }, + { 6, 10, -1, -1, -1, ATHLON_64, "Athlon XP (Barton)" }, + { 6, 10, -1, -1, -1, ATHLON_XP_BARTON, "Athlon XP (Barton)" }, + { 6, 10, -1, -1, -1, SEMPRON, "Sempron (Barton)" }, + { 6, 10, -1, -1, -1, SEMPRON_64_256K, "Sempron (Barton)" }, + { 6, 10, -1, -1, -1, ATHLON_XP, "Athlon XP" }, + /* ^^ Actually, Thorton, but it's equivallent to Thoroughbred */ + { 6, 10, -1, -1, -1, ATHLON_MP, "Athlon MP (Barton)" }, + { 6, 10, -1, -1, -1, ATHLON_XP_M, "Mobile Athlon (Barton)" }, + { 6, 10, -1, -1, -1, ATHLON_XP_M_LV, "Mobile Athlon (Barton)" }, + + /* K8 Architecture */ + { 15, -1, -1, 0, -1, NO_CODE, "Unknown K8" }, + { 15, -1, -1, 1, -1, NO_CODE, "Unknown K9" }, + + { 15, -1, -1, 0, 0, NO_CODE, "Unknown A64" }, + { 15, -1, -1, 0, 0, OPTERON_SINGLECORE, "Opteron" }, + { 15, -1, -1, 0, 0, OPTERON_DUALCORE, "Opteron (Dual Core)" }, + { 15, -1, -1, 0, 0, ATHLON_64_512K, "Athlon 64 (512K)" }, + { 15, -1, -1, 0, 0, ATHLON_64_1024K, "Athlon 64 (1024K)" }, + { 15, -1, -1, 0, 0, ATHLON_64_X2_512K, "Athlon 64 X2 (512K)" }, + { 15, -1, -1, 0, 0, ATHLON_64_X2_1024K, "Athlon 64 X2 (1024K)" }, + { 15, -1, -1, 0, 0, ATHLON_FX, "Athlon FX" }, + { 15, -1, -1, 0, 0, ATHLON_64_FX, "Athlon 64 FX" }, + { 15, -1, -1, 0, 0, TURION_64_512K, "Turion 64 (512K)" }, + { 15, -1, -1, 0, 0, TURION_64_1024K, "Turion 64 (1024K)" }, + { 15, -1, -1, 0, 0, TURION_X2_512K, "Turion 64 X2 (512K)" }, + { 15, -1, -1, 0, 0, TURION_X2_1024K, "Turion 64 X2 (1024K)" }, + { 15, -1, -1, 0, 0, SEMPRON_64_128K, "A64 Sempron (128K)" }, + { 15, -1, -1, 0, 0, SEMPRON_64_256K, "A64 Sempron (256K)" }, +}; + static void load_amd_features(struct cpu_raw_data_t* raw, struct cpu_id_t* data) { @@ -113,10 +236,67 @@ static void decode_amd_number_of_cores(struct cpu_raw_data_t* raw, struct cpu_id } } +static amd_code_t decode_amd_codename_part1(const char *bs) +{ + if (strstr(bs, "Opteron")) { + if (strstr(bs, "Dual Core")) return OPTERON_DUALCORE; + return OPTERON_SINGLECORE; + } + if (strstr(bs, "Athlon(tm) 64 FX")) return ATHLON_64_FX; + if (strstr(bs, "Athlon(tm) FX")) return ATHLON_FX; + if (strstr(bs, "Athlon(tm) 64")) { + if (strstr(bs, "Dual Core")) return ATHLON_64_X2_512K; + return ATHLON_64_512K; + } + if (strstr(bs, "Turion(tm)")) { + if (strstr(bs, "X2")) + return TURION_X2_512K; + else + return TURION_64_512K; + } + if (strstr(bs, "Sempron(tm)")) return SEMPRON_64_128K; + + if (strstr(bs, "mobile") || strstr(bs, "Mobile")) { + if (strstr(bs, "Athlon(tm) XP-M (LV)")) return ATHLON_XP_M_LV; + if (strstr(bs, "Athlon(tm) XP")) return ATHLON_XP_M; + if (strstr(bs, "Athlon")) return MOBILE_ATHLON64; + if (strstr(bs, "Duron")) return MOBILE_DURON; + } else { + if (strstr(bs, "Athlon(tm) XP")) return ATHLON_XP; + if (strstr(bs, "Athlon(tm) MP")) return ATHLON_MP; + if (strstr(bs, "Duron")) return DURON; + if (strstr(bs, "Athlon")) return ATHLON_64; + } + + return NO_CODE; +} + +static void decode_amd_codename(struct cpu_raw_data_t* raw, struct cpu_id_t* data) +{ + amd_code_t code = decode_amd_codename_part1(data->brand_str); + + if (code == ATHLON_64 && data->l2_cache == 512) + code = ATHLON_64_MANCHESTER; + if (code == ATHLON_XP && data->l2_cache == 512) + code = ATHLON_XP_BARTON; + if (code == ATHLON_64_512K && data->l2_cache > 512) + code = ATHLON_64_1024K; + if (code == SEMPRON_64_128K && data->l2_cache > 128) + code = SEMPRON_64_256K; + if (code == TURION_64_512K && data->l2_cache > 512) + code = TURION_64_1024K; + if (code == TURION_X2_512K && data->l2_cache > 512) + code = TURION_X2_1024K; + if (code == ATHLON_64_X2_512K && data->l2_cache > 512) + code = ATHLON_64_X2_1024K; + match_cpu_codename(cpudb_amd, COUNT_OF(cpudb_amd), data, code); +} + int cpuid_identify_amd(struct cpu_raw_data_t* raw, struct cpu_id_t* data) { load_amd_features(raw, data); decode_amd_cache_info(raw, data); decode_amd_number_of_cores(raw, data); + decode_amd_codename(raw, data); return 0; } diff --git a/libcpuid/recog_intel.c b/libcpuid/recog_intel.c index dfe9f7d..c803c3a 100644 --- a/libcpuid/recog_intel.c +++ b/libcpuid/recog_intel.c @@ -52,131 +52,131 @@ enum _intel_code_t { typedef enum _intel_code_t intel_code_t; const struct match_entry_t cpudb_intel[] = { - { -1, -1, -1, -1, -1, NO_CODE, "Unknown Intel CPU" }, + { -1, -1, -1, -1, -1, NO_CODE , "Unknown Intel CPU" }, - // i486 - { 4, -1, -1, -1, -1, NO_CODE, "Unknown i486" }, - { 4, 0, -1, -1, -1, NO_CODE, "i486 DX-25/33" }, - { 4, 1, -1, -1, -1, NO_CODE, "i486 DX-50" }, - { 4, 2, -1, -1, -1, NO_CODE, "i486 SX" }, - { 4, 3, -1, -1, -1, NO_CODE, "i486 DX2" }, - { 4, 4, -1, -1, -1, NO_CODE, "i486 SL" }, - { 4, 5, -1, -1, -1, NO_CODE, "i486 SX2" }, - { 4, 7, -1, -1, -1, NO_CODE, "i486 DX2 WriteBack" }, - { 4, 8, -1, -1, -1, NO_CODE, "i486 DX4" }, - { 4, 9, -1, -1, -1, NO_CODE, "i486 DX4 WriteBack" }, + /* i486 */ + { 4, -1, -1, -1, -1, NO_CODE , "Unknown i486" }, + { 4, 0, -1, -1, -1, NO_CODE , "i486 DX-25/33" }, + { 4, 1, -1, -1, -1, NO_CODE , "i486 DX-50" }, + { 4, 2, -1, -1, -1, NO_CODE , "i486 SX" }, + { 4, 3, -1, -1, -1, NO_CODE , "i486 DX2" }, + { 4, 4, -1, -1, -1, NO_CODE , "i486 SL" }, + { 4, 5, -1, -1, -1, NO_CODE , "i486 SX2" }, + { 4, 7, -1, -1, -1, NO_CODE , "i486 DX2 WriteBack" }, + { 4, 8, -1, -1, -1, NO_CODE , "i486 DX4" }, + { 4, 9, -1, -1, -1, NO_CODE , "i486 DX4 WriteBack" }, - /* All Pentia: */ - // Pentium 1 - { 5, -1, -1, -1, -1, NO_CODE, "Unknown Pentium" }, - { 5, 0, -1, -1, -1, NO_CODE, "Pentium A-Step" }, - { 5, 1, -1, -1, -1, NO_CODE, "Pentium 1 (0.8u)" }, - { 5, 2, -1, -1, -1, NO_CODE, "Pentium 1 (0.35u)" }, - { 5, 3, -1, -1, -1, NO_CODE, "Pentium OverDrive" }, - { 5, 4, -1, -1, -1, NO_CODE, "Pentium 1 (0.35u)" }, - { 5, 7, -1, -1, -1, NO_CODE, "Pentium 1 (0.35u)" }, - { 5, 8, -1, -1, -1, NO_CODE, "Pentium MMX (0.25u)" }, + /* All Pentia: + Pentium 1 */ + { 5, -1, -1, -1, -1, NO_CODE , "Unknown Pentium" }, + { 5, 0, -1, -1, -1, NO_CODE , "Pentium A-Step" }, + { 5, 1, -1, -1, -1, NO_CODE , "Pentium 1 (0.8u)" }, + { 5, 2, -1, -1, -1, NO_CODE , "Pentium 1 (0.35u)" }, + { 5, 3, -1, -1, -1, NO_CODE , "Pentium OverDrive" }, + { 5, 4, -1, -1, -1, NO_CODE , "Pentium 1 (0.35u)" }, + { 5, 7, -1, -1, -1, NO_CODE , "Pentium 1 (0.35u)" }, + { 5, 8, -1, -1, -1, NO_CODE , "Pentium MMX (0.25u)" }, - // Pentium 2 / 3 / M / Conroe / whatsnext - all P6 based. - { 6, -1, -1, -1, -1, NO_CODE, "Unknown P6" }, - { 6, 0, -1, -1, -1, NO_CODE, "Pentium Pro" }, - { 6, 1, -1, -1, -1, NO_CODE, "Pentium Pro" }, - { 6, 3, -1, -1, -1, NO_CODE, "Pentium II (Klamath)" }, - { 6, 5, -1, -1, -1, NO_CODE, "Pentium II (Deschutes)" }, - { 6, 6, -1, -1, -1, NO_CODE, "Pentium II (Dixon)" }, + /* Pentium 2 / 3 / M / Conroe / whatsnext - all P6 based. */ + { 6, -1, -1, -1, -1, NO_CODE , "Unknown P6" }, + { 6, 0, -1, -1, -1, NO_CODE , "Pentium Pro" }, + { 6, 1, -1, -1, -1, NO_CODE , "Pentium Pro" }, + { 6, 3, -1, -1, -1, NO_CODE , "Pentium II (Klamath)" }, + { 6, 5, -1, -1, -1, NO_CODE , "Pentium II (Deschutes)" }, + { 6, 6, -1, -1, -1, NO_CODE , "Pentium II (Dixon)" }, - { 6, 3, -1, -1, -1, XEON, "P-II Xeon" }, - { 6, 5, -1, -1, -1, XEON, "P-II Xeon" }, - { 6, 6, -1, -1, -1, XEON, "P-II Xeon" }, + { 6, 3, -1, -1, -1, XEON , "P-II Xeon" }, + { 6, 5, -1, -1, -1, XEON , "P-II Xeon" }, + { 6, 6, -1, -1, -1, XEON , "P-II Xeon" }, - { 6, 5, -1, -1, -1, CELERON, "P-II Celeron (no L2)" }, - { 6, 6, -1, -1, -1, CELERON, "P-II Celeron (128K)" }, + { 6, 5, -1, -1, -1, CELERON , "P-II Celeron (no L2)" }, + { 6, 6, -1, -1, -1, CELERON , "P-II Celeron (128K)" }, - // ////////////////////////////////////////////////// // + /* ////////////////////////////////////////////////// */ - { 6, 7, -1, -1, -1, NO_CODE, "Pentium III (Katmai)" }, - { 6, 8, -1, -1, -1, NO_CODE, "Pentium III (Coppermine)" }, - { 6, 10, -1, -1, -1, NO_CODE, "Pentium III (Coppermine)" }, - { 6, 11, -1, -1, -1, NO_CODE, "Pentium III (Tualatin)" }, + { 6, 7, -1, -1, -1, NO_CODE , "Pentium III (Katmai)" }, + { 6, 8, -1, -1, -1, NO_CODE , "Pentium III (Coppermine)"}, + { 6, 10, -1, -1, -1, NO_CODE , "Pentium III (Coppermine)"}, + { 6, 11, -1, -1, -1, NO_CODE , "Pentium III (Tualatin)" }, - { 6, 7, -1, -1, -1, XEON, "P-III Xeon" }, - { 6, 8, -1, -1, -1, XEON, "P-III Xeon" }, - { 6, 10, -1, -1, -1, XEON, "P-III Xeon" }, - { 6, 11, -1, -1, -1, XEON, "P-III Xeon" }, + { 6, 7, -1, -1, -1, XEON , "P-III Xeon" }, + { 6, 8, -1, -1, -1, XEON , "P-III Xeon" }, + { 6, 10, -1, -1, -1, XEON , "P-III Xeon" }, + { 6, 11, -1, -1, -1, XEON , "P-III Xeon" }, - { 6, 7, -1, -1, -1, CELERON, "P-III Celeron" }, - { 6, 8, -1, -1, -1, CELERON, "P-III Celeron" }, - { 6, 10, -1, -1, -1, CELERON, "P-III Celeron" }, - { 6, 11, -1, -1, -1, CELERON, "P-III Celeron" }, + { 6, 7, -1, -1, -1, CELERON , "P-III Celeron" }, + { 6, 8, -1, -1, -1, CELERON , "P-III Celeron" }, + { 6, 10, -1, -1, -1, CELERON , "P-III Celeron" }, + { 6, 11, -1, -1, -1, CELERON , "P-III Celeron" }, - // ////////////////////////////////////////////////// // + /* ////////////////////////////////////////////////// */ - { 6, 9, -1, -1, -1, NO_CODE, "Unknown Pentium M" }, - { 6, 9, -1, -1, -1, MOBILE_PENTIUM_M, "Unknown Pentium M" }, - { 6, 9, -1, -1, -1, PENTIUM, "Pentium M (Banias)" }, - { 6, 9, -1, -1, -1, CELERON, "Celeron M" }, - { 6, 13, -1, -1, -1, PENTIUM, "Pentium M (Dothan)" }, - { 6, 13, -1, -1, -1, CELERON, "Celeron M" }, + { 6, 9, -1, -1, -1, NO_CODE , "Unknown Pentium M" }, + { 6, 9, -1, -1, -1, MOBILE_PENTIUM_M , "Unknown Pentium M" }, + { 6, 9, -1, -1, -1, PENTIUM , "Pentium M (Banias)" }, + { 6, 9, -1, -1, -1, CELERON , "Celeron M" }, + { 6, 13, -1, -1, -1, PENTIUM , "Pentium M (Dothan)" }, + { 6, 13, -1, -1, -1, CELERON , "Celeron M" }, - // ////////////////////////////////////////////////// // + /* ////////////////////////////////////////////////// */ - { 6, 14, -1, -1, -1, NO_CODE, "Unknown Yonah" }, - { 6, 14, -1, -1, -1, CORE_SOLO, "Yonah (Core Solo)" }, - { 6, 14, -1, -1, -1, CORE_DUO, "Yonah (Core Duo)" }, - { 6, 14, -1, -1, -1, XEON, "Xeon LV" }, - { 6, 14, -1, -1, -1, CORE_SOLO, "Yonah (Core Solo)" }, + { 6, 14, -1, -1, -1, NO_CODE , "Unknown Yonah" }, + { 6, 14, -1, -1, -1, CORE_SOLO , "Yonah (Core Solo)" }, + { 6, 14, -1, -1, -1, CORE_DUO , "Yonah (Core Duo)" }, + { 6, 14, -1, -1, -1, XEON , "Xeon LV" }, + { 6, 14, -1, -1, -1, CORE_SOLO , "Yonah (Core Solo)" }, - { 6, 15, -1, -1, -1, NO_CODE, "Unknown Core 2" }, - { 6, 15, -1, -1, -1, CORE_DUO, "Conroe (Core 2 Duo)" }, - { 6, 15, -1, -1, -1, KENTSFIELD, "Kentsfield" }, - { 6, 15, -1, -1, -1, MORE_THAN_QUADCORE, "More than quad-core" }, - { 6, 15, -1, -1, -1, ALLENDALE, "Allendale (Core 2 Duo)" }, + { 6, 15, -1, -1, -1, NO_CODE , "Unknown Core 2" }, + { 6, 15, -1, -1, -1, CORE_DUO , "Conroe (Core 2 Duo)" }, + { 6, 15, -1, -1, -1, KENTSFIELD , "Kentsfield" }, + { 6, 15, -1, -1, -1, MORE_THAN_QUADCORE, "More than quad-core" }, + { 6, 15, -1, -1, -1, ALLENDALE , "Allendale (Core 2 Duo)" }, - { 6, 16, -1, -1, -1, NO_CODE, "Unknown Core ?" }, // future ones - { 6, 17, -1, -1, -1, NO_CODE, "Unknown Core ?" }, // future ones - { 6, 16, -1, -1, -1, MORE_THAN_QUADCORE, "More than quad-core" }, // future ones - { 6, 17, -1, -1, -1, MORE_THAN_QUADCORE, "More than quad-core" }, // future ones + { 6, 16, -1, -1, -1, NO_CODE , "Unknown Core ?" }, // future ones + { 6, 17, -1, -1, -1, NO_CODE , "Unknown Core ?" }, // future ones + { 6, 16, -1, -1, -1, MORE_THAN_QUADCORE, "More than quad-core" }, // future ones + { 6, 17, -1, -1, -1, MORE_THAN_QUADCORE, "More than quad-core" }, // future ones - // Itaniums - { 7, -1, -1, -1, -1, NO_CODE, "Itanium" }, - { 15, -1, -1, 1, -1, NO_CODE, "Itanium 2" }, + /* Itaniums */ + { 7, -1, -1, -1, -1, NO_CODE , "Itanium" }, + { 15, -1, -1, 1, -1, NO_CODE , "Itanium 2" }, - // Netburst based (Pentium 4 and later) - // classic P4s - { 15, -1, -1, 0, -1, NO_CODE, "Unknown Pentium 4" }, - { 15, -1, -1, 0, -1, CELERON, "Unknown P-4 Celeron" }, - { 15, -1, -1, 0, -1, XEON, "Unknown Xeon" }, + /* Netburst based (Pentium 4 and later) + classic P4s */ + { 15, -1, -1, 0, -1, NO_CODE , "Unknown Pentium 4" }, + { 15, -1, -1, 0, -1, CELERON , "Unknown P-4 Celeron" }, + { 15, -1, -1, 0, -1, XEON , "Unknown Xeon" }, - { 15, 0, -1, 0, -1, NO_CODE, "Pentium 4 (Willamette)" }, - { 15, 1, -1, 0, -1, NO_CODE, "Pentium 4 (Willamette)" }, - { 15, 2, -1, 0, -1, NO_CODE, "Pentium 4 (Northwood)" }, - { 15, 3, -1, 0, -1, NO_CODE, "Pentium 4 (Prescott)" }, - { 15, 4, -1, 0, -1, NO_CODE, "Pentium 4 (Prescott)" }, + { 15, 0, -1, 0, -1, NO_CODE , "Pentium 4 (Willamette)" }, + { 15, 1, -1, 0, -1, NO_CODE , "Pentium 4 (Willamette)" }, + { 15, 2, -1, 0, -1, NO_CODE , "Pentium 4 (Northwood)" }, + { 15, 3, -1, 0, -1, NO_CODE , "Pentium 4 (Prescott)" }, + { 15, 4, -1, 0, -1, NO_CODE , "Pentium 4 (Prescott)" }, - // server CPUs - { 15, 0, -1, 0, -1, XEON, "Xeon (Foster)" }, - { 15, 1, -1, 0, -1, XEON, "Xeon (Foster)" }, - { 15, 2, -1, 0, -1, XEON, "Xeon (Prestonia)" }, - { 15, 2, -1, 0, -1, XEONMP, "Xeon (Gallatin)" }, - { 15, 3, -1, 0, -1, XEON, "Xeon (Nocona)" }, - { 15, 4, -1, 0, -1, XEON, "Xeon (Nocona)" }, - { 15, 4, -1, 0, -1, XEON_IRWIN, "Xeon (Irwindale)" }, - { 15, 4, -1, 0, -1, XEONMP, "Xeon (Cranford)" }, - { 15, 4, -1, 0, -1, XEON_POTOMAC, "Xeon (Potomac)" }, - { 15, 6, -1, 0, -1, XEON, "Xeon 5000" }, + /* server CPUs */ + { 15, 0, -1, 0, -1, XEON , "Xeon (Foster)" }, + { 15, 1, -1, 0, -1, XEON , "Xeon (Foster)" }, + { 15, 2, -1, 0, -1, XEON , "Xeon (Prestonia)" }, + { 15, 2, -1, 0, -1, XEONMP , "Xeon (Gallatin)" }, + { 15, 3, -1, 0, -1, XEON , "Xeon (Nocona)" }, + { 15, 4, -1, 0, -1, XEON , "Xeon (Nocona)" }, + { 15, 4, -1, 0, -1, XEON_IRWIN , "Xeon (Irwindale)" }, + { 15, 4, -1, 0, -1, XEONMP , "Xeon (Cranford)" }, + { 15, 4, -1, 0, -1, XEON_POTOMAC , "Xeon (Potomac)" }, + { 15, 6, -1, 0, -1, XEON , "Xeon 5000" }, - // Pentium Ds - { 15, 4, 4, 0, -1, NO_CODE, "Pentium D" }, - { 15, 4, -1, 0, -1, PENTIUM_D, "Pentium D" }, - { 15, 4, 7, 0, -1, NO_CODE, "Pentium D" }, - { 15, 6, -1, 0, -1, PENTIUM_D, "Pentium D" }, + /* Pentium Ds */ + { 15, 4, 4, 0, -1, NO_CODE , "Pentium D" }, + { 15, 4, -1, 0, -1, PENTIUM_D , "Pentium D" }, + { 15, 4, 7, 0, -1, NO_CODE , "Pentium D" }, + { 15, 6, -1, 0, -1, PENTIUM_D , "Pentium D" }, - // Celeron and Celeron Ds - { 15, 1, -1, 0, -1, CELERON, "P-4 Celeron (128K)" }, - { 15, 2, -1, 0, -1, CELERON, "P-4 Celeron (128K)" }, - { 15, 3, -1, 0, -1, CELERON, "Celeron D" }, - { 15, 4, -1, 0, -1, CELERON, "Celeron D" }, - { 15, 6, -1, 0, -1, CELERON, "Celeron D" }, + /* Celeron and Celeron Ds */ + { 15, 1, -1, 0, -1, CELERON , "P-4 Celeron (128K)" }, + { 15, 2, -1, 0, -1, CELERON , "P-4 Celeron (128K)" }, + { 15, 3, -1, 0, -1, CELERON , "Celeron D" }, + { 15, 4, -1, 0, -1, CELERON , "Celeron D" }, + { 15, 6, -1, 0, -1, CELERON , "Celeron D" }, }; @@ -409,7 +409,7 @@ static void decode_intel_number_of_cores(struct cpu_raw_data_t* raw, } } -static void decode_cpu_codename(struct cpu_raw_data_t* raw, struct cpu_id_t* data) +static void decode_intel_codename(struct cpu_raw_data_t* raw, struct cpu_id_t* data) { intel_code_t code = NO_CODE; int i; @@ -467,6 +467,6 @@ int cpuid_identify_intel(struct cpu_raw_data_t* raw, struct cpu_id_t* data) decode_intel_oldstyle_cache_info(raw, data); } decode_intel_number_of_cores(raw, data); - decode_cpu_codename(raw, data); + decode_intel_codename(raw, data); return 0; }