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DB: add Intel Emerald Rapids-SP
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@ -71,6 +71,7 @@ enum _intel_model_t {
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_x2xx, /* Xeon Bronze/Silver/Gold/Platinum x2xx */
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_x3xx, /* Xeon Bronze/Silver/Gold/Platinum x3xx */
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_x4xx, /* Xeon Bronze/Silver/Gold/Platinum/Max x4xx */
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_x5xx, /* Xeon Bronze/Silver/Gold/Platinum x5xx */
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_1xx, /* Core Ultra [579] 1xx */
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};
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typedef enum _intel_model_t intel_model_t;
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@ -538,6 +539,12 @@ const struct match_entry_t cpudb_intel[] = {
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{ 6, 15, -1, -1, 143, -1, -1, -1, NC, XEON_|_SILVER_ , _x4xx, "Sapphire Rapids-SP (Xeon Silver)" },
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{ 6, 15, -1, -1, 143, -1, -1, -1, NC, XEON_|_BRONZE_ , _x4xx, "Sapphire Rapids-SP (Xeon Bronze)" },
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/* Emerald Rapids CPUs (2023, 5th Xeon Scalable gen, Intel 7) => https://en.wikichip.org/wiki/intel/microarchitectures/emerald_rapids */
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{ 6, 15, -1, -1, 207, -1, -1, -1, NC, XEON_|_PLATINIUM_, _x5xx, "Emerald Rapids-SP (Xeon Platinum)" }, // Xeon Platinum (8500)
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{ 6, 15, -1, -1, 207, -1, -1, -1, NC, XEON_|_GOLD_ , _x5xx, "Emerald Rapids-SP (Xeon Gold)" }, // Xeon Gold (5500 and 6500)
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{ 6, 15, -1, -1, 207, -1, -1, -1, NC, XEON_|_SILVER_ , _x5xx, "Emerald Rapids-SP (Xeon Silver)" }, // Xeon Silver (4500)
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{ 6, 15, -1, -1, 207, -1, -1, -1, NC, XEON_|_BRONZE_ , _x5xx, "Emerald Rapids-SP (Xeon Bronze)" }, // Xeon Bronze (3500)
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/* Meteor Lake CPUs (2023, 1st Core Ultra gen, Intel 4) => https://en.wikichip.org/wiki/intel/microarchitectures/meteor_lake */
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{ 6, 10, -1, -1, 170, -1, -1, -1, NC, CORE_|_ULTRA_|_9|_H, _x1xx, "Meteor Lake-H (Core Ultra 9)" },
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{ 6, 10, -1, -1, 170, -1, -1, -1, NC, CORE_|_ULTRA_|_7|_H, _x1xx, "Meteor Lake-H (Core Ultra 7)" },
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@ -966,6 +973,7 @@ static intel_model_t get_model_code(struct cpu_id_t* data)
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if (bs[i] == '2') return _x2xx;
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if (bs[i] == '3') return _x3xx;
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if (bs[i] == '4') return _x4xx;
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if (bs[i] == '5') return _x5xx;
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return UNKNOWN;
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}
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