From 0c9ef3249c755ea674e042d84f9333016ee12c9d Mon Sep 17 00:00:00 2001 From: Xorg Date: Tue, 20 Sep 2022 07:18:16 +0200 Subject: [PATCH] Decode deterministic cache info for AMD CPUs too Since Zen-based CPUs, cpu_id_t::l3_cache is the size of the total L3 cache for the whole chip, while cpu_id_t::l1_cache and cpu_id_t::l2_cache are size for each instances. This change provide L3 cache size per instance. --- libcpuid/libcpuid_internal.h | 13 +- libcpuid/libcpuid_util.c | 110 +++++++++++ libcpuid/libcpuid_util.h | 11 ++ libcpuid/recog_amd.c | 26 +-- libcpuid/recog_intel.c | 188 +++++-------------- tests/amd/bobcat/brazos-zacate.test | 2 +- tests/amd/bulldozer/godavari-x4.test | 2 +- tests/amd/bulldozer/kaveri-x4.test | 2 +- tests/amd/k10/athlon-2-champlain-mobile.test | 2 +- tests/amd/k10/athlon-2-propus-2.test | 2 +- tests/amd/k10/athlon-2-propus-3.test | 2 +- tests/amd/k10/athlon-2-propus.test | 2 +- tests/amd/k10/athlon-2-regor.test | 2 +- tests/amd/k10/sempron-sargas.test | 2 +- tests/amd/k7/athlon-thoroughbred.test | 2 +- tests/amd/k7/duron-applebred.test | 2 +- tests/amd/k7/sempron-barton.test | 2 +- tests/amd/k8/athlon-64-brisbane.test | 2 +- tests/amd/k8/athlon-64-venice.test | 2 +- tests/amd/k8/mobile-sempron-64-keene.test | 2 +- tests/amd/k8/mobile-sempron-64-sonora.test | 2 +- tests/amd/k8/opteron-denmark.test | 2 +- tests/amd/k8/sempron-64-sparta.test | 2 +- tests/amd/k8/turion-64-lancaster.test | 2 +- tests/amd/zen2/epyc-rome.test | 2 +- tests/amd/zen2/ryzen5-lucienne.test | 2 +- tests/amd/zen2/ryzen5-matisse.test | 2 +- tests/amd/zen2/ryzen5-renoir.test | 2 +- tests/amd/zen2/ryzen7-lucienne.test | 2 +- tests/amd/zen2/ryzen7-matisse.test | 2 +- tests/amd/zen2/ryzen7-renoir.test | 2 +- tests/amd/zen2/ryzen9-matisse.test | 2 +- tests/amd/zen2/threadripper-castle-peak.test | 2 +- tests/amd/zen3/epyc-milan.test | 2 +- tests/amd/zen3/ryzen7-warhol.test | 108 ----------- tests/amd/zen3/ryzen9-vermeer.test | 2 +- 36 files changed, 220 insertions(+), 296 deletions(-) delete mode 100644 tests/amd/zen3/ryzen7-warhol.test diff --git a/libcpuid/libcpuid_internal.h b/libcpuid/libcpuid_internal.h index 647091e..9837deb 100644 --- a/libcpuid/libcpuid_internal.h +++ b/libcpuid/libcpuid_internal.h @@ -38,6 +38,16 @@ enum _common_codes_t { NC, /* No code */ }; +enum _cache_type_t { + L1I, + L1D, + L2, + L3, + L4, + NUM_CACHE_TYPES +}; +typedef enum _cache_type_t cache_type_t; + #define CODE(x) x #define CODE2(x, y) x = y enum _amd_code_t { @@ -59,8 +69,7 @@ struct internal_id_info_t { } code; uint64_t bits; int score; // detection (matchtable) score - int32_t smt_id; - int32_t core_id; + int32_t cache_mask[NUM_CACHE_TYPES]; }; #define LBIT(x) (((long long) 1) << x) diff --git a/libcpuid/libcpuid_util.c b/libcpuid/libcpuid_util.c index 6ae2c93..6e43c53 100644 --- a/libcpuid/libcpuid_util.c +++ b/libcpuid/libcpuid_util.c @@ -34,6 +34,7 @@ #endif #include "libcpuid.h" #include "libcpuid_util.h" +#include "libcpuid_internal.h" int _current_verboselevel; @@ -265,3 +266,112 @@ void clear_affinity_mask_bit(logical_cpu_t logical_cpu, cpu_affinity_mask_t *aff { affinity_mask->__bits[logical_cpu / __MASK_NCPUBITS] &= ~(0x1 << (logical_cpu % __MASK_NCPUBITS)); } + +/* https://github.com/torvalds/linux/blob/3e5c673f0d75bc22b3c26eade87e4db4f374cd34/include/linux/bitops.h#L210-L216 */ +static int get_count_order(unsigned int x) +{ + int r = 32; + + if (x == 0) + return -1; + + --x; + if (!x) + return 0; + if (!(x & 0xffff0000u)) { + x <<= 16; + r -= 16; + } + if (!(x & 0xff000000u)) { + x <<= 8; + r -= 8; + } + if (!(x & 0xf0000000u)) { + x <<= 4; + r -= 4; + } + if (!(x & 0xc0000000u)) { + x <<= 2; + r -= 2; + } + if (!(x & 0x80000000u)) { + x <<= 1; + r -= 1; + } + return r; +} + +void assign_cache_data(uint8_t on, cache_type_t cache, int size, int assoc, int linesize, struct cpu_id_t* data) +{ + if (!on) return; + switch (cache) { + case L1I: + data->l1_instruction_cache = size; + data->l1_instruction_assoc = assoc; + data->l1_instruction_cacheline = linesize; + break; + case L1D: + data->l1_data_cache = size; + data->l1_data_assoc = assoc; + data->l1_data_cacheline = linesize; + break; + case L2: + data->l2_cache = size; + data->l2_assoc = assoc; + data->l2_cacheline = linesize; + break; + case L3: + data->l3_cache = size; + data->l3_assoc = assoc; + data->l3_cacheline = linesize; + break; + case L4: + data->l4_cache = size; + data->l4_assoc = assoc; + data->l4_cacheline = linesize; + break; + default: + break; + } +} + +void decode_deterministic_cache_info_x86(uint32_t cache_regs[][NUM_REGS], + uint8_t subleaf_count, + struct cpu_id_t* data, + struct internal_id_info_t* internal) +{ + uint8_t i; + uint32_t cache_level, cache_type, ways, partitions, linesize, sets, size, num_sharing_cache, index_msb; + cache_type_t type; + + for (i = 0; i < subleaf_count; i++) { + cache_level = EXTRACTS_BITS(cache_regs[i][EAX], 7, 5); + cache_type = EXTRACTS_BITS(cache_regs[i][EAX], 4, 0); + if ((cache_level == 0) || (cache_type == 0)) + break; + if (cache_level == 1 && cache_type == 1) + type = L1D; + else if (cache_level == 1 && cache_type == 2) + type = L1I; + else if (cache_level == 2 && cache_type == 3) + type = L2; + else if (cache_level == 3 && cache_type == 3) + type = L3; + else if (cache_level == 4 && cache_type == 3) + type = L4; + else { + warnf("deterministic_cache: unknown level/typenumber combo (%d/%d), cannot\n", cache_level, cache_type); + warnf("deterministic_cache: recognize cache type\n"); + continue; + } + num_sharing_cache = EXTRACTS_BITS(cache_regs[i][EAX], 25, 14) + 1; + ways = EXTRACTS_BITS(cache_regs[i][EBX], 31, 22) + 1; + partitions = EXTRACTS_BITS(cache_regs[i][EBX], 21, 12) + 1; + linesize = EXTRACTS_BITS(cache_regs[i][EBX], 11, 0) + 1; + sets = EXTRACTS_BITS(cache_regs[i][ECX], 31, 0) + 1; + size = ways * partitions * linesize * sets / 1024; + index_msb = get_count_order(num_sharing_cache); + internal->cache_mask[i] = ~((1 << index_msb) - 1); + assign_cache_data(1, type, size, ways, linesize, data); + } +} diff --git a/libcpuid/libcpuid_util.h b/libcpuid/libcpuid_util.h index a4a701b..c4f832a 100644 --- a/libcpuid/libcpuid_util.h +++ b/libcpuid/libcpuid_util.h @@ -26,6 +26,8 @@ #ifndef __LIBCPUID_UTIL_H__ #define __LIBCPUID_UTIL_H__ +#include "libcpuid_internal.h" + #define COUNT_OF(array) (sizeof(array) / sizeof(array[0])) struct feature_map_t { @@ -114,4 +116,13 @@ bool get_affinity_mask_bit(logical_cpu_t logical_cpu, cpu_affinity_mask_t *affin /* set bit corresponding to 'logical_cpu' to '0' */ void clear_affinity_mask_bit(logical_cpu_t logical_cpu, cpu_affinity_mask_t *affinity_mask); +/* assign cache values in cpu_id_t type */ +void assign_cache_data(uint8_t on, cache_type_t cache, int size, int assoc, int linesize, struct cpu_id_t* data); + +/* generic way to retrieve cache topology for x86 CPUs */ +void decode_deterministic_cache_info_x86(uint32_t cache_regs[][NUM_REGS], + uint8_t subleaf_count, + struct cpu_id_t* data, + struct internal_id_info_t* internal); + #endif /* __LIBCPUID_UTIL_H__ */ diff --git a/libcpuid/recog_amd.c b/libcpuid/recog_amd.c index 2527fcc..7b0e2ff 100644 --- a/libcpuid/recog_amd.c +++ b/libcpuid/recog_amd.c @@ -416,26 +416,13 @@ static void decode_amd_cache_info(struct cpu_raw_data_t* raw, struct cpu_id_t* d l3_result = (raw->ext_cpuid[6][EDX] >> 18); if (l3_result > 0) { - l3_result = 512 * l3_result; /* AMD spec says it's a range, - but we take the lower bound */ + l3_result *= 512; /* AMD spec says it's a range, but we take the lower bound */ l3_assoc = (raw->ext_cpuid[6][EDX] >> 12) & 0xf; data->l3_cache = l3_result; - - if(l3_assoc == 0x9) { - /* Since Zen 2, CPUID_Fn80000006_EDX[15:12] is invalid (0x9) - According to page 74 on - Processor Programming Reference (PPR) for AMD Family 17h Model 71h, Revision B0 Processors: - "There are insufficient available encodings to represent all possible L3 - associativities. Please refer to Core::X86::Cpuid::CachePropEbx3[CacheNumWays]." - Note: we do not read CPUID_Fn80000001_ECX[22] (AKA TopologyExtensions) to allow backward compatibility with existing tests */ - data->l3_assoc = EXTRACTS_BITS(raw->amd_fn8000001dh[0x3][EBX], 31, 22) + 1; // Cache number of ways is CacheNumWays + 1 - data->l3_cacheline = EXTRACTS_BITS(raw->amd_fn8000001dh[0x3][EBX], 11, 0) + 1; // Cache line size in bytes is CacheLineSize + 1 - } else { - data->l3_assoc = assoc_table[l3_assoc]; - data->l3_cacheline = (raw->ext_cpuid[6][EDX]) & 0xff; - } + data->l3_assoc = assoc_table[l3_assoc]; + data->l3_cacheline = (raw->ext_cpuid[6][EDX]) & 0xff; } else { - data->l3_cache = 0; + data->l3_cache = -1; } } } @@ -608,7 +595,10 @@ static void decode_amd_codename(struct cpu_raw_data_t* raw, struct cpu_id_t* dat int cpuid_identify_amd(struct cpu_raw_data_t* raw, struct cpu_id_t* data, struct internal_id_info_t* internal) { load_amd_features(raw, data); - decode_amd_cache_info(raw, data); + if ((EXTRACTS_BIT(raw->ext_cpuid[1][ECX], 22) == 1) && (EXTRACTS_BITS(raw->amd_fn8000001dh[0][EAX], 4, 0) != 0)) /* TopologyExtensions supported */ + decode_deterministic_cache_info_x86(raw->amd_fn8000001dh, MAX_AMDFN8000001DH_LEVEL, data, internal); + else + decode_amd_cache_info(raw, data); decode_amd_number_of_cores(raw, data); decode_amd_codename(raw, data, internal); return 0; diff --git a/libcpuid/recog_intel.c b/libcpuid/recog_intel.c index 9bcffba..b886be7 100644 --- a/libcpuid/recog_intel.c +++ b/libcpuid/recog_intel.c @@ -503,49 +503,6 @@ static void load_intel_features(struct cpu_raw_data_t* raw, struct cpu_id_t* dat } } -enum _cache_type_t { - L1I, - L1D, - L2, - L3, - L4 -}; -typedef enum _cache_type_t cache_type_t; - -static void check_case(uint8_t on, cache_type_t cache, int size, int assoc, int linesize, struct cpu_id_t* data) -{ - if (!on) return; - switch (cache) { - case L1I: - data->l1_instruction_cache = size; - data->l1_instruction_assoc = assoc; - data->l1_instruction_cacheline = linesize; - break; - case L1D: - data->l1_data_cache = size; - data->l1_data_assoc = assoc; - data->l1_data_cacheline = linesize; - break; - case L2: - data->l2_cache = size; - data->l2_assoc = assoc; - data->l2_cacheline = linesize; - break; - case L3: - data->l3_cache = size; - data->l3_assoc = assoc; - data->l3_cacheline = linesize; - break; - case L4: - data->l4_cache = size; - data->l4_assoc = assoc; - data->l4_cacheline = linesize; - break; - default: - break; - } -} - static void decode_intel_oldstyle_cache_info(struct cpu_raw_data_t* raw, struct cpu_id_t* data) { uint8_t f[256] = {0}; @@ -560,59 +517,59 @@ static void decode_intel_oldstyle_cache_info(struct cpu_raw_data_t* raw, struct } } - check_case(f[0x06], L1I, 8, 4, 32, data); - check_case(f[0x08], L1I, 16, 4, 32, data); - check_case(f[0x0A], L1D, 8, 2, 32, data); - check_case(f[0x0C], L1D, 16, 4, 32, data); - check_case(f[0x22], L3, 512, 4, 64, data); - check_case(f[0x23], L3, 1024, 8, 64, data); - check_case(f[0x25], L3, 2048, 8, 64, data); - check_case(f[0x29], L3, 4096, 8, 64, data); - check_case(f[0x2C], L1D, 32, 8, 64, data); - check_case(f[0x30], L1I, 32, 8, 64, data); - check_case(f[0x39], L2, 128, 4, 64, data); - check_case(f[0x3A], L2, 192, 6, 64, data); - check_case(f[0x3B], L2, 128, 2, 64, data); - check_case(f[0x3C], L2, 256, 4, 64, data); - check_case(f[0x3D], L2, 384, 6, 64, data); - check_case(f[0x3E], L2, 512, 4, 64, data); - check_case(f[0x41], L2, 128, 4, 32, data); - check_case(f[0x42], L2, 256, 4, 32, data); - check_case(f[0x43], L2, 512, 4, 32, data); - check_case(f[0x44], L2, 1024, 4, 32, data); - check_case(f[0x45], L2, 2048, 4, 32, data); - check_case(f[0x46], L3, 4096, 4, 64, data); - check_case(f[0x47], L3, 8192, 8, 64, data); - check_case(f[0x4A], L3, 6144, 12, 64, data); - check_case(f[0x4B], L3, 8192, 16, 64, data); - check_case(f[0x4C], L3, 12288, 12, 64, data); - check_case(f[0x4D], L3, 16384, 16, 64, data); - check_case(f[0x4E], L2, 6144, 24, 64, data); - check_case(f[0x60], L1D, 16, 8, 64, data); - check_case(f[0x66], L1D, 8, 4, 64, data); - check_case(f[0x67], L1D, 16, 4, 64, data); - check_case(f[0x68], L1D, 32, 4, 64, data); + assign_cache_data(f[0x06], L1I, 8, 4, 32, data); + assign_cache_data(f[0x08], L1I, 16, 4, 32, data); + assign_cache_data(f[0x0A], L1D, 8, 2, 32, data); + assign_cache_data(f[0x0C], L1D, 16, 4, 32, data); + assign_cache_data(f[0x22], L3, 512, 4, 64, data); + assign_cache_data(f[0x23], L3, 1024, 8, 64, data); + assign_cache_data(f[0x25], L3, 2048, 8, 64, data); + assign_cache_data(f[0x29], L3, 4096, 8, 64, data); + assign_cache_data(f[0x2C], L1D, 32, 8, 64, data); + assign_cache_data(f[0x30], L1I, 32, 8, 64, data); + assign_cache_data(f[0x39], L2, 128, 4, 64, data); + assign_cache_data(f[0x3A], L2, 192, 6, 64, data); + assign_cache_data(f[0x3B], L2, 128, 2, 64, data); + assign_cache_data(f[0x3C], L2, 256, 4, 64, data); + assign_cache_data(f[0x3D], L2, 384, 6, 64, data); + assign_cache_data(f[0x3E], L2, 512, 4, 64, data); + assign_cache_data(f[0x41], L2, 128, 4, 32, data); + assign_cache_data(f[0x42], L2, 256, 4, 32, data); + assign_cache_data(f[0x43], L2, 512, 4, 32, data); + assign_cache_data(f[0x44], L2, 1024, 4, 32, data); + assign_cache_data(f[0x45], L2, 2048, 4, 32, data); + assign_cache_data(f[0x46], L3, 4096, 4, 64, data); + assign_cache_data(f[0x47], L3, 8192, 8, 64, data); + assign_cache_data(f[0x4A], L3, 6144, 12, 64, data); + assign_cache_data(f[0x4B], L3, 8192, 16, 64, data); + assign_cache_data(f[0x4C], L3, 12288, 12, 64, data); + assign_cache_data(f[0x4D], L3, 16384, 16, 64, data); + assign_cache_data(f[0x4E], L2, 6144, 24, 64, data); + assign_cache_data(f[0x60], L1D, 16, 8, 64, data); + assign_cache_data(f[0x66], L1D, 8, 4, 64, data); + assign_cache_data(f[0x67], L1D, 16, 4, 64, data); + assign_cache_data(f[0x68], L1D, 32, 4, 64, data); /* The following four entries are trace cache. Intel does not * specify a cache-line size, so we use -1 instead */ - check_case(f[0x70], L1I, 12, 8, -1, data); - check_case(f[0x71], L1I, 16, 8, -1, data); - check_case(f[0x72], L1I, 32, 8, -1, data); - check_case(f[0x73], L1I, 64, 8, -1, data); + assign_cache_data(f[0x70], L1I, 12, 8, -1, data); + assign_cache_data(f[0x71], L1I, 16, 8, -1, data); + assign_cache_data(f[0x72], L1I, 32, 8, -1, data); + assign_cache_data(f[0x73], L1I, 64, 8, -1, data); - check_case(f[0x78], L2, 1024, 4, 64, data); - check_case(f[0x79], L2, 128, 8, 64, data); - check_case(f[0x7A], L2, 256, 8, 64, data); - check_case(f[0x7B], L2, 512, 8, 64, data); - check_case(f[0x7C], L2, 1024, 8, 64, data); - check_case(f[0x7D], L2, 2048, 8, 64, data); - check_case(f[0x7F], L2, 512, 2, 64, data); - check_case(f[0x82], L2, 256, 8, 32, data); - check_case(f[0x83], L2, 512, 8, 32, data); - check_case(f[0x84], L2, 1024, 8, 32, data); - check_case(f[0x85], L2, 2048, 8, 32, data); - check_case(f[0x86], L2, 512, 4, 64, data); - check_case(f[0x87], L2, 1024, 8, 64, data); + assign_cache_data(f[0x78], L2, 1024, 4, 64, data); + assign_cache_data(f[0x79], L2, 128, 8, 64, data); + assign_cache_data(f[0x7A], L2, 256, 8, 64, data); + assign_cache_data(f[0x7B], L2, 512, 8, 64, data); + assign_cache_data(f[0x7C], L2, 1024, 8, 64, data); + assign_cache_data(f[0x7D], L2, 2048, 8, 64, data); + assign_cache_data(f[0x7F], L2, 512, 2, 64, data); + assign_cache_data(f[0x82], L2, 256, 8, 32, data); + assign_cache_data(f[0x83], L2, 512, 8, 32, data); + assign_cache_data(f[0x84], L2, 1024, 8, 32, data); + assign_cache_data(f[0x85], L2, 2048, 8, 32, data); + assign_cache_data(f[0x86], L2, 512, 4, 64, data); + assign_cache_data(f[0x87], L2, 1024, 8, 64, data); if (f[0x49]) { /* This flag is overloaded with two meanings. On Xeon MP @@ -643,69 +600,24 @@ static void decode_intel_oldstyle_cache_info(struct cpu_raw_data_t* raw, struct } } -static void decode_intel_deterministic_cache_info(struct cpu_raw_data_t* raw, - struct cpu_id_t* data) -{ - int ecx; - int ways, partitions, linesize, sets, size, level, typenumber; - cache_type_t type; - for (ecx = 0; ecx < MAX_INTELFN4_LEVEL; ecx++) { - typenumber = raw->intel_fn4[ecx][EAX] & 0x1f; - if (typenumber == 0) break; - level = (raw->intel_fn4[ecx][EAX] >> 5) & 0x7; - if (level == 1 && typenumber == 1) - type = L1D; - else if (level == 1 && typenumber == 2) - type = L1I; - else if (level == 2 && typenumber == 3) - type = L2; - else if (level == 3 && typenumber == 3) - type = L3; - else if (level == 4 && typenumber == 3) - type = L4; - else { - warnf("deterministic_cache: unknown level/typenumber combo (%d/%d), cannot\n", level, typenumber); - warnf("deterministic_cache: recognize cache type\n"); - continue; - } - ways = ((raw->intel_fn4[ecx][EBX] >> 22) & 0x3ff) + 1; - partitions = ((raw->intel_fn4[ecx][EBX] >> 12) & 0x3ff) + 1; - linesize = (raw->intel_fn4[ecx][EBX] & 0xfff) + 1; - sets = raw->intel_fn4[ecx][ECX] + 1; - size = ways * partitions * linesize * sets / 1024; - check_case(1, type, size, ways, linesize, data); - } -} - static int decode_intel_extended_topology(struct cpu_raw_data_t* raw, struct cpu_id_t* data, struct internal_id_info_t* internal) { int i, level_type, num_smt = -1, num_core = -1; - uint8_t apic_package_shift = 0, apic_shift = 0, apic_next_shift; - uint32_t apic_id, unique_id; - - for (i = 0; (raw->intel_fn11[i][EAX] != 0x0) && (raw->intel_fn11[i][EBX] != 0x0) && (i < MAX_INTELFN11_LEVEL); i++) - apic_package_shift = EXTRACTS_BITS(raw->intel_fn11[i][EAX], 4, 0); for (i = 0; (raw->intel_fn11[i][EAX] != 0x0) && (raw->intel_fn11[i][EBX] != 0x0) && (i < MAX_INTELFN11_LEVEL); i++) { level_type = EXTRACTS_BITS(raw->intel_fn11[i][ECX], 15, 8); - apic_next_shift = EXTRACTS_BITS(raw->intel_fn11[i][EAX], 4, 0); - apic_id = raw->intel_fn11[i][EDX]; - unique_id = (apic_id >> apic_shift) & ((1 << (apic_package_shift - apic_shift)) - 1); switch (level_type) { case 0x01: num_smt = EXTRACTS_BITS(raw->intel_fn11[i][EBX], 15, 0); - internal->smt_id = unique_id; break; case 0x02: num_core = EXTRACTS_BITS(raw->intel_fn11[i][EBX], 15, 0); - internal->core_id = unique_id; break; default: break; } - apic_shift = apic_next_shift; } if (num_smt == -1 || num_core == -1) return 0; data->num_logical_cpus = num_core; @@ -1003,7 +915,7 @@ int cpuid_identify_intel(struct cpu_raw_data_t* raw, struct cpu_id_t* data, stru load_intel_features(raw, data); if (raw->basic_cpuid[0][EAX] >= 4) { /* Deterministic way is preferred, being more generic */ - decode_intel_deterministic_cache_info(raw, data); + decode_deterministic_cache_info_x86(raw->intel_fn4, MAX_INTELFN4_LEVEL, data, internal); } else if (raw->basic_cpuid[0][EAX] >= 2) { decode_intel_oldstyle_cache_info(raw, data); } diff --git a/tests/amd/bobcat/brazos-zacate.test b/tests/amd/bobcat/brazos-zacate.test index a37f8dd..0d920a3 100644 --- a/tests/amd/bobcat/brazos-zacate.test +++ b/tests/amd/bobcat/brazos-zacate.test @@ -83,7 +83,7 @@ general 32 32 512 -0 +-1 -1 8 2 diff --git a/tests/amd/bulldozer/godavari-x4.test b/tests/amd/bulldozer/godavari-x4.test index 59e9c4d..b2218e0 100644 --- a/tests/amd/bulldozer/godavari-x4.test +++ b/tests/amd/bulldozer/godavari-x4.test @@ -91,7 +91,7 @@ general 16 96 2048 -0 +-1 -1 4 3 diff --git a/tests/amd/bulldozer/kaveri-x4.test b/tests/amd/bulldozer/kaveri-x4.test index bffe90b..b46d3f2 100644 --- a/tests/amd/bulldozer/kaveri-x4.test +++ b/tests/amd/bulldozer/kaveri-x4.test @@ -91,7 +91,7 @@ general 16 96 2048 -0 +-1 -1 4 3 diff --git a/tests/amd/k10/athlon-2-champlain-mobile.test b/tests/amd/k10/athlon-2-champlain-mobile.test index 8bbb22e..5814309 100644 --- a/tests/amd/k10/athlon-2-champlain-mobile.test +++ b/tests/amd/k10/athlon-2-champlain-mobile.test @@ -83,7 +83,7 @@ general 64 64 512 -0 +-1 -1 2 2 diff --git a/tests/amd/k10/athlon-2-propus-2.test b/tests/amd/k10/athlon-2-propus-2.test index e60c77f..6916966 100644 --- a/tests/amd/k10/athlon-2-propus-2.test +++ b/tests/amd/k10/athlon-2-propus-2.test @@ -83,7 +83,7 @@ general 64 64 512 -0 +-1 -1 2 2 diff --git a/tests/amd/k10/athlon-2-propus-3.test b/tests/amd/k10/athlon-2-propus-3.test index 5cca219..c53da91 100644 --- a/tests/amd/k10/athlon-2-propus-3.test +++ b/tests/amd/k10/athlon-2-propus-3.test @@ -83,7 +83,7 @@ general 64 64 512 -0 +-1 -1 2 2 diff --git a/tests/amd/k10/athlon-2-propus.test b/tests/amd/k10/athlon-2-propus.test index e60c77f..6916966 100644 --- a/tests/amd/k10/athlon-2-propus.test +++ b/tests/amd/k10/athlon-2-propus.test @@ -83,7 +83,7 @@ general 64 64 512 -0 +-1 -1 2 2 diff --git a/tests/amd/k10/athlon-2-regor.test b/tests/amd/k10/athlon-2-regor.test index 08f95c7..c453511 100644 --- a/tests/amd/k10/athlon-2-regor.test +++ b/tests/amd/k10/athlon-2-regor.test @@ -83,7 +83,7 @@ general 64 64 1024 -0 +-1 -1 2 2 diff --git a/tests/amd/k10/sempron-sargas.test b/tests/amd/k10/sempron-sargas.test index e717f9c..6e887f8 100644 --- a/tests/amd/k10/sempron-sargas.test +++ b/tests/amd/k10/sempron-sargas.test @@ -83,7 +83,7 @@ general 64 64 1024 -0 +-1 -1 2 2 diff --git a/tests/amd/k7/athlon-thoroughbred.test b/tests/amd/k7/athlon-thoroughbred.test index 2892613..4d37592 100644 --- a/tests/amd/k7/athlon-thoroughbred.test +++ b/tests/amd/k7/athlon-thoroughbred.test @@ -79,7 +79,7 @@ general 64 64 256 -0 +-1 -1 2 2 diff --git a/tests/amd/k7/duron-applebred.test b/tests/amd/k7/duron-applebred.test index 091ea89..5081aaf 100644 --- a/tests/amd/k7/duron-applebred.test +++ b/tests/amd/k7/duron-applebred.test @@ -79,7 +79,7 @@ general 64 64 64 -0 +-1 -1 2 2 diff --git a/tests/amd/k7/sempron-barton.test b/tests/amd/k7/sempron-barton.test index fdb609e..b1461bd 100644 --- a/tests/amd/k7/sempron-barton.test +++ b/tests/amd/k7/sempron-barton.test @@ -79,7 +79,7 @@ general 64 64 512 -0 +-1 -1 2 2 diff --git a/tests/amd/k8/athlon-64-brisbane.test b/tests/amd/k8/athlon-64-brisbane.test index f679fa8..d9f8406 100644 --- a/tests/amd/k8/athlon-64-brisbane.test +++ b/tests/amd/k8/athlon-64-brisbane.test @@ -79,7 +79,7 @@ general 64 64 512 -0 +-1 -1 2 2 diff --git a/tests/amd/k8/athlon-64-venice.test b/tests/amd/k8/athlon-64-venice.test index df970a1..a191388 100644 --- a/tests/amd/k8/athlon-64-venice.test +++ b/tests/amd/k8/athlon-64-venice.test @@ -79,7 +79,7 @@ general 64 64 512 -0 +-1 -1 2 2 diff --git a/tests/amd/k8/mobile-sempron-64-keene.test b/tests/amd/k8/mobile-sempron-64-keene.test index cbd48d2..3cf8225 100644 --- a/tests/amd/k8/mobile-sempron-64-keene.test +++ b/tests/amd/k8/mobile-sempron-64-keene.test @@ -79,7 +79,7 @@ general 64 64 512 -0 +-1 -1 2 2 diff --git a/tests/amd/k8/mobile-sempron-64-sonora.test b/tests/amd/k8/mobile-sempron-64-sonora.test index 11db5be..6f15535 100644 --- a/tests/amd/k8/mobile-sempron-64-sonora.test +++ b/tests/amd/k8/mobile-sempron-64-sonora.test @@ -79,7 +79,7 @@ general 64 64 128 -0 +-1 -1 2 2 diff --git a/tests/amd/k8/opteron-denmark.test b/tests/amd/k8/opteron-denmark.test index 4dbd0e5..d9ca017 100644 --- a/tests/amd/k8/opteron-denmark.test +++ b/tests/amd/k8/opteron-denmark.test @@ -79,7 +79,7 @@ general 64 64 1024 -0 +-1 -1 2 2 diff --git a/tests/amd/k8/sempron-64-sparta.test b/tests/amd/k8/sempron-64-sparta.test index 395440b..e15d6da 100644 --- a/tests/amd/k8/sempron-64-sparta.test +++ b/tests/amd/k8/sempron-64-sparta.test @@ -79,7 +79,7 @@ general 64 64 256 -0 +-1 -1 2 2 diff --git a/tests/amd/k8/turion-64-lancaster.test b/tests/amd/k8/turion-64-lancaster.test index a78402f..ed8a368 100644 --- a/tests/amd/k8/turion-64-lancaster.test +++ b/tests/amd/k8/turion-64-lancaster.test @@ -79,7 +79,7 @@ general 64 64 1024 -0 +-1 -1 2 2 diff --git a/tests/amd/zen2/epyc-rome.test b/tests/amd/zen2/epyc-rome.test index c23060e..0ace3ee 100644 --- a/tests/amd/zen2/epyc-rome.test +++ b/tests/amd/zen2/epyc-rome.test @@ -91,7 +91,7 @@ general 32 32 512 -262144 +16384 -1 8 8 diff --git a/tests/amd/zen2/ryzen5-lucienne.test b/tests/amd/zen2/ryzen5-lucienne.test index 06a6766..3833cfc 100644 --- a/tests/amd/zen2/ryzen5-lucienne.test +++ b/tests/amd/zen2/ryzen5-lucienne.test @@ -91,7 +91,7 @@ general 32 32 512 -8192 +4096 -1 8 8 diff --git a/tests/amd/zen2/ryzen5-matisse.test b/tests/amd/zen2/ryzen5-matisse.test index adeab2b..dc41e58 100644 --- a/tests/amd/zen2/ryzen5-matisse.test +++ b/tests/amd/zen2/ryzen5-matisse.test @@ -983,7 +983,7 @@ general 32 32 512 -32768 +16384 -1 8 8 diff --git a/tests/amd/zen2/ryzen5-renoir.test b/tests/amd/zen2/ryzen5-renoir.test index 701c707..31b6fd3 100644 --- a/tests/amd/zen2/ryzen5-renoir.test +++ b/tests/amd/zen2/ryzen5-renoir.test @@ -91,7 +91,7 @@ general 32 32 512 -8192 +4096 -1 8 8 diff --git a/tests/amd/zen2/ryzen7-lucienne.test b/tests/amd/zen2/ryzen7-lucienne.test index bb2a104..3406c91 100644 --- a/tests/amd/zen2/ryzen7-lucienne.test +++ b/tests/amd/zen2/ryzen7-lucienne.test @@ -91,7 +91,7 @@ general 32 32 512 -8192 +4096 -1 8 8 diff --git a/tests/amd/zen2/ryzen7-matisse.test b/tests/amd/zen2/ryzen7-matisse.test index a3a2237..f236de5 100644 --- a/tests/amd/zen2/ryzen7-matisse.test +++ b/tests/amd/zen2/ryzen7-matisse.test @@ -91,7 +91,7 @@ general 32 32 512 -32768 +16384 -1 8 8 diff --git a/tests/amd/zen2/ryzen7-renoir.test b/tests/amd/zen2/ryzen7-renoir.test index 40aecdd..d442d0a 100644 --- a/tests/amd/zen2/ryzen7-renoir.test +++ b/tests/amd/zen2/ryzen7-renoir.test @@ -91,7 +91,7 @@ general 32 32 512 -8192 +4096 -1 8 8 diff --git a/tests/amd/zen2/ryzen9-matisse.test b/tests/amd/zen2/ryzen9-matisse.test index 811b8ca..75616a3 100644 --- a/tests/amd/zen2/ryzen9-matisse.test +++ b/tests/amd/zen2/ryzen9-matisse.test @@ -91,7 +91,7 @@ general 32 32 512 -65536 +16384 -1 8 8 diff --git a/tests/amd/zen2/threadripper-castle-peak.test b/tests/amd/zen2/threadripper-castle-peak.test index da30bee..96bff75 100644 --- a/tests/amd/zen2/threadripper-castle-peak.test +++ b/tests/amd/zen2/threadripper-castle-peak.test @@ -91,7 +91,7 @@ general 32 32 512 -131072 +16384 -1 8 8 diff --git a/tests/amd/zen3/epyc-milan.test b/tests/amd/zen3/epyc-milan.test index 9593841..afece8a 100644 --- a/tests/amd/zen3/epyc-milan.test +++ b/tests/amd/zen3/epyc-milan.test @@ -91,7 +91,7 @@ general 32 32 512 -262144 +32768 -1 8 8 diff --git a/tests/amd/zen3/ryzen7-warhol.test b/tests/amd/zen3/ryzen7-warhol.test deleted file mode 100644 index a3fd780..0000000 --- a/tests/amd/zen3/ryzen7-warhol.test +++ /dev/null @@ -1,108 +0,0 @@ -basic_cpuid[0]=00000010 68747541 444d4163 69746e65 -basic_cpuid[1]=00a20f12 00100800 7ef8320b 178bfbff -basic_cpuid[2]=00000000 00000000 00000000 00000000 -basic_cpuid[3]=00000000 00000000 00000000 00000000 -basic_cpuid[4]=00000000 00000000 00000000 00000000 -basic_cpuid[5]=00000040 00000040 00000003 00000011 -basic_cpuid[6]=00000004 00000000 00000001 00000000 -basic_cpuid[7]=00000000 219c95a9 0040068c 00000000 -basic_cpuid[8]=00000000 00000000 00000000 00000000 -basic_cpuid[9]=00000000 00000000 00000000 00000000 -basic_cpuid[10]=00000000 00000000 00000000 00000000 -basic_cpuid[11]=00000001 00000002 00000100 00000000 -basic_cpuid[12]=00000000 00000000 00000000 00000000 -basic_cpuid[13]=00000207 00000340 00000988 00000000 -basic_cpuid[14]=00000000 00000000 00000000 00000000 -basic_cpuid[15]=00000000 000000ff 00000000 00000002 -basic_cpuid[16]=00000000 00000002 00000000 00000000 -basic_cpuid[17]=ffffffff ffffffff ffffffff ffffffff -basic_cpuid[18]=ffffffff ffffffff ffffffff ffffffff -basic_cpuid[19]=ffffffff ffffffff ffffffff ffffffff -basic_cpuid[20]=ffffffff ffffffff ffffffff ffffffff -basic_cpuid[21]=ffffffff ffffffff ffffffff ffffffff -basic_cpuid[22]=ffffffff ffffffff ffffffff ffffffff -basic_cpuid[23]=ffffffff ffffffff ffffffff ffffffff -basic_cpuid[24]=ffffffff ffffffff ffffffff ffffffff -basic_cpuid[25]=ffffffff ffffffff ffffffff ffffffff -basic_cpuid[26]=ffffffff ffffffff ffffffff ffffffff -basic_cpuid[27]=ffffffff ffffffff ffffffff ffffffff -basic_cpuid[28]=ffffffff ffffffff ffffffff ffffffff -basic_cpuid[29]=ffffffff ffffffff ffffffff ffffffff -basic_cpuid[30]=ffffffff ffffffff ffffffff ffffffff -basic_cpuid[31]=ffffffff ffffffff ffffffff ffffffff -ext_cpuid[0]=80000023 68747541 444d4163 69746e65 -ext_cpuid[1]=00a20f12 20000000 75c237ff 2fd3fbff -ext_cpuid[2]=20444d41 657a7952 2037206e 30303835 -ext_cpuid[3]=20443358 6f432d38 50206572 65636f72 -ext_cpuid[4]=726f7373 20202020 20202020 00202020 -ext_cpuid[5]=ff40ff40 ff40ff40 20080140 20080140 -ext_cpuid[6]=48002200 68004200 02006140 03009140 -ext_cpuid[7]=00000000 0000003b 00000000 00006799 -ext_cpuid[8]=00003030 111ef657 0000400f 00010000 -ext_cpuid[9]=00000000 00000000 00000000 00000000 -ext_cpuid[10]=00000001 00008000 00000000 101bbcff -ext_cpuid[11]=00000000 00000000 00000000 00000000 -ext_cpuid[12]=00000000 00000000 00000000 00000000 -ext_cpuid[13]=00000000 00000000 00000000 00000000 -ext_cpuid[14]=00000000 00000000 00000000 00000000 -ext_cpuid[15]=00000000 00000000 00000000 00000000 -ext_cpuid[16]=00000000 00000000 00000000 00000000 -ext_cpuid[17]=00000000 00000000 00000000 00000000 -ext_cpuid[18]=00000000 00000000 00000000 00000000 -ext_cpuid[19]=00000000 00000000 00000000 00000000 -ext_cpuid[20]=00000000 00000000 00000000 00000000 -ext_cpuid[21]=00000000 00000000 00000000 00000000 -ext_cpuid[22]=00000000 00000000 00000000 00000000 -ext_cpuid[23]=00000000 00000000 00000000 00000000 -ext_cpuid[24]=00000000 00000000 00000000 00000000 -ext_cpuid[25]=f040f040 f0400000 00000000 00000000 -ext_cpuid[26]=00000006 00000000 00000000 00000000 -ext_cpuid[27]=000003ff 00000000 00000000 00000000 -ext_cpuid[28]=00000000 00000000 00000000 00000000 -ext_cpuid[29]=00004121 01c0003f 0000003f 00000000 -ext_cpuid[30]=00000000 00000100 00000000 00000000 -ext_cpuid[31]=0001780f 00000173 000001fd 00000001 -intel_fn4[0]=ffffffff ffffffff ffffffff ffffffff -intel_fn4[1]=ffffffff ffffffff ffffffff ffffffff -intel_fn4[2]=ffffffff ffffffff ffffffff ffffffff -intel_fn4[3]=ffffffff ffffffff ffffffff ffffffff -intel_fn4[4]=ffffffff ffffffff ffffffff ffffffff -intel_fn4[5]=ffffffff ffffffff ffffffff ffffffff -intel_fn4[6]=ffffffff ffffffff ffffffff ffffffff -intel_fn4[7]=ffffffff ffffffff ffffffff ffffffff -intel_fn11[0]=ffffffff ffffffff ffffffff ffffffff -intel_fn11[1]=ffffffff ffffffff ffffffff ffffffff -intel_fn11[2]=ffffffff ffffffff ffffffff ffffffff -intel_fn11[3]=ffffffff ffffffff ffffffff ffffffff -amd_fn8000001dh[0]=ffffffff ffffffff ffffffff ffffffff -amd_fn8000001dh[1]=ffffffff ffffffff ffffffff ffffffff -amd_fn8000001dh[2]=ffffffff ffffffff ffffffff ffffffff -amd_fn8000001dh[3]=ffffffff ffffffff ffffffff ffffffff --------------------------------------------------------------------------------- -x86 -general -15 -1 -2 -25 -33 -8 -16 -32 -32 -512 -98304 --1 -8 -8 -8 -1024 --1 -64 -64 -64 -4096 --1 -256 (authoritative) -Ryzen 7 (Warhol) -fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd hwpstate constant_tsc fma3 f16c rdrand cpb aperfmperf avx2 bmi1 bmi2 sha_ni rdseed adx diff --git a/tests/amd/zen3/ryzen9-vermeer.test b/tests/amd/zen3/ryzen9-vermeer.test index d1f0a7e..c8575f8 100644 --- a/tests/amd/zen3/ryzen9-vermeer.test +++ b/tests/amd/zen3/ryzen9-vermeer.test @@ -91,7 +91,7 @@ general 32 32 512 -65536 +32768 -1 8 8