From 1344ec1a81279a6e29b2d2cfa308f0392cee96c3 Mon Sep 17 00:00:00 2001 From: Veselin Georgiev Date: Sat, 26 May 2012 13:00:04 +0000 Subject: [PATCH] Added support for detecting the following processors: The newer 6 and 8-core Sandy Bridges (termed Sandy Bridge-E), Ivy Bridge, AMD Magny-Cours. Added support for detecting the rdrand instruction. Added tests. git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@104 3b4be424-7ac5-41d7-8526-f4ddcb85d872 --- libcpuid/cpuid_main.c | 2 +- libcpuid/libcpuid.h | 3 + libcpuid/recog_amd.c | 4 + libcpuid/recog_intel.c | 39 ++++- tests/tests_stash.txt | 376 +++++++++++++++++++++++++++++++++++++++++ 5 files changed, 418 insertions(+), 6 deletions(-) diff --git a/libcpuid/cpuid_main.c b/libcpuid/cpuid_main.c index defa873..7ace74b 100644 --- a/libcpuid/cpuid_main.c +++ b/libcpuid/cpuid_main.c @@ -544,7 +544,7 @@ const char* cpu_feature_str(cpu_feature_t feature) { CPU_FEATURE_FMA4, "fma4" }, { CPU_FEATURE_TBM, "tbm" }, { CPU_FEATURE_F16C, "f16c" }, - + { CPU_FEATURE_RDRAND, "rdrand" }, }; unsigned i, n = COUNT_OF(matchtable); if (n != NUM_CPU_FEATURES) { diff --git a/libcpuid/libcpuid.h b/libcpuid/libcpuid.h index bfadb6b..c42406d 100644 --- a/libcpuid/libcpuid.h +++ b/libcpuid/libcpuid.h @@ -43,6 +43,8 @@ * 0.2.0 (2011-10-11): Support for AMD Bulldozer CPUs, 128-bit SSE unit size * checking. A backwards-incompatible change, since the * sizeof cpu_id_t is now different. + * 0.2.1 (2012-05-26): Support for Ivy Bridge, and detecting the presence of + * the RdRand instruction. */ /** @mainpage A simple libcpuid introduction @@ -346,6 +348,7 @@ typedef enum { CPU_FEATURE_FMA4, /*!< The FMA4 instruction set */ CPU_FEATURE_TBM, /*!< Trailing bit manipulation instruction support */ CPU_FEATURE_F16C, /*!< 16-bit FP convert instruction support */ + CPU_FEATURE_RDRAND, /*!< RdRand instruction */ /* termination: */ NUM_CPU_FEATURES, } cpu_feature_t; diff --git a/libcpuid/recog_amd.c b/libcpuid/recog_amd.c index 62eeae8..3daa297 100644 --- a/libcpuid/recog_amd.c +++ b/libcpuid/recog_amd.c @@ -251,6 +251,10 @@ const struct match_entry_t cpudb_amd[] = { { 15, -1, -1, 18, 1, 2, 1024, -1, FUSION_EA , 0, "Llano X2" }, { 15, -1, -1, 18, 1, 3, 1024, -1, FUSION_EA , 0, "Llano X3" }, { 15, -1, -1, 18, 1, 4, 1024, -1, FUSION_EA , 0, "Llano X4" }, + + /* Newer Opterons: */ + { 15, 9, -1, 16, 9, 8, -1, -1, OPTERON_GENERIC , 0, "Magny-Cours Opteron" }, + /* Bulldozer CPUs: */ { 15, -1, -1, 21, 1, 2, 2048, -1, NO_CODE , 0, "Bulldozer X2" }, { 15, -1, -1, 21, 1, 2, 4096, -1, NO_CODE , 0, "Bulldozer X2" }, diff --git a/libcpuid/recog_intel.c b/libcpuid/recog_intel.c index dfb6c2f..e0efe03 100644 --- a/libcpuid/recog_intel.c +++ b/libcpuid/recog_intel.c @@ -64,6 +64,9 @@ enum _intel_code_t { CORE_I3, CORE_I5, CORE_I7, + CORE_IVY3, /* 22nm Core-iX */ + CORE_IVY5, + CORE_IVY7, }; typedef enum _intel_code_t intel_code_t; @@ -79,6 +82,8 @@ enum _intel_model_t { _5200, _5300, _5400, + _2xxx, /* Core i[357] 2xxx */ + _3xxx, /* Core i[357] 3xxx */ }; typedef enum _intel_model_t intel_model_t; @@ -259,8 +264,10 @@ const struct match_entry_t cpudb_intel[] = { { 6, 10, -1, -1, 42, -1, -1, -1, CORE_I7 , 0, "Sandy Bridge i7" }, { 6, 10, -1, -1, 42, 4, -1, -1, CORE_I7 , 0, "Sandy Bridge (Core i7)" }, { 6, 10, -1, -1, 42, 4, -1, -1, CORE_I5 , 0, "Sandy Bridge (Core i5)" }, + { 6, 10, -1, -1, 42, 2, -1, -1, CORE_I3 , 0, "Sandy Bridge (Core i3)" }, { 6, 10, -1, -1, 42, 1, -1, -1, CELERON , 0, "Celeron (Sandy Bridge)" }, { 6, 10, -1, -1, 42, 2, -1, -1, CELERON , 0, "Celeron (Sandy Bridge)" }, + { 6, 10, -1, -1, 42, 2, -1, -1, PENTIUM , 0, "Pentium (Sandy Bridge)" }, { 6, 10, -1, -1, 26, 1, -1, -1, CORE_I7 , 0, "Intel Core i7" }, { 6, 10, -1, -1, 26, 4, -1, -1, CORE_I7 , 0, "Bloomfield (Core i7)" }, @@ -274,8 +281,17 @@ const struct match_entry_t cpudb_intel[] = { { 6, 12, -1, -1, 44, -1, -1, -1, XEON_WESTMERE , 0, "Xeon (Westmere-based)" }, { 6, 12, -1, -1, 44, 4, -1, 12288, CORE_I7 , 0, "Gulftown (Core i7)" }, { 6, 12, -1, -1, 44, -1, -1, 12288, XEON_WESTMERE , 0, "Xeon (Gulftown)" }, + + { 6, 13, -1, -1, 45, -1, -1, -1, XEON , 0, "Xeon (Sandy Bridge)" }, - + { 6, 13, -1, -1, 45, -1, -1, -1, CORE_I7 , 0, "Sandy Bridge-E (Core i7)" }, + { 6, 13, -1, -1, 45, -1, -1, -1, CORE_I5 , 0, "Sandy Bridge-E (Core i5)" }, + { 6, 13, -1, -1, 45, -1, -1, -1, CORE_I3 , 0, "Sandy Bridge-E (Core i3)" }, + + { 6, 10, -1, -1, 58, 4, -1, -1, CORE_IVY7 , 0, "Ivy Bridge (Core i7)" }, + { 6, 10, -1, -1, 58, 4, -1, -1, CORE_IVY5 , 0, "Ivy Bridge (Core i5)" }, + { 6, 10, -1, -1, 58, 2, -1, -1, CORE_IVY3 , 0, "Ivy Bridge (Core i3)" }, + /* Core microarchitecture-based Xeons: */ { 6, 14, -1, -1, 14, 1, -1, -1, XEON , 0, "Xeon LV" }, @@ -326,6 +342,7 @@ static void load_intel_features(struct cpu_raw_data_t* raw, struct cpu_id_t* dat { 26, CPU_FEATURE_XSAVE }, { 27, CPU_FEATURE_OSXSAVE }, { 28, CPU_FEATURE_AVX }, + { 30, CPU_FEATURE_RDRAND }, }; const struct feature_map_t matchtable_edx81[] = { { 20, CPU_FEATURE_XD }, @@ -556,7 +573,7 @@ static void decode_intel_number_of_cores(struct cpu_raw_data_t* raw, static intel_code_t get_brand_code(struct cpu_id_t* data) { intel_code_t code = NO_CODE; - int i, need_matchtable = 1; + int i, need_matchtable = 1, ivy_bridge = 0; const char* bs = data->brand_str; const char* s; const struct { intel_code_t c; const char *search; } matchtable[] = { @@ -586,10 +603,12 @@ static intel_code_t get_brand_code(struct cpu_id_t* data) if ((i = match_pattern(bs, "Core(TM) i[357]")) != 0) { /* Core i3, Core i5 or Core i7 */ need_matchtable = 0; + if (data->flags[CPU_FEATURE_RDRAND]) + ivy_bridge = 1; switch (bs[i + 9]) { - case '3': code = CORE_I3; break; - case '5': code = CORE_I5; break; - case '7': code = CORE_I7; break; + case '3': code = ivy_bridge ? CORE_IVY3 : CORE_I3; break; + case '5': code = ivy_bridge ? CORE_IVY5 : CORE_I5; break; + case '7': code = ivy_bridge ? CORE_IVY7 : CORE_I7; break; } } if (need_matchtable) { @@ -664,6 +683,16 @@ static intel_model_t get_model_code(struct cpu_id_t* data) int l = (int) strlen(data->brand_str); const char *bs = data->brand_str; int mod_flags = 0, model_no = 0, ndigs = 0; + /* If the CPU is a Core ix, then just return the model number generation: */ + if ((i = match_pattern(bs, "Core(TM) i[357]")) != 0) { + i += 11; + if (i + 4 >= l) return UNKNOWN; + if (bs[i] == '2') return _2xxx; + if (bs[i] == '3') return _3xxx; + return UNKNOWN; + } + + /* For Core2-based Xeons: */ while (i < l - 3) { if (bs[i] == 'C' && bs[i+1] == 'P' && bs[i+2] == 'U') break; diff --git a/tests/tests_stash.txt b/tests/tests_stash.txt index b0f6569..6f6000c 100644 --- a/tests/tests_stash.txt +++ b/tests/tests_stash.txt @@ -5318,3 +5318,379 @@ intel_fn11[3]=00000000 00000000 00000003 00000000 Celeron (Sandy Bridge) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd popcnt xsave lm lahf_lm -------------------------------------------------------------------------------- +basic_cpuid[0]=0000000d 756e6547 6c65746e 49656e69 +basic_cpuid[1]=000206d7 00200800 1fbee3ff bfebfbff +basic_cpuid[2]=76035a01 00f0b2ff 00000000 00ca0000 +basic_cpuid[3]=00000000 00000000 00000000 00000000 +basic_cpuid[4]=3c004121 01c0003f 0000003f 00000000 +basic_cpuid[5]=00000040 00000040 00000003 00021120 +basic_cpuid[6]=00000077 00000002 00000009 00000000 +basic_cpuid[7]=00000000 00000000 00000000 00000000 +basic_cpuid[8]=00000000 00000000 00000000 00000000 +basic_cpuid[9]=00000001 00000000 00000000 00000000 +basic_cpuid[10]=07300403 00000000 00000000 00000603 +basic_cpuid[11]=00000001 00000002 00000100 00000000 +basic_cpuid[12]=00000000 00000000 00000000 00000000 +basic_cpuid[13]=00000007 00000340 00000340 00000000 +basic_cpuid[14]=00000007 00000340 00000340 00000000 +basic_cpuid[15]=00000007 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00000000 00000000 00000000 +ext_cpuid[27]=0000001f 00000000 00000000 00000000 +ext_cpuid[28]=00000000 00000000 00000000 00000000 +ext_cpuid[29]=00000000 00000000 00000000 00000000 +ext_cpuid[30]=00000000 00000000 00000000 00000000 +ext_cpuid[31]=00000000 00000000 00000000 00000000 +intel_fn4[0]=00000000 00000000 00000000 00000000 +intel_fn4[1]=00000000 00000000 00000000 00000000 +intel_fn4[2]=00000000 00000000 00000000 00000000 +intel_fn4[3]=00000000 00000000 00000000 00000000 +intel_fn11[0]=00000000 00000000 00000000 00000000 +intel_fn11[1]=00000000 00000000 00000000 00000000 +intel_fn11[2]=00000000 00000000 00000000 00000000 +intel_fn11[3]=00000000 00000000 00000000 00000000 +-------------------------------------------------------------------------------- +15 +9 +1 +16 +9 +12 +12 +64 +64 +512 +10240 +2 +16 +92 +64 +64 +64 +128 (authoritative) +Magny-Cours Opteron +fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni monitor cx16 syscall popcnt mmxext 3dnow 3dnowext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd stc 100mhzsteps hwpstate constant_tsc +--------------------------------------------------------------------------------