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https://github.com/anrieff/libcpuid
synced 2024-11-10 22:59:13 +00:00
Improve/clean code for cpu_msrinfo()
* Add AMD and Intel doc links * Use 'return' only if there is no error; on error, the end-function 'return CPU_INVALID_VALUE' is used * Add more comments about MSRs * Simplify a lot of things * Avoid cpu_rdmsr_range() to override cpu_rdmsr() error * Remove int casting in cpu_msrinfo()
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Xorg
parent
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1 changed files with 121 additions and 70 deletions
185
libcpuid/rdmsr.c
185
libcpuid/rdmsr.c
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@ -465,6 +465,23 @@ int cpu_msrinfo(struct msr_driver_t* driver, cpu_msrinfo_request_t which)
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#endif /* Unsupported OS */
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/* Useful links for hackers:
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- AMD MSRs:
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AMD BIOS and Kernel Developer’s Guide (BKDG)
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* AMD Family 10h Processors
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http://support.amd.com/TechDocs/31116.pdf
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* AMD Family 15h Models 00h-0Fh Processors
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http://support.amd.com/TechDocs/42301_15h_Mod_00h-0Fh_BKDG.pdf
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* AMD Family 15h Models 30h-3Fh
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http://support.amd.com/TechDocs/49125_15h_Models_30h-3Fh_BKDG.pdf
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- Intel MSRs:
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Intel® 64 and IA-32 Architectures Software Developer’s Manual
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* Volume 3 (3A, 3B, 3C & 3D): System Programming Guide
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http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-system-programming-manual-325384.pdf
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*/
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static int rdmsr_supported(void)
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{
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struct cpu_id_t* id = get_cached_cpuid();
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@ -489,74 +506,92 @@ static int perfmsr_measure(struct msr_driver_t* handle, int msr)
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static double get_info_cur_multiplier(struct msr_driver_t* handle, struct cpu_id_t *id,
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struct internal_id_info_t *internal)
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{
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int err, cur_clock;
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uint64_t r;
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static double bclk = 0.0;
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#define IA32_PERF_STATUS 0x198
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int err;
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uint64_t reg;
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if(id->vendor == VENDOR_INTEL && internal->code.intel == PENTIUM) {
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err = cpu_rdmsr(handle, 0x2a, &r);
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if (err) return CPU_INVALID_VALUE;
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return (r>>22) & 0x1f;
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err = cpu_rdmsr(handle, 0x2a, ®);
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if (!err) return (reg>>22) & 0x1f;
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}
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else if(id->vendor == VENDOR_INTEL && internal->code.intel != PENTIUM) {
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if(!bclk)
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bclk = (double) cpu_msrinfo(handle, INFO_BCLK) / 100;
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if(bclk > 0) {
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cur_clock = cpu_clock_by_ic(10, 4);
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if(cur_clock > 0)
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return cur_clock / bclk;
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}
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/* Refer links above
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Table 35-2. IA-32 Architectural MSRs (Contd.)
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IA32_PERF_STATUS[15:0] is Current performance State Value
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[7:0] is 0x0, [15:8] looks like current ratio */
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err = cpu_rdmsr_range(handle, IA32_PERF_STATUS, 15, 8, ®);
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if (!err) return reg;
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}
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return CPU_INVALID_VALUE;
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#undef IA32_PERF_STATUS
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}
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static double get_info_max_multiplier(struct msr_driver_t* handle, struct cpu_id_t *id,
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struct internal_id_info_t *internal)
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{
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#define PLATFORM_INFO_MSR 206
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#define PLATFORM_INFO_MSR_low 8
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#define PLATFORM_INFO_MSR_high 15
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#define MSR_TURBO_RATIO_LIMIT 0x1ad
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int err;
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uint64_t val, r;
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static int multiplier = 0;
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uint64_t reg;
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if(id->vendor == VENDOR_INTEL && internal->code.intel == PENTIUM) {
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err = cpu_rdmsr(handle, 0x198, &r);
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if (err) return CPU_INVALID_VALUE;
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return (r >> 40) & 0x1f;
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err = cpu_rdmsr(handle, 0x198, ®);
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if (!err) return (reg >> 40) & 0x1f;
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}
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else if(id->vendor == VENDOR_INTEL && internal->code.intel != PENTIUM) {
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if(!multiplier) {
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cpu_rdmsr_range(handle, PLATFORM_INFO_MSR, PLATFORM_INFO_MSR_high, PLATFORM_INFO_MSR_low, &val);
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multiplier = (int) val;
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}
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if(multiplier > 0)
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return multiplier;
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/* Refer links above
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Table 35-10. Specific MSRs Supported by Intel® Atom™ Processor C2000 Series with CPUID Signature 06_4DH
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Table 35-12. MSRs in Next Generation Intel Atom Processors Based on the Goldmont Microarchitecture (Contd.)
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Table 35-13. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.)
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Table 35-14. Additional MSRs in Intel® Xeon® Processor 5500 and 3400 Series
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Table 35-16. Additional MSRs Supported by Intel Processors (Based on Intel® Microarchitecture Code Name Westmere)
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Table 35-19. MSRs Supported by 2nd Generation Intel® Core™ Processors (Intel® microarchitecture code name Sandy Bridge)
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Table 35-21. Selected MSRs Supported by Intel® Xeon® Processors E5 Family (based on Sandy Bridge microarchitecture)
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Table 35-28. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell microarchitecture) (Contd.)
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Table 35-30. Additional MSRs Supported by Intel® Xeon® Processor E5 v3 Family
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Table 35-33. Additional MSRs Supported by Intel® Core™ M Processors and 5th Generation Intel® Core™ Processors
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Table 35-34. Additional MSRs Common to Intel® Xeon® Processor D and Intel Xeon Processors E5 v4 Family Based on the Broadwell Microarchitecture
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Table 35-37. Additional MSRs Supported by 6th Generation Intel® Core™ Processors Based on Skylake Microarchitecture
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Table 35-40. Selected MSRs Supported by Next Generation Intel® Xeon Phi™ Processors with DisplayFamily_DisplayModel Signature 06_57H
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MSR_TURBO_RATIO_LIMIT[7:0] is Maximum Ratio Limit for 1C */
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err = cpu_rdmsr_range(handle, MSR_TURBO_RATIO_LIMIT, 7, 0, ®);
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if (!err) return reg;
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}
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return CPU_INVALID_VALUE;
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#undef MSR_TURBO_RATIO_LIMIT
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}
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static int get_info_temperature(struct msr_driver_t* handle, struct cpu_id_t *id,
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struct internal_id_info_t *internal)
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{
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#define IA32_THERM_STATUS 0x19C
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#define IA32_TEMPERATURE_TARGET 0x1a2
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uint64_t digital_readout, thermal_status, PROCHOT_temp;
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#define MSR_TEMPERATURE_TARGET 0x1a2
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int err;
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uint64_t DigitalReadout, ReadingValid, TemperatureTarget;
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if(id->vendor == VENDOR_INTEL && internal->code.intel != PENTIUM) {
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// https://github.com/ajaiantilal/i7z/blob/5023138d7c35c4667c938b853e5ea89737334e92/helper_functions.c#L59
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cpu_rdmsr_range(handle, IA32_THERM_STATUS, 23, 16, &digital_readout);
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cpu_rdmsr_range(handle, IA32_THERM_STATUS, 32, 31, &thermal_status);
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cpu_rdmsr_range(handle, IA32_TEMPERATURE_TARGET, 23, 16, &PROCHOT_temp);
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/* Refer links above
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Table 35-2. IA-32 Architectural MSRs
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IA32_THERM_STATUS[22:16] is Digital Readout
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IA32_THERM_STATUS[31] is Reading Valid
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// These bits are thermal status : 1 if supported, 0 else
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if(thermal_status)
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return(PROCHOT_temp - digital_readout); // Temperature is prochot - digital readout
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Table 35-6. MSRs Common to the Silvermont Microarchitecture and Newer Microarchitectures for Intel® Atom
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Table 35-13. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.)
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Table 35-18. MSRs Supported by Intel® Processors based on Intel® microarchitecture code name Sandy Bridge (Contd.)
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Table 35-24. MSRs Supported by Intel® Xeon® Processors E5 v2 Product Family (based on Ivy Bridge-E microarchitecture) (Contd.)
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Table 35-34. Additional MSRs Common to Intel® Xeon® Processor D and Intel Xeon Processors E5 v4 Family Based on the Broadwell Microarchitecture
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Table 35-40. Selected MSRs Supported by Next Generation Intel® Xeon Phi™ Processors with DisplayFamily_DisplayModel Signature 06_57H
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MSR_TEMPERATURE_TARGET[23:16] is Temperature Target */
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err = cpu_rdmsr_range(handle, IA32_THERM_STATUS, 22, 16, &DigitalReadout);
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err += cpu_rdmsr_range(handle, IA32_THERM_STATUS, 31, 31, &ReadingValid);
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err += cpu_rdmsr_range(handle, MSR_TEMPERATURE_TARGET, 23, 16, &TemperatureTarget);
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if(!err && ReadingValid) return TemperatureTarget - DigitalReadout;
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}
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return CPU_INVALID_VALUE;
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#undef IA32_THERM_STATUS
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#undef MSR_TEMPERATURE_TARGET
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}
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static double get_info_voltage(struct msr_driver_t* handle, struct cpu_id_t *id,
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@ -565,66 +600,82 @@ static double get_info_voltage(struct msr_driver_t* handle, struct cpu_id_t *id,
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#define MSR_PERF_STATUS 0x198
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#define MSR_PSTATE_S 0xC0010063
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#define MSR_PSTATE_0 0xC0010064
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uint64_t val;
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int err;
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uint64_t reg, CpuVid;
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if(id->vendor == VENDOR_INTEL) {
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cpu_rdmsr_range(handle, MSR_PERF_STATUS, 47, 32, &val);
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double ret = (double) val / (1 << 13);
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return (ret > 0) ? ret : CPU_INVALID_VALUE;
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/* Refer links above
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Table 35-18. MSRs Supported by Intel® Processors based on Intel® microarchitecture code name Sandy Bridge (Contd.)
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MSR_PERF_STATUS[47:32] is Core Voltage
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P-state core voltage can be computed by MSR_PERF_STATUS[37:32] * (float) 1/(2^13). */
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err = cpu_rdmsr_range(handle, MSR_PERF_STATUS, 47, 32, ®);
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if (!err) return (double) reg / (1 << 13);
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}
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else if(id->vendor == VENDOR_AMD) {
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/* http://support.amd.com/TechDocs/42301_15h_Mod_00h-0Fh_BKDG.pdf
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MSRC001_0063[2:0] = CurPstate
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MSRC001_00[6B:64][15:9] = CpuVid */
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uint64_t CpuVid;
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cpu_rdmsr_range(handle, MSR_PSTATE_S, 2, 0, &val);
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if(val <= 7) { // Support 8 P-states
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cpu_rdmsr_range(handle, MSR_PSTATE_0 + val, 15, 9, &CpuVid);
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return 1.550 - 0.0125 * CpuVid; // 2.4.1.6.3 - Serial VID (SVI) Encodings
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}
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/* Refer links above
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MSRC001_00[6B:64][15:9] is CpuVid
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MSRC001_0063[2:0] is P-state Status
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2.4.1.6.3 Serial VID (SVI) Encodings: voltage = 1.550V - 0.0125V * SviVid[6:0] */
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err = cpu_rdmsr_range(handle, MSR_PSTATE_S, 2, 0, ®);
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err += cpu_rdmsr_range(handle, MSR_PSTATE_0 + reg, 15, 9, &CpuVid);
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if (!err && reg <= 7) return 1.550 - 0.0125 * CpuVid;
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}
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return CPU_INVALID_VALUE;
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#undef MSR_PERF_STATUS
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#undef MSR_PSTATE_S
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#undef MSR_PSTATE_0
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}
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static double get_info_bclk(struct msr_driver_t* handle, struct cpu_id_t *id,
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struct internal_id_info_t *internal)
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{
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static int max_clock = 0, multiplier = 0;
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#define MSR_PLATFORM_INFO 0xce
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int err;
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static int clock = 0;
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uint64_t reg;
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if(!max_clock)
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max_clock = cpu_clock_measure(100, 1); // Return the non-Turbo clock
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if(!multiplier)
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multiplier = cpu_msrinfo(handle, INFO_MAX_MULTIPLIER) / 100;
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if(max_clock > 0 && multiplier > 0)
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return (double) max_clock / multiplier;
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if(clock == 0)
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clock = cpu_clock_measure(50, 1);
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if(id->vendor == VENDOR_INTEL) {
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/* Refer links above
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Table 35-12. MSRs in Next Generation Intel Atom Processors Based on the Goldmont Microarchitecture
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Table 35-13. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem
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Table 35-18. MSRs Supported by Intel® Processors based on Intel® microarchitecture code name Sandy Bridge (Contd.)
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Table 35-23. Additional MSRs Supported by 3rd Generation Intel® Core™ Processors (based on Intel® microarchitecture code name Ivy Bridge)
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Table 35-24. MSRs Supported by Intel® Xeon® Processors E5 v2 Product Family (based on Ivy Bridge-E microarchitecture)
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Table 35-27. Additional MSRs Supported by Processors based on the Haswell or Haswell-E microarchitectures
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Table 35-40. Selected MSRs Supported by Next Generation Intel® Xeon Phi™ Processors with DisplayFamily_DisplayModel Signature 06_57H
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MSR_PLATFORM_INFO[15:8] is Maximum Non-Turbo Ratio */
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err = cpu_rdmsr_range(handle, MSR_PLATFORM_INFO, 15, 8, ®);
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if (!err) return (double) clock / reg;
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}
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return CPU_INVALID_VALUE;
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#undef MSR_PLATFORM_INFO
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}
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#ifndef MSRINFO_DEFINED
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#define IA32_PACKAGE_THERM_STATUS 0x1b1
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#define MSR_TURBO_RATIO_LIMIT 429
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int cpu_rdmsr_range(struct msr_driver_t* handle, uint32_t msr_index, uint8_t highbit,
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uint8_t lowbit, uint64_t* result)
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{
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int err;
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const uint8_t bits = highbit - lowbit + 1;
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if(highbit > 63 || lowbit > highbit)
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return set_error(ERR_INVRANGE);
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if(cpu_rdmsr(handle, msr_index, result))
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return set_error(ERR_HANDLE_R);
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err = cpu_rdmsr(handle, msr_index, result);
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if(bits < 64) {
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if(!err && bits < 64) {
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/* Show only part of register */
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*result >>= lowbit;
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*result &= (1ULL << bits) - 1;
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}
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return 0;
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return err;
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}
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int cpu_msrinfo(struct msr_driver_t* handle, cpu_msrinfo_request_t which)
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@ -647,17 +698,17 @@ int cpu_msrinfo(struct msr_driver_t* handle, cpu_msrinfo_request_t which)
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case INFO_APERF:
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return perfmsr_measure(handle, 0xe8);
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case INFO_CUR_MULTIPLIER:
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return (int) get_info_cur_multiplier(handle, &id, &internal) * 100;
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return get_info_cur_multiplier(handle, &id, &internal) * 100;
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case INFO_MAX_MULTIPLIER:
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return (int) get_info_max_multiplier(handle, &id, &internal) * 100;
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return get_info_max_multiplier(handle, &id, &internal) * 100;
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case INFO_TEMPERATURE:
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return get_info_temperature(handle, &id, &internal);
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case INFO_THROTTLING:
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return CPU_INVALID_VALUE;
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case INFO_VOLTAGE:
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return (int) get_info_voltage(handle, &id, &internal) * 100;
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return get_info_voltage(handle, &id, &internal) * 100;
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case INFO_BCLK:
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return (int) get_info_bclk(handle, &id, &internal) * 100;
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return get_info_bclk(handle, &id, &internal) * 100;
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default:
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return CPU_INVALID_VALUE;
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}
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