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DB: add Intel Arrow Lake

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The Tumultuous Unicorn Of Darkness 2024-11-30 12:22:10 +01:00
parent d5a82d6f64
commit 15cbda31bd
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2
libcpuid/rdmsr.c
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@ -739,6 +739,8 @@ static int msr_platform_info_supported(struct msr_info_t *info)
{ 6, 207 }, { 6, 207 },
/* ==> Meteor Lake */ /* ==> Meteor Lake */
{ 6, 170 }, { 6, 170 },
/* ==> Arrow Lake */
{ 6, 198 },
/* Table 2-50. MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature DisplayFamily_DisplayModel Value of 06_55H */ /* Table 2-50. MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature DisplayFamily_DisplayModel Value of 06_55H */
{ 0x6, 0x55 }, { 0x6, 0x55 },
/* Table 2-56. Selected MSRs Supported by Intel® Xeon PhiTM Processors with a CPUID Signature DisplayFamily_DisplayModel Value of 06_57H or 06_85H */ /* Table 2-56. Selected MSRs Supported by Intel® Xeon PhiTM Processors with a CPUID Signature DisplayFamily_DisplayModel Value of 06_57H or 06_85H */

8
libcpuid/recog_intel.c
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@ -73,6 +73,7 @@ enum _intel_model_t {
_x4xx, /* Xeon Bronze/Silver/Gold/Platinum/Max x4xx */ _x4xx, /* Xeon Bronze/Silver/Gold/Platinum/Max x4xx */
_x5xx, /* Xeon Bronze/Silver/Gold/Platinum x5xx */ _x5xx, /* Xeon Bronze/Silver/Gold/Platinum x5xx */
_1xx, /* Core Ultra [3579] 1xx */ _1xx, /* Core Ultra [3579] 1xx */
_2xx, /* Core Ultra [3579] 2xx */
}; };
typedef enum _intel_model_t intel_model_t; typedef enum _intel_model_t intel_model_t;
@ -551,6 +552,12 @@ const struct match_entry_t cpudb_intel[] = {
{ 6, 10, -1, -1, 170, -1, -1, -1, NC, CORE_|_ULTRA_|_5|_H, _1xx, "Meteor Lake-H (Core Ultra 5)" }, { 6, 10, -1, -1, 170, -1, -1, -1, NC, CORE_|_ULTRA_|_5|_H, _1xx, "Meteor Lake-H (Core Ultra 5)" },
{ 6, 10, -1, -1, 170, -1, -1, -1, NC, CORE_|_ULTRA_|_7|_U, _1xx, "Meteor Lake-U (Core Ultra 7)" }, { 6, 10, -1, -1, 170, -1, -1, -1, NC, CORE_|_ULTRA_|_7|_U, _1xx, "Meteor Lake-U (Core Ultra 7)" },
{ 6, 10, -1, -1, 170, -1, -1, -1, NC, CORE_|_ULTRA_|_5|_U, _1xx, "Meteor Lake-U (Core Ultra 5)" }, { 6, 10, -1, -1, 170, -1, -1, -1, NC, CORE_|_ULTRA_|_5|_U, _1xx, "Meteor Lake-U (Core Ultra 5)" },
/* Arrow Lake CPUs (2024, Core Ultra Series 2 processors, TSMC N3B) => https://en.wikichip.org/wiki/intel/microarchitectures/arrow_lake */
{ 6, 6, -1, -1, 198, -1, -1, -1, NC, CORE_|_ULTRA_|_9|_S, _2xx, "Arrow Lake-S (Core Ultra 9)" },
{ 6, 6, -1, -1, 198, -1, -1, -1, NC, CORE_|_ULTRA_|_7|_S, _2xx, "Arrow Lake-S (Core Ultra 7)" },
{ 6, 6, -1, -1, 198, -1, -1, -1, NC, CORE_|_ULTRA_|_5|_S, _2xx, "Arrow Lake-S (Core Ultra 5)" },
{ 6, 6, -1, -1, 198, -1, -1, -1, NC, CORE_|_ULTRA_|_3|_S, _2xx, "Arrow Lake-S (Core Ultra 3)" },
/* F M S EF EM #cores L2$ L3$ BC ModelBits ModelCode Name */ /* F M S EF EM #cores L2$ L3$ BC ModelBits ModelCode Name */
@ -947,6 +954,7 @@ static intel_model_t get_model_code(struct cpu_id_t* data)
i += 16; i += 16;
if (i + 3 >= l) return UNKNOWN; if (i + 3 >= l) return UNKNOWN;
if (bs[i] == '1') return _1xx; if (bs[i] == '1') return _1xx;
if (bs[i] == '2') return _2xx;
return UNKNOWN; return UNKNOWN;
} }
else if ((i = match_pattern(bs, "Xeon(R) [WBSGP]")) != 0) { else if ((i = match_pattern(bs, "Xeon(R) [WBSGP]")) != 0) {

1247
tests/intel/x86-64/lion-cove/arrow-lake-s-core-ultra-5.test Normal file
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