mirror of
https://github.com/anrieff/libcpuid
synced 2024-12-16 16:35:45 +00:00
DB: add Intel Sapphire Rapids-WS
Related to InstLatx64/InstLatx64@954a632d8a
This commit is contained in:
parent
b4aa93f204
commit
2317f40b36
3 changed files with 3134 additions and 1 deletions
|
@ -128,6 +128,7 @@ enum _intel_bits_t {
|
||||||
_X = LBIT( 18 ),
|
_X = LBIT( 18 ),
|
||||||
_P = LBIT( 19 ),
|
_P = LBIT( 19 ),
|
||||||
_N = LBIT( 20 ),
|
_N = LBIT( 20 ),
|
||||||
|
_W_ = LBIT( 21 ),
|
||||||
};
|
};
|
||||||
typedef enum _intel_bits_t intel_bits_t;
|
typedef enum _intel_bits_t intel_bits_t;
|
||||||
|
|
||||||
|
|
|
@ -459,7 +459,7 @@ const struct match_entry_t cpudb_intel[] = {
|
||||||
{ 6, 14, -1, -1, 190, 4, -1, -1, NC, _N , 0, "Alder Lake-N" },
|
{ 6, 14, -1, -1, 190, 4, -1, -1, NC, _N , 0, "Alder Lake-N" },
|
||||||
{ 6, 14, -1, -1, 190, 2, -1, -1, NC, _N , 0, "Alder Lake-N" },
|
{ 6, 14, -1, -1, 190, 2, -1, -1, NC, _N , 0, "Alder Lake-N" },
|
||||||
|
|
||||||
/* Raptor Lake CPUs (2022, 13th gen, 7nm) => https://en.wikichip.org/wiki/intel/microarchitectures/raptor_lake */
|
/* Raptor Lake CPUs (2022, 13th Core i gen, Intel 7) => https://en.wikichip.org/wiki/intel/microarchitectures/raptor_lake */
|
||||||
{ 6, 7, -1, -1, 183, -1, -1, -1, NC, CORE_|_I_|_9 ,_13xxx, "Raptor Lake-S (Core i9)" },
|
{ 6, 7, -1, -1, 183, -1, -1, -1, NC, CORE_|_I_|_9 ,_13xxx, "Raptor Lake-S (Core i9)" },
|
||||||
{ 6, 7, -1, -1, 183, -1, -1, -1, NC, CORE_|_I_|_7 ,_13xxx, "Raptor Lake-S (Core i7)" },
|
{ 6, 7, -1, -1, 183, -1, -1, -1, NC, CORE_|_I_|_7 ,_13xxx, "Raptor Lake-S (Core i7)" },
|
||||||
{ 6, 7, -1, -1, 183, -1, -1, -1, NC, CORE_|_I_|_5 ,_13xxx, "Raptor Lake-S (Core i5)" },
|
{ 6, 7, -1, -1, 183, -1, -1, -1, NC, CORE_|_I_|_5 ,_13xxx, "Raptor Lake-S (Core i5)" },
|
||||||
|
@ -471,6 +471,12 @@ const struct match_entry_t cpudb_intel[] = {
|
||||||
{ 6, 10, 3, -1, 186, -1, -1, -1, NC, CORE_|_I_|_7 ,_13xxx, "Raptor Lake-U (Core i7)" },
|
{ 6, 10, 3, -1, 186, -1, -1, -1, NC, CORE_|_I_|_7 ,_13xxx, "Raptor Lake-U (Core i7)" },
|
||||||
{ 6, 10, 3, -1, 186, -1, -1, -1, NC, CORE_|_I_|_5 ,_13xxx, "Raptor Lake-U (Core i5)" },
|
{ 6, 10, 3, -1, 186, -1, -1, -1, NC, CORE_|_I_|_5 ,_13xxx, "Raptor Lake-U (Core i5)" },
|
||||||
{ 6, 10, 3, -1, 186, -1, -1, -1, NC, CORE_|_I_|_3 ,_13xxx, "Raptor Lake-U (Core i3)" },
|
{ 6, 10, 3, -1, 186, -1, -1, -1, NC, CORE_|_I_|_3 ,_13xxx, "Raptor Lake-U (Core i3)" },
|
||||||
|
|
||||||
|
/* Sapphire Rapids CPUs (2023, 4th Xeon Scalable gen, Intel 7) => https://en.wikichip.org/wiki/intel/microarchitectures/sapphire_rapids */
|
||||||
|
{ 6, 15, -1, -1, 143, -1, -1, -1, NC, XEON_|_W_|_9 , 0, "Sapphire Rapids-WS (Xeon w9)" },
|
||||||
|
{ 6, 15, -1, -1, 143, -1, -1, -1, NC, XEON_|_W_|_7 , 0, "Sapphire Rapids-WS (Xeon w7)" },
|
||||||
|
{ 6, 15, -1, -1, 143, -1, -1, -1, NC, XEON_|_W_|_5 , 0, "Sapphire Rapids-WS (Xeon w5)" },
|
||||||
|
{ 6, 15, -1, -1, 143, -1, -1, -1, NC, XEON_|_W_|_3 , 0, "Sapphire Rapids-WS (Xeon w3)" },
|
||||||
/* F M S EF EM C L2 L3 Brand */
|
/* F M S EF EM C L2 L3 Brand */
|
||||||
|
|
||||||
|
|
||||||
|
@ -752,6 +758,19 @@ static intel_code_and_bits_t get_brand_code_and_bits(struct cpu_id_t* data)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
else if ((i = match_pattern(bs, "Xeon(R) w[3579]")) != 0) {
|
||||||
|
bits |= XEON_;
|
||||||
|
i--;
|
||||||
|
switch (bs[i + 8]) {
|
||||||
|
case 'w': bits |= _W_; break;
|
||||||
|
}
|
||||||
|
switch (bs[i + 9]) {
|
||||||
|
case '3': bits |= _3; break;
|
||||||
|
case '5': bits |= _5; break;
|
||||||
|
case '7': bits |= _7; break;
|
||||||
|
case '9': bits |= _9; break;
|
||||||
|
}
|
||||||
|
}
|
||||||
for (i = 0; i < COUNT_OF(matchtable); i++)
|
for (i = 0; i < COUNT_OF(matchtable); i++)
|
||||||
if (match_pattern(bs, matchtable[i].search)) {
|
if (match_pattern(bs, matchtable[i].search)) {
|
||||||
code = matchtable[i].c;
|
code = matchtable[i].c;
|
||||||
|
|
3113
tests/intel/sapphire_rapids/sapphire-rapids-ws-xeon-w7.test
Normal file
3113
tests/intel/sapphire_rapids/sapphire-rapids-ws-xeon-w7.test
Normal file
File diff suppressed because it is too large
Load diff
Loading…
Reference in a new issue