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Add L1 Instruction Cache information

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Some CPUs does not have the same associativity for L1D and L1I, as reported in X0rg/CPU-X#119
It adds l1_instruction_assoc and l1_instruction_cacheline in cpu_id_t
To avoid confusing, also adds l1_data_assoc and l1_data_cacheline
l1_assoc and l1_cacheline are leave untouched for backward compatibility
This commit is contained in:
Xorg 2020-05-10 11:47:43 +02:00
commit 25d0614811
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GPG key ID: 1E55EE2EFF18BC1A
5 changed files with 54 additions and 15 deletions
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20
cpuid_tool/cpuid_tool.c
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@ -75,10 +75,12 @@ typedef enum {
NEED_L3_SIZE,
NEED_L4_SIZE,
NEED_L1D_ASSOC,
NEED_L1I_ASSOC,
NEED_L2_ASSOC,
NEED_L3_ASSOC,
NEED_L4_ASSOC,
NEED_L1D_CACHELINE,
NEED_L1I_CACHELINE,
NEED_L2_CACHELINE,
NEED_L3_CACHELINE,
NEED_L4_CACHELINE,
@ -133,10 +135,12 @@ matchtable[] = {
{ NEED_L3_SIZE , "--l3-cache" , 1},
{ NEED_L4_SIZE , "--l4-cache" , 1},
{ NEED_L1D_ASSOC , "--l1d-assoc" , 1},
{ NEED_L1I_ASSOC , "--l1i-assoc" , 1},
{ NEED_L2_ASSOC , "--l2-assoc" , 1},
{ NEED_L3_ASSOC , "--l3-assoc" , 1},
{ NEED_L4_ASSOC , "--l4-assoc" , 1},
{ NEED_L1D_CACHELINE, "--l1d-cacheline", 1},
{ NEED_L1I_CACHELINE, "--l1i-cacheline", 1},
{ NEED_L2_CACHELINE , "--l2-cacheline" , 1},
{ NEED_L3_CACHELINE , "--l3-cacheline" , 1},
{ NEED_L4_CACHELINE , "--l4-cacheline" , 1},
@ -391,7 +395,10 @@ static void print_info(output_data_switch query, struct cpu_raw_data_t* raw,
fprintf(fout, "%d\n", data->l4_cache);
break;
case NEED_L1D_ASSOC:
fprintf(fout, "%d\n", data->l1_assoc);
fprintf(fout, "%d\n", data->l1_data_assoc);
break;
case NEED_L1I_ASSOC:
fprintf(fout, "%d\n", data->l1_instruction_assoc);
break;
case NEED_L2_ASSOC:
fprintf(fout, "%d\n", data->l2_assoc);
@ -403,7 +410,10 @@ static void print_info(output_data_switch query, struct cpu_raw_data_t* raw,
fprintf(fout, "%d\n", data->l4_assoc);
break;
case NEED_L1D_CACHELINE:
fprintf(fout, "%d\n", data->l1_cacheline);
fprintf(fout, "%d\n", data->l1_data_cacheline);
break;
case NEED_L1I_CACHELINE:
fprintf(fout, "%d\n", data->l1_instruction_cacheline);
break;
case NEED_L2_CACHELINE:
fprintf(fout, "%d\n", data->l2_cacheline);
@ -654,11 +664,13 @@ int main(int argc, char** argv)
fprintf(fout, " L2 cache : %d KB\n", data.l2_cache);
fprintf(fout, " L3 cache : %d KB\n", data.l3_cache);
fprintf(fout, " L4 cache : %d KB\n", data.l4_cache);
fprintf(fout, " L1D assoc. : %d-way\n", data.l1_assoc);
fprintf(fout, " L1D assoc. : %d-way\n", data.l1_data_assoc);
fprintf(fout, " L1I assoc. : %d-way\n", data.l1_instruction_assoc);
fprintf(fout, " L2 assoc. : %d-way\n", data.l2_assoc);
fprintf(fout, " L3 assoc. : %d-way\n", data.l3_assoc);
fprintf(fout, " L4 assoc. : %d-way\n", data.l4_assoc);
fprintf(fout, " L1D line sz: %d bytes\n", data.l1_cacheline);
fprintf(fout, " L1D line sz: %d bytes\n", data.l1_data_cacheline);
fprintf(fout, " L1I line sz: %d bytes\n", data.l1_instruction_cacheline);
fprintf(fout, " L2 line sz : %d bytes\n", data.l2_cacheline);
fprintf(fout, " L3 line sz : %d bytes\n", data.l3_cacheline);
fprintf(fout, " L4 line sz : %d bytes\n", data.l4_cacheline);