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Support for 2MB L2 Cache Yorkfield added. Also, made the logic a bit more foolproof by adding explicit core count for those Yorkfields.

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git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@95 3b4be424-7ac5-41d7-8526-f4ddcb85d872
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Veselin Georgiev 2011-01-16 01:11:00 +00:00
commit 2f949b18d9
2 changed files with 96 additions and 2 deletions
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libcpuid/recog_intel.c
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@ -243,8 +243,9 @@ const struct match_entry_t cpudb_intel[] = {
{ 6, 7, -1, -1, 23, 1, -1, -1, MOBILE_CORE_DUO , 0, "Penryn (Core 2 Duo)" },
{ 6, 7, -1, -1, 23, 2, 3072, -1, PENRYN , 0, "Penryn (Core 2 Duo) 3M" },
{ 6, 7, -1, -1, 23, 2, 6144, -1, PENRYN , 0, "Penryn (Core 2 Duo) 6M" },
{ 6, 7, -1, -1, 23, 1, 3072, -1, QUAD_CORE , 0, "Yorkfield (Core 2 Quad) 3M"},
{ 6, 7, -1, -1, 23, 1, 6144, -1, QUAD_CORE , 0, "Yorkfield (Core 2 Quad) 6M"},
{ 6, 7, -1, -1, 23, 4, 2048, -1, QUAD_CORE , 0, "Yorkfield (Core 2 Quad) 2M"},
{ 6, 7, -1, -1, 23, 4, 3072, -1, QUAD_CORE , 0, "Yorkfield (Core 2 Quad) 3M"},
{ 6, 7, -1, -1, 23, 4, 6144, -1, QUAD_CORE , 0, "Yorkfield (Core 2 Quad) 6M"},
{ 6, 5, -1, -1, 37, 2, -1, -1, NO_CODE , 0, "Unknown Core i3/i5 CPU" },
{ 6, 5, -1, -1, 37, 2, -1, 4096, CORE_I7 , 0, "Arrandale (Core i7)" },