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Added SSE unit size detection, based on the AMD extended leaf 1a, bit 0. Added a field in cpu_id_t to specify SSE unit size. Also added a hints array, similar to the flags array, which will hold various detection-specific hints. The only currently present hint is about the way the SSE unit size is inferred - whether it is based on the old CPU family/model guesswork (which fails for the AMD Brazos-based cores). Also, added the features XOP, FMA4, TBM and F16C. Changed the library version due to breaking binary compatibility.

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git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@96 3b4be424-7ac5-41d7-8526-f4ddcb85d872
This commit is contained in:
Veselin Georgiev 2011-10-11 16:38:41 +00:00
parent 2f949b18d9
commit 3623c5639d
7 changed files with 78 additions and 22 deletions
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9
cpuid_tool/cpuid_tool.c
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@ -85,6 +85,7 @@ typedef enum {
NEED_CLOCK_RDTSC,
NEED_CLOCK_IC,
NEED_RDMSR,
NEED_SSE_UNIT_SIZE,
} output_data_switch;
int need_input = 0,
@ -136,6 +137,7 @@ matchtable[] = {
{ NEED_CLOCK_RDTSC , "--clock-rdtsc" , 1},
{ NEED_CLOCK_IC , "--clock-ic" , 1},
{ NEED_RDMSR , "--rdmsr" , 0},
{ NEED_SSE_UNIT_SIZE, "--sse_size" , 1},
};
const int sz_match = (sizeof(matchtable) / sizeof(matchtable[0]));
@ -422,6 +424,12 @@ static void print_info(output_data_switch query, struct cpu_raw_data_t* raw,
}
break;
}
case NEED_SSE_UNIT_SIZE:
{
fprintf(fout, "%d (%s)\n", data->sse_size,
data->detection_hints[CPU_HINT_SSE_SIZE_AUTH] ? "authoritative" : "non-authoritative");
break;
}
default:
fprintf(fout, "How did you get here?!?\n");
break;
@ -580,6 +588,7 @@ int main(int argc, char** argv)
fprintf(fout, " L1D line sz: %d bytes\n", data.l1_cacheline);
fprintf(fout, " L2 line sz : %d bytes\n", data.l2_cacheline);
fprintf(fout, " L3 line sz : %d bytes\n", data.l3_cacheline);
fprintf(fout, " SSE units : %d bits (%s)\n", data.sse_size, data.detection_hints[CPU_HINT_SSE_SIZE_AUTH] ? "authoritative" : "non-authoritative");
fprintf(fout, " code name : `%s'\n", data.cpu_codename);
fprintf(fout, " features :");
/*