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DB: add Intel Alder Lake-HX

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Refer to https://en.wikipedia.org/wiki/Alder_Lake#Alder_Lake-HX
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The Tumultuous Unicorn Of Darkness 2022-12-31 12:04:12 +01:00
parent d984d4389f
commit 44bde9877a
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GPG key ID: 1E55EE2EFF18BC1A
3 changed files with 1738 additions and 10 deletions
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3
libcpuid/libcpuid_internal.h
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@ -123,6 +123,9 @@ enum _intel_bits_t {
_I_ = LBIT( 13 ),
XEON_ = LBIT( 14 ),
ATOM_ = LBIT( 15 ),
_H = LBIT( 16 ),
_K = LBIT( 17 ),
_X = LBIT( 18 ),
};
typedef enum _intel_bits_t intel_bits_t;

31
libcpuid/recog_intel.c
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@ -438,16 +438,19 @@ const struct match_entry_t cpudb_intel[] = {
{ 6, 12, -1, -1, 140, 2, -1, -1, NC, CELERON_ , 0, "Tiger Lake (Celeron)" },
/* Alder Lake CPUs (2021, 12th gen, 10nm) => https://en.wikichip.org/wiki/intel/microarchitectures/alder_lake */
{ 6, 7, -1, -1, 151, -1, -1, -1, NC, CORE_|_I_|_9 ,_12xxx, "Alder Lake-S (Core i9)" },
{ 6, 7, -1, -1, 151, -1, -1, -1, NC, CORE_|_I_|_7 ,_12xxx, "Alder Lake-S (Core i7)" },
{ 6, 7, -1, -1, 151, -1, -1, -1, NC, CORE_|_I_|_5 ,_12xxx, "Alder Lake-S (Core i5)" },
{ 6, 7, -1, -1, 151, -1, -1, -1, NC, CORE_|_I_|_3 ,_12xxx, "Alder Lake-S (Core i3)" },
{ 6, 7, -1, -1, 151, -1, -1, -1, NC, PENTIUM_ , 0, "Alder Lake-S (Pentium)" },
{ 6, 7, -1, -1, 151, -1, -1, -1, NC, CELERON_ , 0, "Alder Lake-S (Celeron)" },
{ 6, 10, -1, -1, 154, -1, -1, -1, NC, CORE_|_I_|_9 ,_12xxx, "Alder Lake-P (Core i9)" },
{ 6, 10, -1, -1, 154, -1, -1, -1, NC, CORE_|_I_|_7 ,_12xxx, "Alder Lake-P (Core i7)" },
{ 6, 10, -1, -1, 154, -1, -1, -1, NC, CORE_|_I_|_5 ,_12xxx, "Alder Lake-P (Core i5)" },
{ 6, 10, -1, -1, 154, -1, -1, -1, NC, CORE_|_I_|_3 ,_12xxx, "Alder Lake-P (Core i3)" },
{ 6, 7, -1, -1, 151, -1, -1, -1, NC, CORE_|_I_|_9 , _12xxx, "Alder Lake-S (Core i9)" },
{ 6, 7, -1, -1, 151, -1, -1, -1, NC, CORE_|_I_|_7 , _12xxx, "Alder Lake-S (Core i7)" },
{ 6, 7, -1, -1, 151, -1, -1, -1, NC, CORE_|_I_|_5 , _12xxx, "Alder Lake-S (Core i5)" },
{ 6, 7, -1, -1, 151, -1, -1, -1, NC, CORE_|_I_|_3 , _12xxx, "Alder Lake-S (Core i3)" },
{ 6, 7, -1, -1, 151, -1, -1, -1, NC, PENTIUM_ , 0, "Alder Lake-S (Pentium)" },
{ 6, 7, -1, -1, 151, -1, -1, -1, NC, CELERON_ , 0, "Alder Lake-S (Celeron)" },
{ 6, 7, -1, -1, 151, -1, -1, -1, NC, CORE_|_I_|_9|_H|_X, _12xxx, "Alder Lake-HX (Core i9)" },
{ 6, 7, -1, -1, 151, -1, -1, -1, NC, CORE_|_I_|_7|_H|_X, _12xxx, "Alder Lake-HX (Core i7)" },
{ 6, 7, -1, -1, 151, -1, -1, -1, NC, CORE_|_I_|_5|_H|_X, _12xxx, "Alder Lake-HX (Core i5)" },
{ 6, 10, -1, -1, 154, -1, -1, -1, NC, CORE_|_I_|_9 , _12xxx, "Alder Lake-P (Core i9)" },
{ 6, 10, -1, -1, 154, -1, -1, -1, NC, CORE_|_I_|_7 , _12xxx, "Alder Lake-P (Core i7)" },
{ 6, 10, -1, -1, 154, -1, -1, -1, NC, CORE_|_I_|_5 , _12xxx, "Alder Lake-P (Core i5)" },
{ 6, 10, -1, -1, 154, -1, -1, -1, NC, CORE_|_I_|_3 , _12xxx, "Alder Lake-P (Core i3)" },
/* Raptor Lake CPUs (2022, 13th gen, 7nm) => https://en.wikichip.org/wiki/intel/microarchitectures/raptor_lake */
{ 6, 7, -1, -1, 183, -1, -1, -1, NC, CORE_|_I_|_9 ,_13xxx, "Raptor Lake-S (Core i9)" },
@ -688,6 +691,7 @@ static intel_code_and_bits_t get_brand_code_and_bits(struct cpu_id_t* data)
int i = 0;
const char* bs = data->brand_str;
const char* s;
const size_t n = strlen(bs);
const struct { intel_code_t c; const char *search; } matchtable[] = {
{ PENTIUM_M, "Pentium(R) M" },
{ CORE_SOLO, "Pentium(R) Dual CPU" },
@ -728,6 +732,13 @@ static intel_code_and_bits_t get_brand_code_and_bits(struct cpu_id_t* data)
case '7': bits |= _7; break;
case '9': bits |= _9; break;
}
for(i = i + 11; i < n; i++) {
switch (bs[i]) {
case 'H': bits |= _H; break;
case 'K': bits |= _K; break;
case 'X': bits |= _X; break;
}
}
}
for (i = 0; i < COUNT_OF(matchtable); i++)
if (match_pattern(bs, matchtable[i].search)) {

1714
tests/intel/core_12th_gen/alder-lake-hx-i7.test Normal file
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