mirror/libcpuid
1
0
Fork 0
mirror of https://github.com/anrieff/libcpuid synced 2025-07-02 14:04:15 +00:00
Code Issues Releases Wiki Activity

DB: add Intel Arrow Lake-H

Browse source 
https://valid.x86.fr/fkv9rb
This commit is contained in:
The Tumultuous Unicorn Of Darkness 2025-04-22 19:15:44 +02:00
parent 022e534401
commit 49ae659ff7
No known key found for this signature in database
GPG key ID: 1E55EE2EFF18BC1A
1 changed files with 3 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

3
libcpuid/recog_intel.c
View file

@ -582,6 +582,9 @@ const struct match_entry_t cpudb_intel[] = {
{ 6, 6, -1, -1, 198, -1, -1, -1, NC, CORE_|_ULTRA_|_5, _2xx, "Arrow Lake-S (Core Ultra 5)" },
{ 6, 6, -1, -1, 181, -1, -1, -1, NC, CORE_|_ULTRA_|_7|_U, _2xx, "Arrow Lake-U (Core Ultra 7)" }, /* Core Ultra 7 255U + Core Ultra 7 265U */
{ 6, 6, -1, -1, 181, -1, -1, -1, NC, CORE_|_ULTRA_|_5|_U, _2xx, "Arrow Lake-U (Core Ultra 5)" }, /* Core Ultra 5 225U + Core Ultra 7 235U */
{ 6, 6, -1, -1, 197, -1, -1, -1, NC, CORE_|_ULTRA_|_9|_H, _2xx, "Arrow Lake-H (Core Ultra 9)" }, /* Core Ultra 9 285H */
{ 6, 6, -1, -1, 197, -1, -1, -1, NC, CORE_|_ULTRA_|_7|_H, _2xx, "Arrow Lake-H (Core Ultra 7)" }, /* Core Ultra 7 255H + Core Ultra 7 265H */
{ 6, 6, -1, -1, 197, -1, -1, -1, NC, CORE_|_ULTRA_|_5|_H, _2xx, "Arrow Lake-H (Core Ultra 5)" }, /* Core Ultra 5 225H + Core Ultra 7 235H */
/* Lunar Lake CPUs (2024, Core Ultra Series 2 processors, TSMC N3B) => https://en.wikichip.org/wiki/intel/microarchitectures/lunar_lake */
{ 6, 13, -1, -1, 189, -1, -1, -1, NC, CORE_|_ULTRA_|_9|_V, _1xx, "Lunar Lake-V (Core Ultra 9)" },
{ 6, 13, -1, -1, 189, -1, -1, -1, NC, CORE_|_ULTRA_|_7|_V, _1xx, "Lunar Lake-V (Core Ultra 7)" },