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https://github.com/anrieff/libcpuid
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Fixed issue #52: Wrong CPU multipliers on AMD APU
Properly use formulas from AMD BKDG, it should fix CPU multipliers report from 10h family to 16h family. Some tests are available in #52.
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Xorg
parent
3f38efb6c9
commit
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1 changed files with 101 additions and 20 deletions
121
libcpuid/rdmsr.c
121
libcpuid/rdmsr.c
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@ -511,10 +511,21 @@ int cpu_msrinfo(struct msr_driver_t* driver, cpu_msrinfo_request_t which)
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AMD BIOS and Kernel Developer’s Guide (BKDG)
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* AMD Family 10h Processors
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http://support.amd.com/TechDocs/31116.pdf
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* AMD Family 15h Models 00h-0Fh Processors
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* AMD Family 11h Processors
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http://support.amd.com/TechDocs/41256.pdf
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* AMD Family 12h Processors
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http://support.amd.com/TechDocs/41131.pdf
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* AMD Family 14h Processors
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http://support.amd.com/TechDocs/43170_14h_Mod_00h-0Fh_BKDG.pdf
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* AMD Family 15h Processors
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http://support.amd.com/TechDocs/42301_15h_Mod_00h-0Fh_BKDG.pdf
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* AMD Family 15h Models 30h-3Fh
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http://support.amd.com/TechDocs/42300_15h_Mod_10h-1Fh_BKDG.pdf
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http://support.amd.com/TechDocs/49125_15h_Models_30h-3Fh_BKDG.pdf
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http://support.amd.com/TechDocs/50742_15h_Models_60h-6Fh_BKDG.pdf
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http://support.amd.com/TechDocs/49125_15h_Models_30h-3Fh_BKDG.pdf
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* AMD Family 16h Processors
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http://support.amd.com/TechDocs/48751_16h_bkdg.pdf
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http://support.amd.com/TechDocs/52740_16h_Models_30h-3Fh_BKDG.pdf
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- Intel MSRs:
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Intel® 64 and IA-32 Architectures Software Developer’s Manual
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@ -561,27 +572,97 @@ static int perfmsr_measure(struct msr_driver_t* handle, int msr)
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return (int) ((y - x) / (b - a));
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}
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static int get_amd_multipliers(struct msr_driver_t* handle, struct internal_id_info_t *internal,
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static int get_amd_multipliers(struct msr_driver_t* handle, struct cpu_id_t *id,
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struct internal_id_info_t *internal,
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uint32_t pstate, uint64_t *multiplier)
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{
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int err;
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uint64_t CpuFid, CpuDid;
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double factor = 2.0;
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static int clock = 0;
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uint64_t CpuFid, CpuDid, CpuDidLSD;
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double divisor;
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if (pstate < MSR_PSTATE_0 || MSR_PSTATE_7 < pstate)
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return 1;
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/* Refer links above
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Table 299: P-state Definitions
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MSRC001_00[6B:64][8:6] is CpuDid
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MSRC001_00[6B:64][5:0] is CpuFid
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APUs -> 100MHz REFCLK
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CPUs -> 200MHz REFCLK */
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if (FUSION_C <= internal->code.amd && internal->code.amd <= FUSION_A)
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factor = 1.0;
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err = cpu_rdmsr_range(handle, pstate, 5, 0, &CpuFid);
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err += cpu_rdmsr_range(handle, pstate, 8, 6, &CpuDid);
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*multiplier = (uint64_t) (((CpuFid + 0x10) / (1ull << CpuDid)) / factor);
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switch (id->ext_family) {
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case 0x11:
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/* BKDG 11h, page 236
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MSRC001_00[6B:64][8:6] is CpuDid
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MSRC001_00[6B:64][5:0] is CpuFid
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CPU COF is ((100 MHz * (CpuFid + 08h)) / (2^CpuDid)) */
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err = cpu_rdmsr_range(handle, pstate, 8, 6, &CpuDid);
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err += cpu_rdmsr_range(handle, pstate, 5, 0, &CpuFid);
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*multiplier = (uint64_t) ((CpuFid + 0x8) / (1ull << CpuDid));
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break;
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case 0x12:
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/* BKDG 12h, page 469
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MSRC001_00[6B:64][8:4] is CpuFid
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MSRC001_00[6B:64][3:0] is CpuDid
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CPU COF is (100MHz * (CpuFid + 10h) / (divisor specified by CpuDid)) */
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err = cpu_rdmsr_range(handle, pstate, 8, 4, &CpuFid);
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err += cpu_rdmsr_range(handle, pstate, 3, 0, &CpuDid);
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if (CpuDid == 0b0000)
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divisor = 1;
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else if (CpuDid == 0b0001)
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divisor = 1.5;
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else if (CpuDid == 0b0010)
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divisor = 2;
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else if (CpuDid == 0b0011)
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divisor = 3;
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else if (CpuDid == 0b0100)
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divisor = 4;
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else if (CpuDid == 0b0101)
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divisor = 6;
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else if (CpuDid == 0b0110)
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divisor = 8;
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else if (CpuDid == 0b0111)
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divisor = 12;
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else if (CpuDid == 0b1000)
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divisor = 16;
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else
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divisor = 0;
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if (divisor > 0)
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*multiplier = (uint64_t) ((CpuFid + 0x10) / divisor);
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else
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err++;
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break;
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case 0x14:
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/* BKDG 14h, page 430
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MSRC001_00[6B:64][8:4] is CpuDidMSD
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MSRC001_00[6B:64][3:0] is CpuDidLSD
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PLL COF is (100 MHz * (D18F3xD4[MainPllOpFreqId] + 10h))
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Divisor is (CpuDidMSD + (CpuDidLSD * 0.25) + 1)
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CPU COF is (main PLL frequency specified by D18F3xD4[MainPllOpFreqId]) / (core clock divisor specified by CpuDidMSD and CpuDidLSD) */
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err = cpu_rdmsr_range(handle, pstate, 8, 4, &CpuDid);
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err += cpu_rdmsr_range(handle, pstate, 3, 0, &CpuDidLSD);
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if (clock == 0)
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clock = cpu_clock_measure(100, 1) + 5; // Fake round
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*multiplier = (uint64_t) ((clock / 100 + 0x10) / (CpuDid + CpuDidLSD * 0.25 + 1));
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break;
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case 0x10:
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/* BKDG 10h, page 429
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MSRC001_00[6B:64][8:6] is CpuDid
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MSRC001_00[6B:64][5:0] is CpuFid
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CPU COF is (100 MHz * (CpuFid + 10h) / (2^CpuDid)) */
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case 0x15:
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/* BKDG 15h, page 570/580/635/692 (00h-0Fh/10h-1Fh/30h-3Fh/60h-6Fh)
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MSRC001_00[6B:64][8:6] is CpuDid
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MSRC001_00[6B:64][5:0] is CpuFid
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CoreCOF is (100 * (MSRC001_00[6B:64][CpuFid] + 10h) / (2^MSRC001_00[6B:64][CpuDid])) */
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case 0x16:
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/* BKDG 16h, page 549/611 (00h-0Fh/30h-3Fh)
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MSRC001_00[6B:64][8:6] is CpuDid
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MSRC001_00[6B:64][5:0] is CpuFid
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CoreCOF is (100 * (MSRC001_00[6B:64][CpuFid] + 10h) / (2^MSRC001_00[6B:64][CpuDid])) */
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err = cpu_rdmsr_range(handle, pstate, 8, 6, &CpuDid);
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err += cpu_rdmsr_range(handle, pstate, 5, 0, &CpuFid);
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*multiplier = (uint64_t) ((CpuFid + 0x10) / (1ull << CpuDid));
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break;
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default:
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err = 1;
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break;
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}
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return err;
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}
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@ -612,7 +693,7 @@ static double get_info_min_multiplier(struct msr_driver_t* handle, struct cpu_id
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MSRC001_0061[6:4] is PstateMaxVal
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PstateMaxVal is the lowest-performance non-boosted P-state */
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err = cpu_rdmsr_range(handle, MSR_PSTATE_L, 6, 4, ®);
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err += get_amd_multipliers(handle, internal, MSR_PSTATE_0 + (uint32_t) reg, ®);
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err += get_amd_multipliers(handle, id, internal, MSR_PSTATE_0 + (uint32_t) reg, ®);
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if (!err) return (double) reg;
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}
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@ -641,7 +722,7 @@ static double get_info_cur_multiplier(struct msr_driver_t* handle, struct cpu_id
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/* Refer links above
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MSRC001_0063[2:0] is CurPstate */
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err = cpu_rdmsr_range(handle, MSR_PSTATE_S, 2, 0, ®);
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err += get_amd_multipliers(handle, internal, MSR_PSTATE_0 + (uint32_t) reg, ®);
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err += get_amd_multipliers(handle, id, internal, MSR_PSTATE_0 + (uint32_t) reg, ®);
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if (!err) return (double) reg;
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}
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@ -681,7 +762,7 @@ static double get_info_max_multiplier(struct msr_driver_t* handle, struct cpu_id
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/* Refer links above
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MSRC001_0064 is Pb0
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Pb0 is the highest-performance boosted P-state */
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err = get_amd_multipliers(handle, internal, MSR_PSTATE_0, ®);
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err = get_amd_multipliers(handle, id, internal, MSR_PSTATE_0, ®);
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if (!err) return (double) reg;
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}
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@ -771,7 +852,7 @@ static double get_info_bus_clock(struct msr_driver_t* handle, struct cpu_id_t *i
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MSRC001_0061[2:0] is CurPstateLimit
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CurPstateLimit is the highest-performance non-boosted P-state */
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err = cpu_rdmsr_range(handle, MSR_PSTATE_L, 2, 0, ®);
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err += get_amd_multipliers(handle, internal, MSR_PSTATE_0 + (uint32_t) reg, ®);
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err += get_amd_multipliers(handle, id, internal, MSR_PSTATE_0 + (uint32_t) reg, ®);
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if (!err) return (double) clock / reg;
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}
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