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Correctly recognize Sandy Bridge-E Xeons.

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They have L3 cache, and the detection code incorrectly assumed this is a Xeon
Irwindale variant due to an old and no longer valid classification check.
Correctly handle the XEON_IRWIN subcode and add an entry in the matchtable
to fix Sandy Bridge-E Xeon.
This commit is contained in:
Veselin Georgiev 2015-09-13 18:36:23 +03:00
parent f642b79047
commit 4a72a734aa
1 changed files with 3 additions and 1 deletions
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4
libcpuid/recog_intel.c
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@ -316,6 +316,7 @@ const struct match_entry_t cpudb_intel[] = {
{ 6, 10, -1, -1, 42, 1, -1, -1, CELERON , 0, "Sandy Bridge (Celeron)" },
{ 6, 10, -1, -1, 42, 2, -1, -1, CELERON , 0, "Sandy Bridge (Celeron)" },
{ 6, 13, -1, -1, 45, -1, -1, -1, NO_CODE , 0, "Sandy Bridge-E" },
{ 6, 13, -1, -1, 45, -1, -1, -1, XEON , 0, "Sandy Bridge-E (Xeon)" },
/* Ivy Bridge CPUs (22nm): */
{ 6, 10, -1, -1, 58, -1, -1, -1, XEON , 0, "Ivy Bridge (Xeon)" },
@ -685,7 +686,8 @@ static intel_code_t get_brand_code(struct cpu_id_t* data)
code = XEON_GAINESTOWN;
else if (match_pattern(bs, "[ELXW]56##"))
code = XEON_WESTMERE;
else if (data->l3_cache > 0)
else if (data->l3_cache > 0 && data->family == 16)
/* restrict by family, since later Xeons also have L3 ... */
code = XEON_IRWIN;
}
if (code == XEONMP && data->l3_cache > 0)