mirror of
https://github.com/anrieff/libcpuid
synced 2024-12-16 16:35:45 +00:00
Veselin Georgiev
GitHub
commit
57298c650c
1 changed files with 49 additions and 31 deletions
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@ -528,6 +528,7 @@ int msr_serialize_raw_data(struct msr_driver_t* handle, const char* filename)
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http://support.amd.com/TechDocs/42300_15h_Mod_10h-1Fh_BKDG.pdf
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http://support.amd.com/TechDocs/49125_15h_Models_30h-3Fh_BKDG.pdf
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http://support.amd.com/TechDocs/50742_15h_Models_60h-6Fh_BKDG.pdf
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http://support.amd.com/TechDocs/55072_AMD_Family_15h_Models_70h-7Fh_BKDG.pdf
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* AMD Family 16h Processors
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http://support.amd.com/TechDocs/48751_16h_bkdg.pdf
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http://support.amd.com/TechDocs/52740_16h_Models_30h-3Fh_BKDG.pdf
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@ -618,12 +619,12 @@ static int perfmsr_measure(struct msr_driver_t* handle, int msr)
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return (int) ((y - x) / (b - a));
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}
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static int get_amd_multipliers(struct msr_info_t *info, uint32_t pstate, uint64_t *multiplier)
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static int get_amd_multipliers(struct msr_info_t *info, uint32_t pstate, double *multiplier)
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{
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int i, err;
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int divisor = 1;
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int magic_constant = 0x10;
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uint64_t CpuFid, CpuDid, CpuDidLSD;
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/* Constant values needed for 12h family */
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const struct { uint64_t did; double divisor; } divisor_t[] = {
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{ 0x0, 1 },
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{ 0x1, 1.5 },
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@ -635,8 +636,14 @@ static int get_amd_multipliers(struct msr_info_t *info, uint32_t pstate, uint64_
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{ 0x7, 12 },
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{ 0x8, 16 },
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};
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int num_dids = (int) COUNT_OF(divisor_t);
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const int num_dids = (int) COUNT_OF(divisor_t);
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/* Constant values for common families */
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const int magic_constant = (info->id->ext_family == 0x11) ? 0x8 : 0x10;
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const int is_apu = ((FUSION_C <= info->internal->code.amd) && (info->internal->code.amd <= FUSION_A)) || (info->internal->bits & _APU_);
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const double divisor = is_apu ? 1.0 : 2.0;
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/* Check if P-state is valid */
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if (pstate < MSR_PSTATE_0 || MSR_PSTATE_7 < pstate)
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return 1;
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@ -645,14 +652,15 @@ static int get_amd_multipliers(struct msr_info_t *info, uint32_t pstate, uint64_
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/* BKDG 12h, page 469
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MSRC001_00[6B:64][8:4] is CpuFid
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MSRC001_00[6B:64][3:0] is CpuDid
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CPU COF is (100MHz * (CpuFid + 10h) / (divisor specified by CpuDid)) */
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CPU COF is (100MHz * (CpuFid + 10h) / (divisor specified by CpuDid))
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Note: This family contains only APUs */
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err = cpu_rdmsr_range(info->handle, pstate, 8, 4, &CpuFid);
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err += cpu_rdmsr_range(info->handle, pstate, 3, 0, &CpuDid);
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i = 0;
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while (i < num_dids && divisor_t[i].did != CpuDid)
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i++;
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if (i < num_dids)
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*multiplier = (uint64_t) ((CpuFid + 0x10) / divisor_t[i].divisor);
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*multiplier = (double) ((CpuFid + magic_constant) / divisor_t[i].divisor);
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else
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err++;
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break;
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@ -662,37 +670,39 @@ static int get_amd_multipliers(struct msr_info_t *info, uint32_t pstate, uint64_
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MSRC001_00[6B:64][3:0] is CpuDidLSD
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PLL COF is (100 MHz * (D18F3xD4[MainPllOpFreqId] + 10h))
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Divisor is (CpuDidMSD + (CpuDidLSD * 0.25) + 1)
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CPU COF is (main PLL frequency specified by D18F3xD4[MainPllOpFreqId]) / (core clock divisor specified by CpuDidMSD and CpuDidLSD) */
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CPU COF is (main PLL frequency specified by D18F3xD4[MainPllOpFreqId]) / (core clock divisor specified by CpuDidMSD and CpuDidLSD)
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Note: This family contains only APUs */
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err = cpu_rdmsr_range(info->handle, pstate, 8, 4, &CpuDid);
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err += cpu_rdmsr_range(info->handle, pstate, 3, 0, &CpuDidLSD);
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*multiplier = (uint64_t) (((info->cpu_clock + 5) / 100 + 0x10) / (CpuDid + CpuDidLSD * 0.25 + 1));
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*multiplier = (double) (((info->cpu_clock + 5) / 100 + magic_constant) / (CpuDid + CpuDidLSD * 0.25 + 1));
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break;
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case 0x11:
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/* BKDG 11h, page 236
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MSRC001_00[6B:64][8:6] is CpuDid
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MSRC001_00[6B:64][5:0] is CpuFid
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CPU COF is ((100 MHz * (CpuFid + 08h)) / (2^CpuDid)) */
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magic_constant = 0x8;
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case 0x10:
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/* BKDG 10h, page 429
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MSRC001_00[6B:64][8:6] is CpuDid
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MSRC001_00[6B:64][5:0] is CpuFid
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CPU COF is (100 MHz * (CpuFid + 10h) / (2^CpuDid))
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N.B.: The (stock) bus speed is 200MHz on AMD 10h & 11h families, we need to divid by 2 */
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divisor = 2;
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Note: This family contains only CPUs */
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case 0x11:
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/* BKDG 11h, page 236
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MSRC001_00[6B:64][8:6] is CpuDid
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MSRC001_00[6B:64][5:0] is CpuFid
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CPU COF is ((100 MHz * (CpuFid + 08h)) / (2^CpuDid))
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Note: This family contains only CPUs */
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case 0x15:
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/* BKDG 15h, page 570/580/635/692 (00h-0Fh/10h-1Fh/30h-3Fh/60h-6Fh)
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MSRC001_00[6B:64][8:6] is CpuDid
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MSRC001_00[6B:64][5:0] is CpuFid
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CoreCOF is (100 * (MSRC001_00[6B:64][CpuFid] + 10h) / (2^MSRC001_00[6B:64][CpuDid])) */
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CoreCOF is (100 * (MSRC001_00[6B:64][CpuFid] + 10h) / (2^MSRC001_00[6B:64][CpuDid]))
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Note: This family contains BOTH CPUs and APUs */
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case 0x16:
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/* BKDG 16h, page 549/611 (00h-0Fh/30h-3Fh)
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MSRC001_00[6B:64][8:6] is CpuDid
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MSRC001_00[6B:64][5:0] is CpuFid
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CoreCOF is (100 * (MSRC001_00[6B:64][CpuFid] + 10h) / (2^MSRC001_00[6B:64][CpuDid])) */
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CoreCOF is (100 * (MSRC001_00[6B:64][CpuFid] + 10h) / (2^MSRC001_00[6B:64][CpuDid]))
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Note: This family contains only APUs */
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err = cpu_rdmsr_range(info->handle, pstate, 8, 6, &CpuDid);
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err += cpu_rdmsr_range(info->handle, pstate, 5, 0, &CpuFid);
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*multiplier = (uint64_t) ((CpuFid + magic_constant) / (1ull << CpuDid)) / divisor;
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*multiplier = (double) ((CpuFid + magic_constant) / (1ull << CpuDid)) / divisor;
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break;
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case 0x17:
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/* PPR 17h, pages 30 and 138-139
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@ -701,7 +711,7 @@ static int get_amd_multipliers(struct msr_info_t *info, uint32_t pstate, uint64_
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CoreCOF is (Core::X86::Msr::PStateDef[CpuFid[7:0]] / Core::X86::Msr::PStateDef[CpuDfsId]) * 200 */
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err = cpu_rdmsr_range(info->handle, pstate, 13, 8, &CpuDid);
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err += cpu_rdmsr_range(info->handle, pstate, 7, 0, &CpuFid);
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*multiplier = (uint64_t) (CpuFid / CpuDid) * 2;
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*multiplier = (double) (CpuFid / CpuDid) * 2;
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break;
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default:
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err = 1;
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@ -734,6 +744,7 @@ static uint32_t get_amd_last_pstate_addr(struct msr_info_t *info)
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static double get_info_min_multiplier(struct msr_info_t *info)
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{
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int err;
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double mult;
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uint32_t addr;
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uint64_t reg;
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@ -756,8 +767,8 @@ static double get_info_min_multiplier(struct msr_info_t *info)
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/* N.B.: Find the last P-state
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get_amd_last_pstate_addr() returns the last P-state, MSR_PSTATE_0 <= addr <= MSR_PSTATE_7 */
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addr = get_amd_last_pstate_addr(info);
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err = get_amd_multipliers(info, addr, ®);
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if (!err) return (double) reg;
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err = get_amd_multipliers(info, addr, &mult);
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if (!err) return mult;
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}
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return (double) CPU_INVALID_VALUE / 100;
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@ -766,6 +777,7 @@ static double get_info_min_multiplier(struct msr_info_t *info)
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static double get_info_cur_multiplier(struct msr_info_t *info)
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{
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int err;
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double mult;
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uint64_t reg;
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if(info->id->vendor == VENDOR_INTEL && info->internal->code.intel == PENTIUM) {
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@ -784,8 +796,8 @@ static double get_info_cur_multiplier(struct msr_info_t *info)
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/* Refer links above
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MSRC001_0063[2:0] is CurPstate */
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err = cpu_rdmsr_range(info->handle, MSR_PSTATE_S, 2, 0, ®);
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err += get_amd_multipliers(info, MSR_PSTATE_0 + (uint32_t) reg, ®);
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if (!err) return (double) reg;
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err += get_amd_multipliers(info, MSR_PSTATE_0 + (uint32_t) reg, &mult);
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if (!err) return mult;
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}
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return (double) CPU_INVALID_VALUE / 100;
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@ -794,6 +806,7 @@ static double get_info_cur_multiplier(struct msr_info_t *info)
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static double get_info_max_multiplier(struct msr_info_t *info)
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{
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int err;
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double mult;
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uint64_t reg;
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if(info->id->vendor == VENDOR_INTEL && info->internal->code.intel == PENTIUM) {
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@ -823,8 +836,8 @@ static double get_info_max_multiplier(struct msr_info_t *info)
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/* Refer links above
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MSRC001_0064 is Pb0
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Pb0 is the highest-performance boosted P-state */
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err = get_amd_multipliers(info, MSR_PSTATE_0, ®);
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if (!err) return (double) reg;
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err = get_amd_multipliers(info, MSR_PSTATE_0, &mult);
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if (!err) return mult;
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}
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return (double) CPU_INVALID_VALUE / 100;
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@ -860,6 +873,7 @@ static int get_info_temperature(struct msr_info_t *info)
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static double get_info_voltage(struct msr_info_t *info)
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{
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int err;
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double VIDStep;
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uint64_t reg, CpuVid;
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if(info->id->vendor == VENDOR_INTEL) {
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@ -875,13 +889,16 @@ static double get_info_voltage(struct msr_info_t *info)
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MSRC001_00[6B:64][15:9] is CpuVid (Jaguar and before)
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MSRC001_00[6B:64][21:14] is CpuVid (Zen)
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MSRC001_0063[2:0] is P-state Status
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2.4.1.6.3 Serial VID (SVI) Encodings: voltage = 1.550V - 0.0125V * SviVid[6:0] */
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err = cpu_rdmsr_range(info->handle, MSR_PSTATE_S, 2, 0, ®);
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BKDG 10h, page 49: voltage = 1.550V - 0.0125V * SviVid (SVI1)
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BKDG 15h, page 50: Voltage = 1.5500 - 0.00625 * Vid[7:0] (SVI2)
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SVI2 since Piledriver (Family 15h, 2nd-gen): Models 10h-1Fh Processors */
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VIDStep = ((info->id->ext_family < 0x15) || ((info->id->ext_family == 0x15) && (info->id->ext_model < 0x10))) ? 0.0125 : 0.00625;
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err = cpu_rdmsr_range(info->handle, MSR_PSTATE_S, 2, 0, ®);
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if(info->id->ext_family < 0x17)
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err += cpu_rdmsr_range(info->handle, MSR_PSTATE_0 + (uint32_t) reg, 15, 9, &CpuVid);
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else
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err += cpu_rdmsr_range(info->handle, MSR_PSTATE_0 + (uint32_t) reg, 21, 14, &CpuVid);
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if (!err && MSR_PSTATE_0 + (uint32_t) reg <= MSR_PSTATE_7) return 1.550 - 0.0125 * CpuVid;
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if (!err && MSR_PSTATE_0 + (uint32_t) reg <= MSR_PSTATE_7) return 1.550 - VIDStep * CpuVid;
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}
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return (double) CPU_INVALID_VALUE / 100;
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@ -890,6 +907,7 @@ static double get_info_voltage(struct msr_info_t *info)
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static double get_info_bus_clock(struct msr_info_t *info)
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{
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int err;
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double mult;
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uint32_t addr;
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uint64_t reg;
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@ -912,8 +930,8 @@ static double get_info_bus_clock(struct msr_info_t *info)
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PstateMaxVal is the the lowest-performance non-boosted P-state */
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addr = get_amd_last_pstate_addr(info);
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err = cpu_rdmsr_range(info->handle, MSR_PSTATE_L, 6, 4, ®);
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err += get_amd_multipliers(info, addr - reg, ®);
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if (!err) return (double) info->cpu_clock / reg;
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err += get_amd_multipliers(info, addr - reg, &mult);
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if (!err) return (double) info->cpu_clock / mult;
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}
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return (double) CPU_INVALID_VALUE / 100;
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