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Support for Gulftown (westmere-based) Intels, and for AMD X6 (Thuban). Also differentiated the Thuban-derived X4s (Zosma) which I suppose also have ext model 10, but this needs to be verified.

git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@88 3b4be424-7ac5-41d7-8526-f4ddcb85d872
This commit is contained in:
Veselin Georgiev 2010-10-13 11:59:46 +00:00
commit 6a7854f3b4
3 changed files with 296 additions and 3 deletions

View file

@ -227,7 +227,10 @@ const struct match_entry_t cpudb_amd[] = {
{ 15, 4, -1, 16, -1, 2, 1024, -1, ATHLON_64_X2 , 0, "Athlon II X2 (Regor)" },
{ 15, 4, -1, 16, -1, 2, 512, -1, PHENOM2 , 0, "Phenom II X2 (Callisto)" },
{ 15, 4, -1, 16, -1, 3, 512, -1, PHENOM2 , 0, "Phenom II X3 (Heka)" },
{ 15, 4, -1, 16, -1, 4, 512, -1, PHENOM2 , 0, "Phenom II X4 (Deneb)" },
{ 15, 4, -1, 16, -1, 4, 512, -1, PHENOM2 , 0, "Phenom II X4" },
{ 15, 4, -1, 16, 4, 4, 512, -1, PHENOM2 , 0, "Phenom II X4 (Deneb)" },
{ 15, 4, -1, 16, 10, 4, 512, -1, PHENOM2 , 0, "Phenom II X4 (Zosma)" },
{ 15, 4, -1, 16, 10, 6, 512, -1, PHENOM2 , 0, "Phenom II X6 (Thuban)" },
{ 15, 5, -1, 16, -1, 4, 512, -1, ATHLON_64_X4 , 0, "Athlon II X4 (Propus)" },
};

View file

@ -41,6 +41,7 @@ enum _intel_code_t {
XEON_POTOMAC,
XEON_I7,
XEON_GAINESTOWN,
XEON_WESTMERE,
MOBILE_PENTIUM_M,
CELERON,
MOBILE_CELERON,
@ -254,7 +255,15 @@ const struct match_entry_t cpudb_intel[] = {
{ 6, 10, -1, -1, 26, 1, -1, -1, CORE_I7 , 0, "Intel Core i7" },
{ 6, 10, -1, -1, 26, 4, -1, -1, CORE_I7 , 0, "Bloomfield (Core i7)" },
{ 6, 10, -1, -1, 26, 4, -1, -1, XEON_I7 , 0, "Xeon (Bloomfield)" },
{ 6, 10, -1, -1, 26, 4, -1, -1, XEON_GAINESTOWN , 0, "Xeon (Gainestown)" },
{ 6, 10, -1, -1, 26, 4, -1, 4096, XEON_GAINESTOWN , 0, "Xeon (Gainestown) 4M" },
{ 6, 10, -1, -1, 26, 4, -1, 8192, XEON_GAINESTOWN , 0, "Xeon (Gainestown) 8M" },
{ 6, 12, -1, -1, 44, -1, -1, -1, XEON_WESTMERE , 0, "Xeon (Westmere-based)" },
{ 6, 12, -1, -1, 44, 4, -1, 12288, CORE_I7 , 0, "Gulftown (Core i7)" },
{ 6, 12, -1, -1, 44, -1, -1, 12288, XEON_WESTMERE , 0, "Xeon (Gulftown)" },
/* Core microarchitecture-based Xeons: */
@ -580,10 +589,12 @@ static intel_code_t get_brand_code(struct cpu_id_t* data)
}
}
if (code == XEON) {
if (match_pattern(bs, "W35##"))
if (match_pattern(bs, "W35##") || match_pattern(bs, "[ELXW]75##"))
code = XEON_I7;
else if (match_pattern(bs, "[ELXW]55##"))
code = XEON_GAINESTOWN;
else if (match_pattern(bs, "[ELXW]56##"))
code = XEON_WESTMERE;
else if (data->l3_cache > 0)
code = XEON_IRWIN;
}