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Fixed issue #7: Atom N2800

Reorganize the detection for Intel Atom CPUs

- no longer make the distinction between single- and dualcore CPUs.
- correctly handle all Pineview and Cedarview CPUs.
This commit is contained in:
Veselin Georgiev 2014-08-20 11:26:29 +03:00
parent ece31fb8d3
commit 7bd1382309

View file

@ -33,24 +33,29 @@
enum _intel_code_t { enum _intel_code_t {
NA, NA,
NO_CODE, NO_CODE,
PENTIUM, PENTIUM = 10,
MOBILE_PENTIUM, MOBILE_PENTIUM,
XEON,
XEON = 20,
XEON_IRWIN, XEON_IRWIN,
XEONMP, XEONMP,
XEON_POTOMAC, XEON_POTOMAC,
XEON_I7, XEON_I7,
XEON_GAINESTOWN, XEON_GAINESTOWN,
XEON_WESTMERE, XEON_WESTMERE,
MOBILE_PENTIUM_M,
MOBILE_PENTIUM_M = 30,
CELERON, CELERON,
MOBILE_CELERON, MOBILE_CELERON,
NOT_CELERON, NOT_CELERON,
CORE_SOLO,
CORE_SOLO = 40,
MOBILE_CORE_SOLO, MOBILE_CORE_SOLO,
CORE_DUO, CORE_DUO,
MOBILE_CORE_DUO, MOBILE_CORE_DUO,
WOLFDALE,
WOLFDALE = 50,
MEROM, MEROM,
PENRYN, PENRYN,
QUAD_CORE, QUAD_CORE,
@ -58,11 +63,14 @@ enum _intel_code_t {
QUAD_CORE_HT, QUAD_CORE_HT,
MORE_THAN_QUADCORE, MORE_THAN_QUADCORE,
PENTIUM_D, PENTIUM_D,
ATOM_DIAMONDVILLE,
ATOM_DUALCORE, ATOM = 60,
ATOM_SILVERTHORNE, ATOM_SILVERTHORNE,
ATOM_DIAMONDVILLE,
ATOM_PINEVIEW, ATOM_PINEVIEW,
CORE_I3, ATOM_CEDARVIEW,
CORE_I3 = 70,
CORE_I5, CORE_I5,
CORE_I7, CORE_I7,
CORE_IVY3, /* 22nm Core-iX */ CORE_IVY3, /* 22nm Core-iX */
@ -206,12 +214,13 @@ const struct match_entry_t cpudb_intel[] = {
{ 6, 13, -1, -1, -1, 1, -1, -1, MOBILE_PENTIUM_M , 0, "Pentium M (Dothan)" }, { 6, 13, -1, -1, -1, 1, -1, -1, MOBILE_PENTIUM_M , 0, "Pentium M (Dothan)" },
{ 6, 13, -1, -1, -1, 1, -1, -1, CELERON , 0, "Celeron M" }, { 6, 13, -1, -1, -1, 1, -1, -1, CELERON , 0, "Celeron M" },
{ 6, 12, -1, -1, -1, 1, -1, -1, NO_CODE , 0, "Unknown Atom" }, { 6, 12, -1, -1, -1, -1, -1, -1, ATOM , 0, "Unknown Atom" },
{ 6, 12, -1, -1, -1, 1, -1, -1, ATOM_DIAMONDVILLE , 0, "Atom (Diamondville)" }, { 6, 12, -1, -1, -1, -1, -1, -1, ATOM_DIAMONDVILLE , 0, "Atom (Diamondville)" },
{ 6, 12, -1, -1, -1, 1, -1, -1, ATOM_DUALCORE , 0, "Atom Dual-Core (Diamondville)" }, { 6, 12, -1, -1, -1, -1, -1, -1, ATOM_DIAMONDVILLE , 0, "Atom (Diamondville)" },
{ 6, 12, -1, -1, -1, 1, -1, -1, ATOM_SILVERTHORNE , 0, "Atom (Silverthorne)" }, { 6, 12, -1, -1, -1, -1, -1, -1, ATOM_SILVERTHORNE , 0, "Atom (Silverthorne)" },
{ 6, 12, -1, -1, -1, 2, -1, -1, NO_CODE , 0, "Atom (Cedarview)" }, { 6, 12, -1, -1, -1, -1, -1, -1, ATOM_CEDARVIEW , 0, "Atom (Cedarview)" },
{ 6, 12, -1, -1, -1, 1, -1, -1, ATOM_PINEVIEW , 0, "Atom (Pineview)" }, { 6, 6, -1, -1, -1, -1, -1, -1, ATOM_CEDARVIEW , 0, "Atom (Cedarview)" },
{ 6, 12, -1, -1, -1, -1, -1, -1, ATOM_PINEVIEW , 0, "Atom (Pineview)" },
/* -------------------------------------------------- */ /* -------------------------------------------------- */
@ -597,11 +606,11 @@ static intel_code_t get_brand_code(struct cpu_id_t* data)
{ PENTIUM, "Pentium" }, { PENTIUM, "Pentium" },
{ CORE_SOLO, "Genuine Intel(R) CPU" }, { CORE_SOLO, "Genuine Intel(R) CPU" },
{ CORE_SOLO, "Intel(R) Core(TM)" }, { CORE_SOLO, "Intel(R) Core(TM)" },
{ ATOM_DIAMONDVILLE, "Atom(TM) CPU 2" }, { ATOM_DIAMONDVILLE, "Atom(TM) CPU [N ][23]## " },
{ ATOM_DIAMONDVILLE, "Atom(TM) CPU N" },
{ ATOM_DUALCORE, "Atom(TM) CPU 3" },
{ ATOM_SILVERTHORNE, "Atom(TM) CPU Z" }, { ATOM_SILVERTHORNE, "Atom(TM) CPU Z" },
{ ATOM_PINEVIEW, "Atom(TM) CPU D" }, { ATOM_PINEVIEW, "Atom(TM) CPU D" },
{ ATOM_CEDARVIEW, "Atom(TM) CPU N####" },
{ ATOM, "Atom(TM) CPU" },
}; };
if (strstr(bs, "Mobile")) { if (strstr(bs, "Mobile")) {
@ -632,10 +641,11 @@ static intel_code_t get_brand_code(struct cpu_id_t* data)
} }
if (need_matchtable) { if (need_matchtable) {
for (i = 0; i < COUNT_OF(matchtable); i++) for (i = 0; i < COUNT_OF(matchtable); i++)
if (strstr(bs, matchtable[i].search)) { if (match_pattern(bs, matchtable[i].search)) {
code = matchtable[i].c; code = matchtable[i].c;
break; break;
} }
debugf(2, "intel matchtable result is %d\n", code);
} }
if (code == XEON) { if (code == XEON) {
if (match_pattern(bs, "W35##") || match_pattern(bs, "[ELXW]75##")) if (match_pattern(bs, "W35##") || match_pattern(bs, "[ELXW]75##"))