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Fixed issue #7: Atom N2800
Reorganize the detection for Intel Atom CPUs - no longer make the distinction between single- and dualcore CPUs. - correctly handle all Pineview and Cedarview CPUs.
This commit is contained in:
parent
ece31fb8d3
commit
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1 changed files with 28 additions and 18 deletions
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@ -33,24 +33,29 @@
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enum _intel_code_t {
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enum _intel_code_t {
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NA,
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NA,
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NO_CODE,
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NO_CODE,
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PENTIUM,
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PENTIUM = 10,
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MOBILE_PENTIUM,
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MOBILE_PENTIUM,
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XEON,
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XEON = 20,
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XEON_IRWIN,
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XEON_IRWIN,
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XEONMP,
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XEONMP,
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XEON_POTOMAC,
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XEON_POTOMAC,
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XEON_I7,
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XEON_I7,
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XEON_GAINESTOWN,
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XEON_GAINESTOWN,
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XEON_WESTMERE,
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XEON_WESTMERE,
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MOBILE_PENTIUM_M,
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MOBILE_PENTIUM_M = 30,
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CELERON,
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CELERON,
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MOBILE_CELERON,
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MOBILE_CELERON,
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NOT_CELERON,
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NOT_CELERON,
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CORE_SOLO,
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CORE_SOLO = 40,
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MOBILE_CORE_SOLO,
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MOBILE_CORE_SOLO,
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CORE_DUO,
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CORE_DUO,
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MOBILE_CORE_DUO,
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MOBILE_CORE_DUO,
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WOLFDALE,
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WOLFDALE = 50,
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MEROM,
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MEROM,
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PENRYN,
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PENRYN,
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QUAD_CORE,
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QUAD_CORE,
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@ -58,11 +63,14 @@ enum _intel_code_t {
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QUAD_CORE_HT,
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QUAD_CORE_HT,
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MORE_THAN_QUADCORE,
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MORE_THAN_QUADCORE,
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PENTIUM_D,
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PENTIUM_D,
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ATOM_DIAMONDVILLE,
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ATOM_DUALCORE,
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ATOM = 60,
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ATOM_SILVERTHORNE,
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ATOM_SILVERTHORNE,
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ATOM_DIAMONDVILLE,
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ATOM_PINEVIEW,
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ATOM_PINEVIEW,
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CORE_I3,
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ATOM_CEDARVIEW,
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CORE_I3 = 70,
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CORE_I5,
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CORE_I5,
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CORE_I7,
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CORE_I7,
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CORE_IVY3, /* 22nm Core-iX */
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CORE_IVY3, /* 22nm Core-iX */
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@ -206,12 +214,13 @@ const struct match_entry_t cpudb_intel[] = {
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{ 6, 13, -1, -1, -1, 1, -1, -1, MOBILE_PENTIUM_M , 0, "Pentium M (Dothan)" },
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{ 6, 13, -1, -1, -1, 1, -1, -1, MOBILE_PENTIUM_M , 0, "Pentium M (Dothan)" },
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{ 6, 13, -1, -1, -1, 1, -1, -1, CELERON , 0, "Celeron M" },
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{ 6, 13, -1, -1, -1, 1, -1, -1, CELERON , 0, "Celeron M" },
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{ 6, 12, -1, -1, -1, 1, -1, -1, NO_CODE , 0, "Unknown Atom" },
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{ 6, 12, -1, -1, -1, -1, -1, -1, ATOM , 0, "Unknown Atom" },
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{ 6, 12, -1, -1, -1, 1, -1, -1, ATOM_DIAMONDVILLE , 0, "Atom (Diamondville)" },
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{ 6, 12, -1, -1, -1, -1, -1, -1, ATOM_DIAMONDVILLE , 0, "Atom (Diamondville)" },
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{ 6, 12, -1, -1, -1, 1, -1, -1, ATOM_DUALCORE , 0, "Atom Dual-Core (Diamondville)" },
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{ 6, 12, -1, -1, -1, -1, -1, -1, ATOM_DIAMONDVILLE , 0, "Atom (Diamondville)" },
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{ 6, 12, -1, -1, -1, 1, -1, -1, ATOM_SILVERTHORNE , 0, "Atom (Silverthorne)" },
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{ 6, 12, -1, -1, -1, -1, -1, -1, ATOM_SILVERTHORNE , 0, "Atom (Silverthorne)" },
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{ 6, 12, -1, -1, -1, 2, -1, -1, NO_CODE , 0, "Atom (Cedarview)" },
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{ 6, 12, -1, -1, -1, -1, -1, -1, ATOM_CEDARVIEW , 0, "Atom (Cedarview)" },
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{ 6, 12, -1, -1, -1, 1, -1, -1, ATOM_PINEVIEW , 0, "Atom (Pineview)" },
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{ 6, 6, -1, -1, -1, -1, -1, -1, ATOM_CEDARVIEW , 0, "Atom (Cedarview)" },
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{ 6, 12, -1, -1, -1, -1, -1, -1, ATOM_PINEVIEW , 0, "Atom (Pineview)" },
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/* -------------------------------------------------- */
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/* -------------------------------------------------- */
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@ -597,11 +606,11 @@ static intel_code_t get_brand_code(struct cpu_id_t* data)
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{ PENTIUM, "Pentium" },
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{ PENTIUM, "Pentium" },
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{ CORE_SOLO, "Genuine Intel(R) CPU" },
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{ CORE_SOLO, "Genuine Intel(R) CPU" },
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{ CORE_SOLO, "Intel(R) Core(TM)" },
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{ CORE_SOLO, "Intel(R) Core(TM)" },
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{ ATOM_DIAMONDVILLE, "Atom(TM) CPU 2" },
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{ ATOM_DIAMONDVILLE, "Atom(TM) CPU [N ][23]## " },
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{ ATOM_DIAMONDVILLE, "Atom(TM) CPU N" },
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{ ATOM_DUALCORE, "Atom(TM) CPU 3" },
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{ ATOM_SILVERTHORNE, "Atom(TM) CPU Z" },
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{ ATOM_SILVERTHORNE, "Atom(TM) CPU Z" },
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{ ATOM_PINEVIEW, "Atom(TM) CPU D" },
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{ ATOM_PINEVIEW, "Atom(TM) CPU D" },
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{ ATOM_CEDARVIEW, "Atom(TM) CPU N####" },
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{ ATOM, "Atom(TM) CPU" },
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};
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};
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if (strstr(bs, "Mobile")) {
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if (strstr(bs, "Mobile")) {
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@ -632,10 +641,11 @@ static intel_code_t get_brand_code(struct cpu_id_t* data)
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}
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}
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if (need_matchtable) {
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if (need_matchtable) {
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for (i = 0; i < COUNT_OF(matchtable); i++)
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for (i = 0; i < COUNT_OF(matchtable); i++)
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if (strstr(bs, matchtable[i].search)) {
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if (match_pattern(bs, matchtable[i].search)) {
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code = matchtable[i].c;
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code = matchtable[i].c;
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break;
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break;
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}
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}
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debugf(2, "intel matchtable result is %d\n", code);
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}
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}
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if (code == XEON) {
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if (code == XEON) {
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if (match_pattern(bs, "W35##") || match_pattern(bs, "[ELXW]75##"))
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if (match_pattern(bs, "W35##") || match_pattern(bs, "[ELXW]75##"))
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