mirror/libcpuid
1
0
Fork 0
mirror of https://github.com/anrieff/libcpuid synced 2025-02-12 20:24:05 +00:00
Code Issues Releases Wiki Activity

RDMSR: fix VID range for AMD family 15h and above

Browse source 
Fix #91
This commit is contained in:
Xorg 2017-04-30 20:20:39 +02:00
parent 58b8eabd7c
commit 84f95c8ad0
1 changed files with 7 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

10
libcpuid/rdmsr.c
View file

@ -528,6 +528,7 @@ int msr_serialize_raw_data(struct msr_driver_t* handle, const char* filename)
http://support.amd.com/TechDocs/42300_15h_Mod_10h-1Fh_BKDG.pdf
http://support.amd.com/TechDocs/49125_15h_Models_30h-3Fh_BKDG.pdf
http://support.amd.com/TechDocs/50742_15h_Models_60h-6Fh_BKDG.pdf
http://support.amd.com/TechDocs/55072_AMD_Family_15h_Models_70h-7Fh_BKDG.pdf
* AMD Family 16h Processors
http://support.amd.com/TechDocs/48751_16h_bkdg.pdf
http://support.amd.com/TechDocs/52740_16h_Models_30h-3Fh_BKDG.pdf
@ -868,6 +869,7 @@ static int get_info_temperature(struct msr_info_t *info)
static double get_info_voltage(struct msr_info_t *info)
{
int err;
double VIDStep;
uint64_t reg, CpuVid;
if(info->id->vendor == VENDOR_INTEL) {
@ -883,13 +885,15 @@ static double get_info_voltage(struct msr_info_t *info)
MSRC001_00[6B:64][15:9] is CpuVid (Jaguar and before)
MSRC001_00[6B:64][21:14] is CpuVid (Zen)
MSRC001_0063[2:0] is P-state Status
2.4.1.6.3 Serial VID (SVI) Encodings: voltage = 1.550V - 0.0125V * SviVid[6:0] */
err = cpu_rdmsr_range(info->handle, MSR_PSTATE_S, 2, 0, &reg);
BKDG 10h, page 49: voltage = 1.550V - 0.0125V * SviVid (SVI1)
BKDG 15h, page 50: Voltage = 1.5500 - 0.00625 * Vid[7:0] (SVI2) */
err = cpu_rdmsr_range(info->handle, MSR_PSTATE_S, 2, 0, &reg);
if(info->id->ext_family < 0x17)
err += cpu_rdmsr_range(info->handle, MSR_PSTATE_0 + (uint32_t) reg, 15, 9, &CpuVid);
else
err += cpu_rdmsr_range(info->handle, MSR_PSTATE_0 + (uint32_t) reg, 21, 14, &CpuVid);
if (!err && MSR_PSTATE_0 + (uint32_t) reg <= MSR_PSTATE_7) return 1.550 - 0.0125 * CpuVid;
VIDStep = (info->id->ext_family < 0x15) ? 0.0125 : 0.00625;
if (!err && MSR_PSTATE_0 + (uint32_t) reg <= MSR_PSTATE_7) return 1.550 - VIDStep * CpuVid;
}
return (double) CPU_INVALID_VALUE / 100;