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Possibly fix #89: Build failes with MSVC

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Fix non-C89 constructs. Not really verified to compile fine on MSVC,
since I don't have one right now, but will check later.
This commit is contained in:
Veselin Georgiev 2017-04-03 13:24:57 +03:00
parent 94507ded22
commit 88483aaba0
3 changed files with 28 additions and 16 deletions
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24
libcpuid/rdmsr.c
View file

@ -621,6 +621,18 @@ static int get_amd_multipliers(struct msr_info_t *info, uint32_t pstate, uint64_
int divisor = 1;
int magic_constant = 0x10;
uint64_t CpuFid, CpuDid, CpuDidLSD;
const struct { uint64_t did; double divisor; } divisor_t[] = {
{ 0x0, 1 },
{ 0x1, 1.5 },
{ 0x2, 2 },
{ 0x3, 3 },
{ 0x4, 4 },
{ 0x5, 6 },
{ 0x6, 8 },
{ 0x7, 12 },
{ 0x8, 16 },
{ CpuDid, 0 },
};
if (pstate < MSR_PSTATE_0 || MSR_PSTATE_7 < pstate)
return 1;
@ -633,18 +645,6 @@ static int get_amd_multipliers(struct msr_info_t *info, uint32_t pstate, uint64_
CPU COF is (100MHz * (CpuFid + 10h) / (divisor specified by CpuDid)) */
err = cpu_rdmsr_range(info->handle, pstate, 8, 4, &CpuFid);
err += cpu_rdmsr_range(info->handle, pstate, 3, 0, &CpuDid);
const struct { uint64_t did; double divisor; } divisor_t[] = {
{ 0x0, 1 },
{ 0x1, 1.5 },
{ 0x2, 2 },
{ 0x3, 3 },
{ 0x4, 4 },
{ 0x5, 6 },
{ 0x6, 8 },
{ 0x7, 12 },
{ 0x8, 16 },
{ CpuDid, 0 },
};
i = 0;
while(divisor_t[i].did != CpuDid)
i++;

13
libcpuid/recog_amd.c
View file

@ -436,6 +436,8 @@ static struct amd_code_and_bits_t decode_amd_codename_part1(const char *bs)
{
amd_code_t code = NC;
uint64_t bits = 0;
struct amd_code_and_bits_t result;
if (strstr(bs, "Dual Core") ||
strstr(bs, "Dual-Core") ||
strstr(bs, " X2 "))
@ -473,7 +475,8 @@ static struct amd_code_and_bits_t decode_amd_codename_part1(const char *bs)
if (match_pattern(bs, "Z-##")) code = FUSION_Z;
if (match_pattern(bs, "E#-####") || match_pattern(bs, "A#-####")) code = FUSION_EA;
struct amd_code_and_bits_t result = { code, bits };
result.code = code;
result.bits = bits;
return result;
}
@ -501,6 +504,8 @@ static void decode_amd_codename(struct cpu_raw_data_t* raw, struct cpu_id_t* dat
struct amd_code_and_bits_t code_and_bits = decode_amd_codename_part1(data->brand_str);
int i = 0;
char* code_str = NULL;
int model_code;
for (i = 0; i < COUNT_OF(amd_code_str); i++) {
if (code_and_bits.code == amd_code_str[i].code) {
code_str = amd_code_str[i].str;
@ -516,8 +521,12 @@ static void decode_amd_codename(struct cpu_raw_data_t* raw, struct cpu_id_t* dat
else
debugf(2, "Detected AMD brand code: %d\n", code_and_bits.code);
if (code_and_bits.bits) {
debugf(2, "Detected AMD bits: ");
debug_print_lbits(2, code_and_bits.bits);
}
// is it Ryzen? if so, we need to detect discern between the four-core 1400/1500 (Ryzen 5) and the four-core Ryzen 3:
int model_code = (data->ext_family == 23) ? decode_amd_ryzen_model_code(data->brand_str) : 0;
model_code = (data->ext_family == 23) ? decode_amd_ryzen_model_code(data->brand_str) : 0;
internal->code.amd = code_and_bits.code;
internal->bits = code_and_bits.bits;

7
libcpuid/recog_intel.c
View file

@ -648,6 +648,7 @@ static void decode_intel_number_of_cores(struct cpu_raw_data_t* raw,
static intel_code_and_bits_t get_brand_code_and_bits(struct cpu_id_t* data)
{
intel_code_t code = (intel_code_t) NC;
intel_code_and_bits_t result;
uint64_t bits = 0;
int i = 0;
const char* bs = data->brand_str;
@ -753,7 +754,9 @@ static intel_code_and_bits_t get_brand_code_and_bits(struct cpu_id_t* data)
(code == CORE_DUO || code == PENTIUM_D || (bits & CELERON_))) {
code = WOLFDALE;
}
intel_code_and_bits_t result = { code, bits };
result.code = code;
result.bits = bits;
return result;
}
@ -908,7 +911,7 @@ int cpuid_identify_intel(struct cpu_raw_data_t* raw, struct cpu_id_t* data, stru
debugf(2, "Detected Intel brand code: %d\n", brand.code);
if (brand.bits) {
debugf(2, "Detected Intel bits: ");
debug_print_lbits(brand.bits, 2);
debug_print_lbits(2, brand.bits);
}
debugf(2, "Detected Intel model code: %d\n", model_code);