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Merge pull request #125 from X0rg/master

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More test files for AMD Zen CPUs
This commit is contained in:
Veselin Georgiev 2019-07-11 08:34:24 +03:00 • committed by GitHub
commit ab3bc3defe
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13 changed files with 758 additions and 7 deletions
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6
libcpuid/libcpuid_internal.h
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@ -67,6 +67,7 @@ enum _common_bits_t {
_3 = LBIT( 3 ),
_5 = LBIT( 4 ),
_7 = LBIT( 5 ),
_9 = LBIT( 6 ),
};
// additional detection bits for Intel CPUs:
@ -75,9 +76,8 @@ enum _intel_bits_t {
CELERON_ = LBIT( 11 ),
CORE_ = LBIT( 12 ),
_I_ = LBIT( 13 ),
_9 = LBIT( 14 ),
XEON_ = LBIT( 15 ),
ATOM_ = LBIT( 16 ),
XEON_ = LBIT( 14 ),
ATOM_ = LBIT( 15 ),
};
typedef enum _intel_bits_t intel_bits_t;

22
libcpuid/recog_amd.c
View file

@ -262,22 +262,35 @@ const struct match_entry_t cpudb_amd[] = {
{ 15, 0, -1, 22, 48, 2, -1, -1, FUSION_E, 0 , 0, "Mullins X2" },
{ 15, 0, -1, 22, 48, 4, -1, -1, FUSION_A, 0 , 0, "Mullins X4" },
/* Family 17h: Zen Architecture (2017) */
/* Family 17h: Zen Architecture (2017) => https://en.wikichip.org/wiki/amd/microarchitectures/zen */
{ 15, -1, -1, 23, 1, -1, -1, -1, NC, EPYC_ , 0, "EPYC (Naples)" },
{ 15, -1, -1, 23, 1, -1, -1, -1, NC, RYZEN_TR_ , 0, "Threadripper (Whitehaven)" },
{ 15, -1, -1, 23, 1, -1, -1, -1, NC, RYZEN_|_7 , 0, "Ryzen 7 (Summit Ridge)" },
{ 15, -1, -1, 23, 1, -1, -1, -1, NC, RYZEN_|_5 , 0, "Ryzen 5 (Summit Ridge)" },
{ 15, -1, -1, 23, 1, -1, -1, -1, NC, RYZEN_|_3 , 0, "Ryzen 3 (Summit Ridge)" },
/* APUs */
{ 15, -1, -1, 23, 17, -1, -1, -1, NC, RYZEN_|_7 , 0, "Ryzen 7 (Raven Ridge)" },
{ 15, -1, -1, 23, 17, -1, -1, -1, NC, RYZEN_|_5 , 0, "Ryzen 5 (Raven Ridge)" },
{ 15, -1, -1, 23, 17, -1, -1, -1, NC, RYZEN_|_3 , 0, "Ryzen 3 (Raven Ridge)" },
{ 15, -1, -1, 23, 17, -1, -1, -1, NC, ATHLON_ , 0, "Athlon (Raven Ridge)" },
/* 2nd-gen, Zen+ (2018): */
/* Zen+ (2018) => https://en.wikichip.org/wiki/amd/microarchitectures/zen%2B */
{ 15, -1, -1, 23, 8, -1, -1, -1, NC, RYZEN_TR_ , 0, "Threadripper (Colfax)" },
{ 15, -1, -1, 23, 8, -1, -1, -1, NC, RYZEN_|_7 , 0, "Ryzen 7 (Pinnacle Ridge)" },
{ 15, -1, -1, 23, 8, -1, -1, -1, NC, RYZEN_|_5 , 0, "Ryzen 5 (Pinnacle Ridge)" },
{ 15, -1, -1, 23, 8, -1, -1, -1, NC, RYZEN_|_3 , 0, "Ryzen 3 (Pinnacle Ridge)" },
{ 15, -1, -1, 23, 24, -1, -1, -1, NC, RYZEN_|_7 , 0, "Ryzen 7 (Picasso)" },
{ 15, -1, -1, 23, 24, -1, -1, -1, NC, RYZEN_|_5 , 0, "Ryzen 5 (Picasso)" },
{ 15, -1, -1, 23, 24, -1, -1, -1, NC, RYZEN_|_3 , 0, "Ryzen 3 (Picasso)" },
{ 15, -1, -1, 23, 24, -1, -1, -1, NC, ATHLON_ , 0, "Athlon (Picasso)" },
/* Zen 2 (2019) => https://en.wikichip.org/wiki/amd/microarchitectures/zen_2 */
{ 15, -1, -1, 23, 113, -1, -1, -1, NC, EPYC_ , 0, "EPYC (Rome)" },
{ 15, -1, -1, 23, 113, -1, -1, -1, NC, RYZEN_|_9 , 0, "Ryzen 9 (Matisse)" },
{ 15, -1, -1, 23, 113, -1, -1, -1, NC, RYZEN_|_7 , 0, "Ryzen 7 (Matisse)" },
{ 15, -1, -1, 23, 113, -1, -1, -1, NC, RYZEN_|_5 , 0, "Ryzen 5 (Matisse)" },
{ 15, -1, -1, 23, 113, -1, -1, -1, NC, RYZEN_|_3 , 0, "Ryzen 3 (Matisse)" },
//{ 15, -1, -1, 23, ??, -1, -1, -1, NC, RYZEN_|_7 , 0, "Ryzen 7 (Renoir)" }, //TBA
//{ 15, -1, -1, 23, ??, -1, -1, -1, NC, RYZEN_|_5 , 0, "Ryzen 5 (Renoir)" }, //TBA
//{ 15, -1, -1, 23, ??, -1, -1, -1, NC, RYZEN_|_3 , 0, "Ryzen 3 (Renoir)" }, //TBA
//{ 15, -1, -1, 23, ??, -1, -1, -1, NC, ATHLON_ , 0, "Athlon (Renoir)" }, //TBA
{ 15, -1, -1, 24, 0, -1, -1, -1, NC, C86_|_7 , 0, "C86 7 (Dhyana)" },
{ 15, -1, -1, 24, 0, -1, -1, -1, NC, C86_|_5 , 0, "C86 5 (Dhyana)" },
@ -473,13 +486,14 @@ static struct amd_code_and_bits_t decode_amd_codename_part1(const char *bs)
if (amd_has_turion_modelname(bs)) {
bits |= TURION_;
}
if ((i = match_pattern(bs, "Ryzen [357]")) != 0) {
if ((i = match_pattern(bs, "Ryzen [3579]")) != 0) {
bits |= RYZEN_;
i--;
switch (bs[i + 6]) {
case '3': bits |= _3; break;
case '5': bits |= _5; break;
case '7': bits |= _7; break;
case '9': bits |= _9; break;
}
}