diff --git a/libcpuid/rdmsr.c b/libcpuid/rdmsr.c index 0bb29c3..b31de43 100644 --- a/libcpuid/rdmsr.c +++ b/libcpuid/rdmsr.c @@ -646,6 +646,203 @@ static int perfmsr_measure(struct msr_driver_t* handle, int msr) return (int) ((y - x) / (b - a)); } +static int msr_platform_info_supported(struct msr_info_t *info) +{ + int i; + static int supported = -1; + + /* Return cached result */ + if(supported >= 0) + return supported; + + /* List of microarchitectures that provide both "Maximum Non-Turbo Ratio" and "Maximum Efficiency Ratio" values + Please note Silvermont does not report "Maximum Efficiency Ratio" */ + const struct { int32_t ext_family; int32_t ext_model; } msr_platform_info[] = { + /* Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture */ + { 6, 92 }, + { 6, 122 }, + /* Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture */ + { 6, 26 }, + { 6, 30 }, + { 6, 37 }, + { 6, 44 }, + /* Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture */ + { 6, 42 }, + { 6, 45 }, + /* Table 2-25. Additional MSRs Supported by 3rd Generation Intel® CoreTM Processors Based on Ivy Bridge Microarchitecture */ + { 6, 58 }, + /* Table 2-26. MSRs Supported by the Intel® Xeon® Processor E5 v2 Product Family (Ivy Bridge-E Microarchitecture) */ + { 6, 62 }, + /* Table 2-29. Additional MSRs Supported by Processors Based on the Haswell and Haswell-E Microarchitectures */ + { 6, 60 }, + { 6, 63 }, + { 6, 69 }, + { 6, 70 }, + /* Table 2-36. Additional MSRs Common to the Intel® Xeon® Processor D and the Intel® Xeon® Processor E5 v4 Family Based on Broadwell Microarchitecture */ + { 6, 61 }, + { 6, 71 }, + { 6, 79 }, + /* Table 2-39. Additional MSRs Supported by the 6th—13th Generation Intel® CoreTM Processors, 1st—5th Generation Intel® Xeon® Scalable Processor Families, Intel® CoreTM Ultra 7 Processors, 8th Generation Intel® CoreTM i3 Processors, and Intel® Xeon® E Processors */ + /* ==> Skylake */ + { 6, 78 }, + { 6, 85 }, + { 6, 94 }, + /* ==> Kaby Lake */ + { 6, 142 }, + { 6, 158 }, + /* ==> Coffee Lake */ + { 6, 102 }, + { 6, 142 }, + { 6, 158 }, + /* ==> Cascade Lake */ + { 6, 85 }, + /* ==> Comet Lake */ + { 6, 142 }, + { 6, 165 }, + /* ==> Ice Lake */ + { 6, 106 }, + { 6, 108 }, + { 6, 126 }, + /* ==> Rocket Lake */ + { 6, 167 }, + /* ==> Tremont */ + { 6, 138 }, + { 6, 150 }, + { 6, 156 }, + /* ==> Tiger Lake */ + { 6, 140 }, + /* ==> Alder Lake */ + { 6, 151 }, + { 6, 154 }, + { 6, 190 }, + /* ==> Raptor Lake */ + { 6, 183 }, + { 6, 186 }, + { 6, 191 }, + /* ==> Sapphire Rapids */ + { 6, 143 }, + /* ==> Emerald Rapids */ + { 6, 207 }, + /* ==> Meteor Lake */ + { 6, 170 }, + /* Table 2-50. MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature DisplayFamily_DisplayModel Value of 06_55H */ + { 0x6, 0x55 }, + /* Table 2-56. Selected MSRs Supported by Intel® Xeon PhiTM Processors with a CPUID Signature DisplayFamily_DisplayModel Value of 06_57H or 06_85H */ + { 0x6, 0x57 }, + { 0x6, 0x85 }, + }; + + if(info->id->vendor == VENDOR_INTEL) { + for(i = 0; i < COUNT_OF(msr_platform_info); i++) { + if((info->id->ext_family == msr_platform_info[i].ext_family) && (info->id->ext_model == msr_platform_info[i].ext_model)) { + debugf(2, "Intel CPU with CPUID signature %02X_%02XH supports MSR_PLATFORM_INFO.\n", info->id->ext_family, info->id->ext_model); + supported = 1; + return supported; + } + } + debugf(2, "Intel CPU with CPUID signature %02X_%02XH does not support MSR_PLATFORM_INFO.\n", info->id->ext_family, info->id->ext_model); + } + + supported = 0; + return supported; +} + +static int msr_temperature_target_supported(struct msr_info_t *info) +{ + /* It seems MSR_TEMPERATURE_TARGET was added with MSR_PLATFORM_INFO, i.e. since "Intel Core ix" CPUs */ + return msr_platform_info_supported(info); +} + +static int msr_perf_status_supported(struct msr_info_t *info) +{ + int i; + static int supported = -1; + + /* Return cached result */ + if(supported >= 0) + return supported; + + /* List of microarchitectures that provide "Core Voltage" values */ + const struct { int32_t ext_family; int32_t ext_model; } msr_perf_status[] = { + /* Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture */ + { 6, 42 }, + { 6, 45 }, + /* ==> Ivy Bridge */ + { 6, 58 }, + { 6, 62 }, + /* ==> Haswell */ + { 6, 60 }, + { 6, 63 }, + { 6, 69 }, + { 6, 70 }, + /* ==> Broadwell */ + { 6, 61 }, + { 6, 71 }, + { 6, 79 }, + /* ==> Skylake */ + { 6, 78 }, + { 6, 85 }, + { 6, 94 }, + /* ==> Kaby Lake */ + { 6, 142 }, + { 6, 158 }, + /* ==> Coffee Lake */ + { 6, 102 }, + { 6, 142 }, + { 6, 158 }, + /* ==> Cascade Lake */ + { 6, 85 }, + /* ==> Comet Lake */ + { 6, 142 }, + { 6, 165 }, + /* ==> Ice Lake */ + { 6, 106 }, + { 6, 108 }, + { 6, 126 }, + /* ==> Rocket Lake */ + { 6, 167 }, + /* ==> Tremont */ + { 6, 138 }, + { 6, 150 }, + { 6, 156 }, + /* ==> Tiger Lake */ + { 6, 140 }, + /* ==> Alder Lake */ + { 6, 151 }, + { 6, 154 }, + { 6, 190 }, + /* ==> Raptor Lake */ + { 6, 183 }, + { 6, 186 }, + { 6, 191 }, + /* ==> Sapphire Rapids */ + { 6, 143 }, + /* ==> Emerald Rapids */ + { 6, 207 }, + /* ==> Meteor Lake */ + { 6, 170 }, + /* Table 2-50. MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature DisplayFamily_DisplayModel Value of 06_55H */ + { 0x6, 0x55 }, + /* Table 2-56. Selected MSRs Supported by Intel® Xeon PhiTM Processors with a CPUID Signature DisplayFamily_DisplayModel Value of 06_57H or 06_85H */ + { 0x6, 0x57 }, + { 0x6, 0x85 }, + }; + + if(info->id->vendor == VENDOR_INTEL) { + for(i = 0; i < COUNT_OF(msr_perf_status); i++) { + if((info->id->ext_family == msr_perf_status[i].ext_family) && (info->id->ext_model == msr_perf_status[i].ext_model)) { + debugf(2, "Intel CPU with CPUID signature %02X_%02XH supports MSR_PERF_STATUS.\n", info->id->ext_family, info->id->ext_model); + supported = 1; + return supported; + } + } + debugf(2, "Intel CPU with CPUID signature %02X_%02XH does not support MSR_PERF_STATUS.\n", info->id->ext_family, info->id->ext_model); + } + + supported = 0; + return supported; +} + static int get_amd_multipliers(struct msr_info_t *info, uint32_t pstate, double *multiplier) { int i, err; @@ -790,7 +987,7 @@ static double get_info_min_multiplier(struct msr_info_t *info) uint32_t addr; uint64_t reg; - if(info->id->vendor == VENDOR_INTEL) { + if(msr_platform_info_supported(info)) { /* Refer links above Table 35-12. MSRs in Next Generation Intel Atom Processors Based on the Goldmont Microarchitecture Table 35-13. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem @@ -890,7 +1087,7 @@ static int get_info_temperature(struct msr_info_t *info) int err; uint64_t DigitalReadout, ReadingValid, TemperatureTarget; - if(info->id->vendor == VENDOR_INTEL) { + if(msr_temperature_target_supported(info)) { /* Refer links above Table 35-2. IA-32 Architectural MSRs IA32_THERM_STATUS[22:16] is Digital Readout @@ -918,7 +1115,7 @@ static double get_info_voltage(struct msr_info_t *info) double VIDStep; uint64_t reg, CpuVid; - if(info->id->vendor == VENDOR_INTEL) { + if(msr_perf_status_supported(info)) { /* Refer links above Table 35-18. MSRs Supported by Intel® Processors based on Intel® microarchitecture code name Sandy Bridge (Contd.) MSR_PERF_STATUS[47:32] is Core Voltage @@ -953,7 +1150,7 @@ static double get_info_bus_clock(struct msr_info_t *info) uint32_t addr; uint64_t reg; - if(info->id->vendor == VENDOR_INTEL) { + if(msr_platform_info_supported(info)) { /* Refer links above Table 35-12. MSRs in Next Generation Intel Atom Processors Based on the Goldmont Microarchitecture Table 35-13. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem