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Add support for ARMv9.5-A CPUs

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New AArch64 registers:
- ID_AA64DFR2_EL1
- ID_AA64FPFR0_EL1
- ID_AA64ISAR3_EL1
This commit is contained in:
The Tumultuous Unicorn Of Darkness 2025-05-01 15:21:29 +02:00
parent 9333f8c0c3
commit ae5b2a24c9
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GPG key ID: 1E55EE2EFF18BC1A
11 changed files with 365 additions and 15 deletions
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2
tests/arm/armv8a/cortex-a53.test
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@ -86,4 +86,4 @@ efficiency
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Apollo
28-10 nm
advsimd crc32 doublelock fp bbm
advsimd crc32 doublelock fp bbm e2h0

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tests/arm/armv8a/cortex-a57.test
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@ -86,4 +86,4 @@ performance
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Atlas
28-14 nm
advsimd crc32 doublelock fp pmull sha1 sha256 bbm
advsimd crc32 doublelock fp pmull sha1 sha256 bbm e2h0

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tests/arm/armv9a/neoverse-n2.test
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@ -86,4 +86,4 @@ general
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Perseus
5 nm
advsimd crc32 doublelock pmull sha1 lse rdm fp16 i8mm sha3 sha512 sm3 sm4 sve fcma fpaccombine jscvt pacqarma5 pauth bbm dit dotprod fhm lrcpc2 lse2 bti dpb2 frintts flagm2 mte rng sb ssbs2 bf16 dgh sve2 sve_bitperm sve_pmull128 sve_sha3 sve_sm4
advsimd crc32 doublelock pmull sha1 lse rdm fp16 i8mm sha3 sha512 sm3 sm4 sve fcma fpaccombine jscvt pacqarma5 pauth bbm dit dotprod fhm lrcpc2 lse2 bti dpb2 frintts flagm2 mte rng sb ssbs2 bf16 dgh sve2 sve_bitperm sve_pmull128 sve_sha3 sve_sm4 e2h0

2
tests/create_test.py
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@ -14,7 +14,7 @@ def readRawFile():
"basic_cpuid", "ext_cpuid", "intel_fn4", "intel_fn11", "amd_fn8000001dh", # x86
"arm_midr", "arm_mpidr", "arm_revidr", # ARM common
"arm_id_afr", "arm_id_dfr", "arm_id_isar", "arm_id_mmfr", "arm_id_pfr", # ARM (AArch32)
"arm_id_aa64afr", "arm_id_aa64dfr", "arm_id_aa64isar", "arm_id_aa64mmfr", "arm_id_aa64pfr", "arm_id_aa64smfr", "arm_id_aa64zfr" # ARM (AArch64)
"arm_id_aa64afr", "arm_id_aa64dfr", "arm_id_aa64fpfr", "arm_id_aa64isar", "arm_id_aa64mmfr", "arm_id_aa64pfr", "arm_id_aa64smfr", "arm_id_aa64zfr" # ARM (AArch64)
]
ignore = ["MSR Register"]
good = False