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Fix SSE unit size for Zen 2 CPUs

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Related to #125
This commit is contained in:
Xorg 2019-07-11 22:29:27 +02:00
parent 5aedd53624
commit bf7f57f519
2 changed files with 12 additions and 3 deletions
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13
libcpuid/recog_amd.c
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@ -344,9 +344,18 @@ static void load_amd_features(struct cpu_raw_data_t* raw, struct cpu_id_t* data)
if (raw->ext_cpuid[0][0] >= 0x80000007)
match_features(matchtable_edx87, COUNT_OF(matchtable_edx87), raw->ext_cpuid[7][3], data);
if (raw->ext_cpuid[0][0] >= 0x8000001a) {
/* We have the extended info about SSE unit size */
/* We have the extended info about SSE unit size
Extracted from BKDG, about CPUID_Fn8000001A_EAX [Performance Optimization Identifiers] (Core::X86::Cpuid::PerfOptId):
- bit 2: FP256
- bit 1: MOVU
- bit 0: FP128 */
data->detection_hints[CPU_HINT_SSE_SIZE_AUTH] = 1;
data->sse_size = (raw->ext_cpuid[0x1a][0] & 1) ? 128 : 64;
if ((raw->ext_cpuid[0x1a][0] >> 2) & 1)
data->sse_size = 256;
else if ((raw->ext_cpuid[0x1a][0]) & 1)
data->sse_size = 128;
else
data->sse_size = 64;
}
}

2
tests/amd/zen2/ryzen5-matisse.test
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@ -73,6 +73,6 @@ ext_cpuid[31]=0001000f 0000016f 000001fd 00000001
64
64
-1
64 (authoritative)
256 (authoritative)
Ryzen 5 (Matisse)
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd hwpstate constant_tsc fma3 f16c rdrand cpb aperfmperf avx2 bmi1 bmi2