1
0
Fork 0
mirror of https://github.com/anrieff/libcpuid synced 2024-11-10 22:59:13 +00:00

DB: add Renoir APUs

This commit is contained in:
Xorg 2020-05-09 15:57:56 +02:00
parent 8720a71b35
commit c854176478
No known key found for this signature in database
GPG key ID: 1E55EE2EFF18BC1A

View file

@ -289,11 +289,11 @@ const struct match_entry_t cpudb_amd[] = {
{ 15, -1, -1, 23, 113, -1, -1, -1, NC, RYZEN_|_7 , 0, "Ryzen 7 (Matisse)" }, { 15, -1, -1, 23, 113, -1, -1, -1, NC, RYZEN_|_7 , 0, "Ryzen 7 (Matisse)" },
{ 15, -1, -1, 23, 113, -1, -1, -1, NC, RYZEN_|_5 , 0, "Ryzen 5 (Matisse)" }, { 15, -1, -1, 23, 113, -1, -1, -1, NC, RYZEN_|_5 , 0, "Ryzen 5 (Matisse)" },
{ 15, -1, -1, 23, 113, -1, -1, -1, NC, RYZEN_|_3 , 0, "Ryzen 3 (Matisse)" }, { 15, -1, -1, 23, 113, -1, -1, -1, NC, RYZEN_|_3 , 0, "Ryzen 3 (Matisse)" },
// F M S EF EM #cores L2$ L3$ BC ModelBits ModelCode Name { 15, -1, -1, 23, 96, -1, -1, -1, NC, RYZEN_|_9 , 0, "Ryzen 9 (Renoir)" },
//{ 15, -1, -1, 23, ??, -1, -1, -1, NC, RYZEN_|_7 , 0, "Ryzen 7 (Renoir)" }, //TBA { 15, -1, -1, 23, 96, -1, -1, -1, NC, RYZEN_|_7 , 0, "Ryzen 7 (Renoir)" },
//{ 15, -1, -1, 23, ??, -1, -1, -1, NC, RYZEN_|_5 , 0, "Ryzen 5 (Renoir)" }, //TBA { 15, -1, -1, 23, 96, -1, -1, -1, NC, RYZEN_|_5 , 0, "Ryzen 5 (Renoir)" },
//{ 15, -1, -1, 23, ??, -1, -1, -1, NC, RYZEN_|_3 , 0, "Ryzen 3 (Renoir)" }, //TBA { 15, -1, -1, 23, 96, -1, -1, -1, NC, RYZEN_|_3 , 0, "Ryzen 3 (Renoir)" },
//{ 15, -1, -1, 23, ??, -1, -1, -1, NC, ATHLON_ , 0, "Athlon (Renoir)" }, //TBA /* F M S EF EM #cores L2$ L3$ BC ModelBits ModelCode Name */
{ 15, -1, -1, 24, 0, -1, -1, -1, NC, C86_|_7 , 0, "C86 7 (Dhyana)" }, { 15, -1, -1, 24, 0, -1, -1, -1, NC, C86_|_7 , 0, "C86 7 (Dhyana)" },
{ 15, -1, -1, 24, 0, -1, -1, -1, NC, C86_|_5 , 0, "C86 5 (Dhyana)" }, { 15, -1, -1, 24, 0, -1, -1, -1, NC, C86_|_5 , 0, "C86 5 (Dhyana)" },