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https://github.com/anrieff/libcpuid
synced 2024-12-16 16:35:45 +00:00
Imrove cpu_rdmsr_range(), make header similar to cpu_rdmsr()
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b5e82df407
commit
c9926ab6f7
3 changed files with 25 additions and 32 deletions
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@ -635,6 +635,7 @@ const char* cpuid_error(void)
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{ ERR_INVMSR , "Invalid MSR"},
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{ ERR_INVMSR , "Invalid MSR"},
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{ ERR_INVCNB , "Invalid core number"},
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{ ERR_INVCNB , "Invalid core number"},
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{ ERR_HANDLE_R , "Error on handle read"},
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{ ERR_HANDLE_R , "Error on handle read"},
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{ ERR_INVRANGE , "Invalid given range"},
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};
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};
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unsigned i;
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unsigned i;
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for (i = 0; i < COUNT_OF(matchtable); i++)
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for (i = 0; i < COUNT_OF(matchtable); i++)
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@ -396,6 +396,7 @@ typedef enum {
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ERR_INVMSR = -13, /*!< "Invalid MSR" */
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ERR_INVMSR = -13, /*!< "Invalid MSR" */
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ERR_INVCNB = -14, /*!< "Invalid core number" */
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ERR_INVCNB = -14, /*!< "Invalid core number" */
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ERR_HANDLE_R = -15, /*!< "Error on handle read" */
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ERR_HANDLE_R = -15, /*!< "Error on handle read" */
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ERR_INVRANGE = -16, /*!< "Invalid given range" */
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} cpu_error_t;
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} cpu_error_t;
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/**
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/**
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@ -431,43 +431,31 @@ static int get_bits_value(uint64_t val, int highbit, int lowbit)
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return (int) data;
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return (int) data;
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}
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}
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static uint64_t cpu_rdmsr_range(struct msr_driver_t* handle, uint32_t reg, unsigned int highbit,
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static int cpu_rdmsr_range(struct msr_driver_t* handle, uint32_t msr_index, uint8_t highbit,
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unsigned int lowbit, int* error_indx)
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uint8_t lowbit, uint64_t* result)
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{
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{
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uint64_t data;
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const uint8_t bits = highbit - lowbit + 1;
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int bits;
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*error_indx =0;
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if (cpu_rdmsr(handle, reg, &data)) {
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if(highbit > 63 || lowbit > highbit)
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*error_indx = 1;
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return set_error(ERR_INVRANGE);
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if(cpu_rdmsr(handle, msr_index, result))
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return set_error(ERR_HANDLE_R);
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return set_error(ERR_HANDLE_R);
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}
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bits = highbit - lowbit + 1;
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if(bits < 64)
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if (bits < 64)
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{
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{
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/* Show only part of register */
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/* Show only part of register */
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data >>= lowbit;
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*result >>= lowbit;
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data &= (1ULL << bits) - 1;
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*result &= (1ULL << bits) - 1;
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}
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}
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/* Make sure we get sign correct */
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return 0;
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if (data & (1ULL << (bits - 1)))
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{
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data &= ~(1ULL << (bits - 1));
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#pragma warning(disable: 4146)
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data = -data;
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#pragma warning(default: 4146)
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}
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*error_indx = 0;
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return (data);
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}
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}
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int cpu_msrinfo(struct msr_driver_t* handle, cpu_msrinfo_request_t which)
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int cpu_msrinfo(struct msr_driver_t* handle, cpu_msrinfo_request_t which)
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{
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{
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uint64_t r;
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uint64_t r;
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int err, error_indx, cur_clock;
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int err, cur_clock;
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static int max_clock = 0, multiplier = 0;
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static int max_clock = 0, multiplier = 0;
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static double bclk = 0.0;
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static double bclk = 0.0;
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uint64_t val;
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uint64_t val;
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@ -502,9 +490,11 @@ int cpu_msrinfo(struct msr_driver_t* handle, cpu_msrinfo_request_t which)
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if(cpuid_get_vendor() == VENDOR_INTEL)
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if(cpuid_get_vendor() == VENDOR_INTEL)
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{
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{
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if(!multiplier)
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if(!multiplier)
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multiplier = (int) cpu_rdmsr_range(handle, PLATFORM_INFO_MSR, PLATFORM_INFO_MSR_high, PLATFORM_INFO_MSR_low, &error_indx);
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cpu_rdmsr_range(handle, PLATFORM_INFO_MSR, PLATFORM_INFO_MSR_high, PLATFORM_INFO_MSR_low, &val);
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if(multiplier > 0)
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if(val > 0) {
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multiplier = (int) val;
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return multiplier * 100;
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return multiplier * 100;
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}
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}
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}
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err = cpu_rdmsr(handle, 0x198, &r);
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err = cpu_rdmsr(handle, 0x198, &r);
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if (err) return CPU_INVALID_VALUE;
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if (err) return CPU_INVALID_VALUE;
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@ -515,10 +505,10 @@ int cpu_msrinfo(struct msr_driver_t* handle, cpu_msrinfo_request_t which)
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{
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{
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// https://github.com/ajaiantilal/i7z/blob/5023138d7c35c4667c938b853e5ea89737334e92/helper_functions.c#L59
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// https://github.com/ajaiantilal/i7z/blob/5023138d7c35c4667c938b853e5ea89737334e92/helper_functions.c#L59
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val = cpu_rdmsr_range(handle, IA32_THERM_STATUS, 63, 0, &error_indx);
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cpu_rdmsr_range(handle, IA32_THERM_STATUS, 63, 0, &val);
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digital_readout = get_bits_value(val, 23, 16);
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digital_readout = get_bits_value(val, 23, 16);
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thermal_status = get_bits_value(val, 32, 31);
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thermal_status = get_bits_value(val, 32, 31);
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val = cpu_rdmsr_range(handle, IA32_TEMPERATURE_TARGET, 63, 0, &error_indx);
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cpu_rdmsr_range(handle, IA32_TEMPERATURE_TARGET, 63, 0, &val);
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PROCHOT_temp = get_bits_value(val, 23, 16);
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PROCHOT_temp = get_bits_value(val, 23, 16);
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// These bits are thermal status : 1 if supported, 0 else
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// These bits are thermal status : 1 if supported, 0 else
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@ -532,7 +522,7 @@ int cpu_msrinfo(struct msr_driver_t* handle, cpu_msrinfo_request_t which)
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{
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{
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if(cpuid_get_vendor() == VENDOR_INTEL)
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if(cpuid_get_vendor() == VENDOR_INTEL)
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{
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{
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uint64_t val = cpu_rdmsr_range(handle, MSR_PERF_STATUS, 47, 32, &error_indx);
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cpu_rdmsr_range(handle, MSR_PERF_STATUS, 47, 32, &val);
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double ret = (double) val / (1 << 13);
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double ret = (double) val / (1 << 13);
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return (ret > 0) ? (int) (ret * 100) : CPU_INVALID_VALUE;
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return (ret > 0) ? (int) (ret * 100) : CPU_INVALID_VALUE;
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}
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}
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@ -541,9 +531,10 @@ int cpu_msrinfo(struct msr_driver_t* handle, cpu_msrinfo_request_t which)
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/* http://support.amd.com/TechDocs/42301_15h_Mod_00h-0Fh_BKDG.pdf
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/* http://support.amd.com/TechDocs/42301_15h_Mod_00h-0Fh_BKDG.pdf
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MSRC001_0063[2:0] = CurPstate
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MSRC001_0063[2:0] = CurPstate
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MSRC001_00[6B:64][15:9] = CpuVid */
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MSRC001_00[6B:64][15:9] = CpuVid */
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uint64_t CurPstate = cpu_rdmsr_range(handle, MSR_PSTATE_S, 2, 0, &error_indx);
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uint64_t CpuVid;
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if(0 <= CurPstate && CurPstate <= 7) { // Support 8 P-states
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cpu_rdmsr_range(handle, MSR_PSTATE_S, 2, 0, &val);
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uint64_t CpuVid = cpu_rdmsr_range(handle, MSR_PSTATE_0 + CurPstate, 15, 9, &error_indx);
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if(0 <= val && val <= 7) { // Support 8 P-states
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cpu_rdmsr_range(handle, MSR_PSTATE_0 + val, 15, 9, &CpuVid);
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return (int) (1.550 - 0.0125 * CpuVid) * 100; // 2.4.1.6.3 - Serial VID (SVI) Encodings
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return (int) (1.550 - 0.0125 * CpuVid) * 100; // 2.4.1.6.3 - Serial VID (SVI) Encodings
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}
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}
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}
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}
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