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Add basic support for Centaur CPUs (VIA/Zhaoxin)

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The Tumultuous Unicorn Of Darkness 2023-07-01 16:01:26 +02:00
commit d4461a9b5f
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GPG key ID: 1E55EE2EFF18BC1A
29 changed files with 2023 additions and 11 deletions

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@ -1,7 +1,8 @@
set(cpuid_sources
cpuid_main.c
recog_intel.c
recog_amd.c
recog_centaur.c
recog_intel.c
rdtsc.c
libcpuid_util.c
rdmsr.c

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@ -8,8 +8,9 @@ libcpuid_la_LDFLAGS = \
-no-undefined -version-info @LIBCPUID_VERSION_INFO@
libcpuid_la_SOURCES = \
cpuid_main.c \
recog_intel.c \
recog_amd.c \
recog_centaur.c \
recog_intel.c \
rdtsc.c \
asm-bits.c \
libcpuid_util.c \
@ -34,8 +35,9 @@ noinst_HEADERS = \
intel_code_t.h \
libcpuid_internal.h \
libcpuid_util.h \
recog_intel.h \
recog_amd.h \
recog_centaur.h \
recog_intel.h \
rdtsc.h
EXTRA_DIST += libcpuid.sym libcpuid_vc71.vcproj libcpuid_vc10.vcxproj libcpuid_vc10.vcxproj.filters

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@ -6,7 +6,7 @@ ASM = ml64 /nologo
CC = cl.exe /nologo /TC
OPTFLAGS = /MT
DEFINES = /D "VERSION=\"0.6.3\""
OBJECTS = masm-x64.obj asm-bits.obj cpuid_main.obj libcpuid_util.obj recog_amd.obj recog_intel.obj rdtsc.obj
OBJECTS = masm-x64.obj asm-bits.obj cpuid_main.obj libcpuid_util.obj recog_amd.obj recog_centaur.obj recog_intel.obj rdtsc.obj
libcpuid.lib: $(OBJECTS)
lib /nologo /MACHINE:AMD64 /out:libcpuid.lib $(OBJECTS) bufferoverflowU.lib
@ -26,6 +26,9 @@ libcpuid_util.obj: libcpuid_util.c
recog_amd.obj: recog_amd.c
$(CC) $(OPTFLAGS) $(DEFINES) /c recog_amd.c
recog_centaur.obj: recog_centaur.c
$(CC) $(OPTFLAGS) $(DEFINES) /c recog_centaur.c
recog_intel.obj: recog_intel.c
$(CC) $(OPTFLAGS) $(DEFINES) /c recog_intel.c

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@ -13,7 +13,7 @@ all: libcpuid.lib
CC = cl.exe /nologo /TC
OPTFLAGS = /MT
DEFINES = /D "VERSION=\"0.6.3\""
OBJECTS = asm-bits.obj cpuid_main.obj libcpuid_util.obj recog_amd.obj recog_intel.obj rdtsc.obj
OBJECTS = asm-bits.obj cpuid_main.obj libcpuid_util.obj recog_amd.obj recog_centaur.obj recog_intel.obj rdtsc.obj
libcpuid.lib: $(OBJECTS)
lib /nologo /out:libcpuid.lib $(OBJECTS)
@ -30,6 +30,9 @@ libcpuid_util.obj: libcpuid_util.c
recog_amd.obj: recog_amd.c
$(CC) $(OPTFLAGS) $(DEFINES) /c recog_amd.c
recog_centaur.obj: recog_centaur.c
$(CC) $(OPTFLAGS) $(DEFINES) /c recog_centaur.c
recog_intel.obj: recog_intel.c
$(CC) $(OPTFLAGS) $(DEFINES) /c recog_intel.c

32
libcpuid/centaur_code_t.h Normal file
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@ -0,0 +1,32 @@
/*
* Copyright 2023 Veselin Georgiev,
* anrieffNOSPAM @ mgail_DOT.com (convert to gmail)
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* This file contains a list of internal codes we use in detection. It is
* of no external use and isn't a complete list of Centaur products.
*/
CODE2(VIA, 3000),
CODE(ZHAOXIN),

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@ -25,8 +25,9 @@
*/
#include "libcpuid.h"
#include "libcpuid_internal.h"
#include "recog_intel.h"
#include "recog_amd.h"
#include "recog_centaur.h"
#include "recog_intel.h"
#include "asm-bits.h"
#include "libcpuid_util.h"
#ifdef HAVE_CONFIG_H
@ -1138,6 +1139,9 @@ int cpu_ident_internal(struct cpu_raw_data_t* raw, struct cpu_id_t* data, struct
case VENDOR_HYGON:
r = cpuid_identify_amd(raw, data, internal);
break;
case VENDOR_CENTAUR:
r = cpuid_identify_centaur(raw, data, internal);
break;
default:
break;
}
@ -1684,7 +1688,7 @@ void cpuid_get_cpu_list(cpu_vendor_t vendor, struct cpu_list_t* list)
make_list_from_string("UMC x86 CPU", list);
break;
case VENDOR_CENTAUR:
make_list_from_string("VIA C3,VIA C7,VIA Nano", list);
cpuid_get_list_centaur(list);
break;
case VENDOR_RISE:
make_list_from_string("Rise mP6", list);

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@ -115,6 +115,10 @@ SOURCE=.\recog_amd.c
SOURCE=.\recog_intel.c
# End Source File
# Begin Source File
SOURCE=.\recog_centaur.c
# End Source File
# End Group
# Begin Group "Header Files"
@ -149,6 +153,10 @@ SOURCE=.\recog_amd.h
# End Source File
# Begin Source File
SOURCE=.\recog_centaur.h
# End Source File
# Begin Source File
SOURCE=.\recog_intel.h
# End Source File
# End Group

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@ -55,6 +55,11 @@ enum _amd_code_t {
};
typedef enum _amd_code_t amd_code_t;
enum _centaur_code_t {
#include "centaur_code_t.h"
};
typedef enum _centaur_code_t centaur_code_t;
enum _intel_code_t {
#include "intel_code_t.h"
};
@ -64,8 +69,9 @@ typedef enum _intel_code_t intel_code_t;
struct internal_id_info_t {
union {
amd_code_t amd;
intel_code_t intel;
amd_code_t amd;
centaur_code_t centaur;
intel_code_t intel;
} code;
uint64_t bits;
int score; // detection (matchtable) score
@ -161,6 +167,29 @@ enum _amd_bits_t {
};
typedef enum _amd_bits_t amd_bits_t;
enum _via_bits_t {
SAMUEL_ = LBIT( 10 ),
EZRA_ = LBIT( 11 ),
NEHEMIAH_ = LBIT( 12 ),
ESTHER_ = LBIT( 13 ),
EDEN_ = LBIT( 14 ),
CNA_ = LBIT( 15 ),
NANO_ = LBIT( 16 ),
QUADCORE_ = LBIT( 17 ),
};
typedef enum _via_bits_t via_bits_t;
enum _zhaoxin_bits_t {
KAISHENG_ = LBIT( 10 ),
KAIXIAN_ = LBIT( 11 ),
_KH_ = LBIT( 12 ),
_KX_ = LBIT( 13 ),
_ZX_ = LBIT( 14 ),
_C = LBIT( 15 ),
_D = LBIT( 16 ),
_E = LBIT( 17 ),
};
typedef enum _zhaoxin_bits_t zhaoxin_bits_t;
int cpu_ident_internal(struct cpu_raw_data_t* raw, struct cpu_id_t* data,

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@ -190,6 +190,7 @@
<ClCompile Include="rdmsr.c" />
<ClCompile Include="rdtsc.c" />
<ClCompile Include="recog_amd.c" />
<ClCompile Include="recog_centaur.c" />
<ClCompile Include="recog_intel.c" />
</ItemGroup>
<ItemGroup>
@ -199,6 +200,7 @@
<ClInclude Include="libcpuid_types.h" />
<ClInclude Include="libcpuid_util.h" />
<ClInclude Include="recog_amd.h" />
<ClInclude Include="recog_centaur.h" />
<ClInclude Include="recog_intel.h" />
<ClInclude Include="rdtsc.h" />
</ItemGroup>
@ -213,4 +215,4 @@
<ImportGroup Label="ExtensionTargets">
<Import Project="$(VCTargetsPath)\BuildCustomizations\masm.targets" />
</ImportGroup>
</Project>
</Project>

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@ -30,6 +30,9 @@
<ClCompile Include="recog_amd.c">
<Filter>Source Files</Filter>
</ClCompile>
<ClCompile Include="recog_centaur.c">
<Filter>Source Files</Filter>
</ClCompile>
<ClCompile Include="recog_intel.c">
<Filter>Source Files</Filter>
</ClCompile>
@ -59,6 +62,9 @@
<ClInclude Include="recog_amd.h">
<Filter>Header Files</Filter>
</ClInclude>
<ClInclude Include="recog_centaur.h">
<Filter>Header Files</Filter>
</ClInclude>
<ClInclude Include="recog_intel.h">
<Filter>Header Files</Filter>
</ClInclude>
@ -71,4 +77,4 @@
<Filter>Source Files</Filter>
</MASM>
</ItemGroup>
</Project>
</Project>

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@ -170,6 +170,9 @@
<File
RelativePath=".\recog_amd.c">
</File>
<File
RelativePath=".\recog_centaur.c">
</File>
<File
RelativePath=".\recog_intel.c">
</File>
@ -208,6 +211,9 @@
<File
RelativePath=".\recog_amd.h">
</File>
<File
RelativePath=".\recog_centaur.h">
</File>
<File
RelativePath=".\recog_intel.h">
</File>

240
libcpuid/recog_centaur.c Normal file
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@ -0,0 +1,240 @@
/*
* Copyright 2023 Veselin Georgiev,
* anrieffNOSPAM @ mgail_DOT.com (convert to gmail)
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdio.h>
#include <string.h>
#include <ctype.h>
#include "libcpuid.h"
#include "libcpuid_util.h"
#include "libcpuid_internal.h"
#include "recog_centaur.h"
const struct centaur_code_str { centaur_code_t code; char *str; } centaur_code_str[] = {
#define CODE(x) { x, #x }
#define CODE2(x, y) CODE(x)
#include "centaur_code_t.h"
#undef CODE
};
typedef struct {
int code;
uint64_t bits;
} centaur_code_and_bits_t;
enum _centaur_model_t {
UNKNOWN = -1,
_4000 = 100, /* Zhaoxin KaiXian (KX) / KaisHeng (KH) Zhangjiang */
_5000, /* Zhaoxin KaiXian (KX) WuDaoKou */
_6000, /* Zhaoxin KaiXian (KX) LuJiaZui */
_7000, /* Zhaoxin KaiXian (KX) Yongfeng */
_20000 = 1000, /* Zhaoxin KaisHeng (KH) WuDaoKou */
_30000, /* Zhaoxin KaisHeng (KH) LuJiaZui */
_40000, /* Zhaoxin KaisHeng (KH) Yongfeng */
};
typedef enum _centaur_model_t centaur_model_t;
const struct match_entry_t cpudb_centaur[] = {
// F M S EF EM #cores L2$ L3$ BC ModelBits ModelCode Name
{ -1, -1, -1, -1, -1, -1, -1, -1, NC, 0, 0, "Unknown Centaur CPU" },
// F M S EF EM #cores L2$ L3$ BC ModelBits ModelCode Name
/* VIA */
// F M S EF EM #cores L2$ L3$ BC ModelBits ModelCode Name
{ 6, -1, -1, -1, -1, -1, -1, -1, VIA, 0 , 0, "Unknown VIA CPU" },
/* Samuel (2000, 180 nm) */
{ 6, 6, -1, -1, -1, -1, -1, -1, VIA, SAMUEL_ , 0, "VIA Cyrix III (Samuel)" },
/* Samuel 2 (2001, 150 nm) */
{ 6, 7, -1, -1, -1, -1, -1, -1, VIA, SAMUEL_ , 0, "VIA C3 (Samuel 2)" },
/* Ezra (2001, 130 nm) */
{ 6, 7, -1, -1, -1, -1, -1, -1, VIA, EZRA_ , 0, "VIA C3 (Ezra)" },
{ 6, 8, -1, -1, -1, -1, -1, -1, VIA, EZRA_ , 0, "VIA C3 (Ezra-T)" },
/* Nehemiah (2003, 130 nm) */
{ 6, 9, -1, -1, -1, -1, -1, -1, VIA, NEHEMIAH_ , 0, "VIA C3 (Nehemiah)" },
/* Esther (2005, 90 nm) */
{ 6, 10, -1, -1, -1, -1, -1, -1, VIA, ESTHER_ , 0, "VIA C7 (Esther)" },
{ 6, 13, -1, -1, -1, -1, -1, -1, VIA, ESTHER_ , 0, "VIA C7-M (Esther)" },
/* Isaiah (2008, 65 nm) */
{ 6, 15, -1, -1, -1, -1, -1, -1, VIA, CNA_ , 0, "VIA Nano (Isaiah)" },
{ 6, 15, -1, -1, -1, 1, -1, -1, VIA, NANO_ , 0, "VIA Nano (Isaiah)" },
{ 6, 15, -1, -1, -1, 2, -1, -1, VIA, NANO_ , 0, "VIA Nano X2 (Isaiah)" },
{ 6, 15, -1, -1, -1, -1, -1, -1, VIA, QUADCORE_ , 0, "VIA Nano X4 (Isaiah)" },
{ 6, 15, -1, -1, -1, 4, -1, -1, VIA, EDEN_ , 0, "VIA Eden X4 (Isaiah)" },
// F M S EF EM #cores L2$ L3$ BC ModelBits ModelCode Name
/* Zhaoxin */
// F M S EF EM #cores L2$ L3$ BC ModelBits ModelCode Name
{ 7, -1, -1, -1, -1, -1, -1, -1, ZHAOXIN, 0 , 0, "Unknown Zhaoxin CPU" },
/* Zhangjiang (2015, 28 nm) */
{ 7, -1, -1, -1, 15, -1, -1, -1, ZHAOXIN, KAISHENG_|_KH_|_C, 0, "Zhaoxin KaisHeng (ZhangJiang)" }, // C+ (4000)
{ 7, -1, -1, -1, 15, -1, -1, -1, ZHAOXIN, KAIXIAN_|_ZX_|_C , 0, "Zhaoxin KaiXian (ZhangJiang)" }, // C/C+ (4000)
/* WuDaoKou (2017, 28 nm) */
{ 7, -1, -1, -1, 27, -1, -1, -1, ZHAOXIN, KAISHENG_|_KH_ , _20000, "Zhaoxin KaisHeng (WuDaoKou)" }, // KH (20000)
{ 7, -1, -1, -1, 27, -1, -1, -1, ZHAOXIN, KAIXIAN_|_KX_ , _5000, "Zhaoxin KaiXian (WuDaoKou)" }, // KX (5000)
/* LuJiaZui (2019, 16 nm) */
{ 7, -1, -1, -1, 59, -1, -1, -1, ZHAOXIN, KAISHENG_|_KH_ , _30000, "Zhaoxin KaisHeng (LuJiaZui)" }, // KH (30000)
{ 7, -1, -1, -1, 59, -1, -1, -1, ZHAOXIN, KAIXIAN_|_KX_ , _6000, "Zhaoxin KaiXian (LuJiaZui)" }, // KX (6000)
/* Yongfeng (2022, 16 nm) */
{ 7, -1, -1, -1, 91, -1, -1, -1, ZHAOXIN, KAISHENG_|_KH_ , _40000, "Zhaoxin KaisHeng (Yongfeng)" }, // KH (40000)
{ 7, -1, -1, -1, 91, -1, -1, -1, ZHAOXIN, KAIXIAN_|_KX_ , _7000, "Zhaoxin KaiXian (Yongfeng)" }, // KX (7000)
// F M S EF EM #cores L2$ L3$ BC ModelBits ModelCode Name
};
static centaur_code_and_bits_t get_brand_code_and_bits(struct cpu_id_t* data)
{
centaur_code_t code = (centaur_code_t) NC;
centaur_code_and_bits_t result;
uint64_t bits = 0;
int i = 0;
const char* bs = data->brand_str;
const struct { centaur_code_t c; const char *search; } code_matchtable[] = {
{ VIA, "VIA" },
{ ZHAOXIN, "ZHAOXIN" },
};
const struct { uint64_t bit; const char* search; } bit_matchtable_via[] = {
{ SAMUEL_, "Samuel" },
{ EZRA_, "Ezra" },
{ NEHEMIAH_, "Nehemiah" },
{ ESTHER_, "Esther" },
{ EDEN_, "Eden" },
{ CNA_, "CNA" },
{ NANO_, "Nano" },
{ QUADCORE_, "QuadCore" },
};
const struct { uint64_t bit; const char* search; } bit_matchtable_zhaoxin[] = {
{ KAISHENG_, "KaisHeng" },
{ KAIXIAN_, "KaiXian" },
{ _KH_, "KH" },
{ _KX_, "KX" },
{ _ZX_, "ZX" },
{ _C, "-C" },
{ _D, "-D" },
{ _E, "-E" },
};
for (i = 0; i < COUNT_OF(code_matchtable); i++) {
if (match_pattern(bs, code_matchtable[i].search)) {
code = code_matchtable[i].c;
break;
}
}
if (code == VIA) {
for (i = 0; i < COUNT_OF(bit_matchtable_via); i++) {
if (match_pattern(bs, bit_matchtable_via[i].search))
bits |= bit_matchtable_via[i].bit;
}
}
else if (code == ZHAOXIN) {
for (i = 0; i < COUNT_OF(bit_matchtable_zhaoxin); i++) {
if (match_pattern(bs, bit_matchtable_zhaoxin[i].search))
bits |= bit_matchtable_zhaoxin[i].bit;
}
}
result.code = code;
result.bits = bits;
return result;
}
static centaur_model_t get_model_code(struct cpu_id_t* data, centaur_code_and_bits_t brand)
{
int i = 0;
int l = (int) strlen(data->brand_str);
const char *bs = data->brand_str;
if (brand.code == ZHAOXIN) {
if ((i = match_pattern(bs, "KaiSheng KH-")) != 0) {
i += 11;
if (i + 4 >= l) return UNKNOWN;
switch(bs[i]) {
case '2': return _20000;
case '3': return _30000;
case '4': return _40000;
default: return UNKNOWN;
}
}
else if ((i = match_pattern(bs, "KaiXian KX-")) != 0) {
i += 10;
if (bs[i] == 'U') i++;
if (i + 3 >= l) return UNKNOWN;
switch(bs[i]) {
case '4': return _4000;
case '5': return _5000;
case '6': return _6000;
case '7': return _7000;
default: return UNKNOWN;
}
}
}
return UNKNOWN;
}
int cpuid_identify_centaur(struct cpu_raw_data_t* raw, struct cpu_id_t* data, struct internal_id_info_t* internal)
{
centaur_code_and_bits_t brand;
centaur_model_t model_code;
int i;
char* brand_code_str = NULL;
if (raw->basic_cpuid[0][EAX] >= 4)
decode_deterministic_cache_info_x86(raw->intel_fn4, MAX_INTELFN4_LEVEL, data, internal);
decode_number_of_cores_x86(raw, data);
brand = get_brand_code_and_bits(data);
model_code = get_model_code(data, brand);
for (i = 0; i < COUNT_OF(centaur_code_str); i++) {
if (brand.code == centaur_code_str[i].code) {
brand_code_str = centaur_code_str[i].str;
break;
}
}
if (brand_code_str)
debugf(2, "Detected Centaur brand code: %d (%s)\n", brand.code, brand_code_str);
else
debugf(2, "Detected Centaur brand code: %d\n", brand.code);
if (brand.bits) {
debugf(2, "Detected Centaur bits: ");
debug_print_lbits(2, brand.bits);
}
debugf(2, "Detected Centaur model code: %d\n", model_code);
internal->code.centaur = brand.code;
internal->bits = brand.bits;
internal->score = match_cpu_codename(cpudb_centaur, COUNT_OF(cpudb_centaur), data,
brand.code, brand.bits, model_code);
return 0;
}
void cpuid_get_list_centaur(struct cpu_list_t* list)
{
generic_get_cpu_list(cpudb_centaur, COUNT_OF(cpudb_centaur), list);
}

32
libcpuid/recog_centaur.h Normal file
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@ -0,0 +1,32 @@
/*
* Copyright 2023 Veselin Georgiev,
* anrieffNOSPAM @ mgail_DOT.com (convert to gmail)
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __RECOG_CENTAUR_H__
#define __RECOG_CENTAUR_H__
int cpuid_identify_centaur(struct cpu_raw_data_t* raw, struct cpu_id_t* data, struct internal_id_info_t* internal);
void cpuid_get_list_centaur(struct cpu_list_t* list);
#endif /* __RECOG_CENTAUR_H__ */