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mirror of https://github.com/anrieff/libcpuid synced 2024-11-10 22:59:13 +00:00

Add PURPOSE_LP_EFFICIENCY to cpu_purpose_t for Intel Meteor Lake

This commit is contained in:
The Tumultuous Unicorn Of Darkness 2024-04-13 16:20:48 +02:00
parent 587f2597d7
commit d9f2683aab
3 changed files with 19 additions and 10 deletions

View file

@ -1451,6 +1451,7 @@ const char* cpu_purpose_str(cpu_purpose_t purpose)
{ PURPOSE_GENERAL, "general" }, { PURPOSE_GENERAL, "general" },
{ PURPOSE_PERFORMANCE, "performance" }, { PURPOSE_PERFORMANCE, "performance" },
{ PURPOSE_EFFICIENCY, "efficiency" }, { PURPOSE_EFFICIENCY, "efficiency" },
{ PURPOSE_LP_EFFICIENCY, "low-power efficiency" },
}; };
unsigned i, n = COUNT_OF(matchtable); unsigned i, n = COUNT_OF(matchtable);
if (n != NUM_CPU_PURPOSES) { if (n != NUM_CPU_PURPOSES) {

View file

@ -158,6 +158,7 @@ typedef enum {
PURPOSE_GENERAL = 0, /*!< general purpose CPU */ PURPOSE_GENERAL = 0, /*!< general purpose CPU */
PURPOSE_PERFORMANCE, /*!< performance CPU */ PURPOSE_PERFORMANCE, /*!< performance CPU */
PURPOSE_EFFICIENCY, /*!< efficiency CPU */ PURPOSE_EFFICIENCY, /*!< efficiency CPU */
PURPOSE_LP_EFFICIENCY, /*!< low-power efficiency CPU */
NUM_CPU_PURPOSES, /*!< Valid CPU purpose ids: 0..NUM_CPU_PURPOSES - 1 */ NUM_CPU_PURPOSES, /*!< Valid CPU purpose ids: 0..NUM_CPU_PURPOSES - 1 */
} cpu_purpose_t; } cpu_purpose_t;

View file

@ -1145,9 +1145,16 @@ cpu_purpose_t cpuid_identify_purpose_intel(struct cpu_raw_data_t* raw)
if (EXTRACTS_BIT(raw->basic_cpuid[0x7][EDX], 15) == 0x1) { if (EXTRACTS_BIT(raw->basic_cpuid[0x7][EDX], 15) == 0x1) {
debugf(3, "Detected Intel CPU hybrid architecture\n"); debugf(3, "Detected Intel CPU hybrid architecture\n");
switch (EXTRACTS_BITS(raw->basic_cpuid[0x1a][EAX], 31, 24)) { switch (EXTRACTS_BITS(raw->basic_cpuid[0x1a][EAX], 31, 24)) {
case 0x20: /* Atom */ return PURPOSE_EFFICIENCY; case 0x20: /* Atom */
case 0x40: /* Core */ return PURPOSE_PERFORMANCE; /* Acccording to Ramyer M. from Intel, LP E-Cores do not have a L3 cache
default: return PURPOSE_GENERAL; https://community.intel.com/t5/Processors/Detecting-LP-E-Cores-on-Meteor-Lake-in-software/m-p/1584555/highlight/true#M70732
If sub-leaf 3 is set, it is an E-Cores.
*/
return (EXTRACTS_BITS(raw->intel_fn4[3][EAX], 31, 0)) ? PURPOSE_EFFICIENCY : PURPOSE_LP_EFFICIENCY;
case 0x40: /* Core */
return PURPOSE_PERFORMANCE;
default:
return PURPOSE_GENERAL;
} }
} }