From dc06877f4fe249049791c232f0083b6143f69f2f Mon Sep 17 00:00:00 2001 From: The Tumultuous Unicorn Of Darkness Date: Sat, 26 Apr 2025 19:46:37 +0200 Subject: [PATCH] Update match_entry_t to remove internal codes and bits Remove brand_code, model_bits and model_code fields, add a new brand sub-struct. There fields were complicated to manage, adding complex functions to make it work. amd_bits_t and intel_bits_t enums were truncated, I had to replace them with #define in 2e01aa030385cec833a5498f86a40f93acd08dc8. Some of these #define were conflicting with other C headers (ctype.h on OpenBSD, corecrt_wctype.h on Windows), that is why I wanted to get rid of it. I updated some CPU codenames meanwhile for more consistency. Fix #212. --- CMakeLists.txt | 5 - configure.ac | 1 - libcpuid/Doxyfile.in | 1 - libcpuid/Makefile.am | 4 - libcpuid/amd_code_t.h | 40 - libcpuid/centaur_code_t.h | 32 - libcpuid/check-consistency.py | 4 +- libcpuid/intel_code_t.h | 58 - libcpuid/libcpuid.dsp | 4 - libcpuid/libcpuid_ctype.h | 81 -- libcpuid/libcpuid_internal.h | 116 -- libcpuid/libcpuid_util.c | 89 +- libcpuid/libcpuid_util.h | 24 +- libcpuid/libcpuid_vc10.vcxproj | 1 - libcpuid/libcpuid_vc10.vcxproj.filters | 3 - libcpuid/libcpuid_vc71.vcproj | 12 - libcpuid/rdmsr.c | 84 +- libcpuid/recog_amd.c | 745 ++++------ libcpuid/recog_arm.c | 2 +- libcpuid/recog_centaur.c | 209 +-- libcpuid/recog_intel.c | 1273 ++++++----------- tests/amd/bobcat/brazos-zacate.test | 2 +- tests/amd/bulldozer/bald-eagle-x4.test | 2 +- tests/amd/bulldozer/godavari-x4.test | 2 +- tests/amd/bulldozer/kaveri-x4.test | 2 +- tests/amd/bulldozer/opteron-abu-dhabi.test | 2 +- tests/amd/bulldozer/opteron-interlagos.test | 2 +- tests/amd/bulldozer/vishera-x4.test | 2 +- tests/amd/bulldozer/zambezi-x3.test | 2 +- tests/amd/bulldozer/zambezi-x4.test | 2 +- tests/amd/jaguar/athlon-kabini.test | 2 +- tests/amd/jaguar/beema-x4.test | 2 +- tests/amd/jaguar/kabini-x4.test | 2 +- tests/amd/jaguar/steppe-eagle-x2.test | 2 +- tests/amd/k10/magny-cours.test | 2 +- tests/amd/zen3/ryzen7-rembrandt-r.test | 2 +- .../dhyana/{dhyana_7.test => dhyana.test} | 2 +- .../intel/ia-32/p6/yonah-core-duo-t2400.test | 2 +- .../intel/ia-32/p6/yonah-core-duo-t2600.test | 2 +- tests/intel/ia-32/p6/yonah-core-solo.test | 2 +- .../intel/x86-64/core/allendale-celeron.test | 2 +- .../x86-64/core/allendale-core-2-duo.test | 2 +- .../intel/x86-64/core/allendale-pentium.test | 2 +- .../intel/x86-64/core/conroe-core-2-duo.test | 2 +- tests/intel/x86-64/core/conroe-l-celeron.test | 2 +- .../x86-64/core/kentsfield-core-2-quad.test | 2 +- .../x86-64/core/merom-core-2-duo-2m.test | 2 +- .../x86-64/core/merom-core-2-duo-4m.test | 2 +- .../x86-64/core/penryn-core-2-duo-3m.test | 2 +- tests/intel/x86-64/core/penryn-l-celeron.test | 2 +- tests/intel/x86-64/core/penryn-pentium-m.test | 2 +- tests/intel/x86-64/core/wolfdale-celeron.test | 2 +- tests/intel/x86-64/core/wolfdale-pentium.test | 2 +- .../x86-64/core/yorkfield-core-2-quad-2m.test | 2 +- .../x86-64/core/yorkfield-core-2-quad-6m.test | 2 +- .../cypress-cove/rocket-lake-core-i7.test | 2 +- .../cypress-cove/rocket-lake-xeon-e.test | 2 +- .../golden-cove/alder-lake-h-core-i7.test | 4 +- .../golden-cove/alder-lake-h-core-i9.test | 4 +- .../golden-cove/alder-lake-hx-core-i7.test | 4 +- .../golden-cove/alder-lake-p-core-i3.test | 4 +- .../golden-cove/alder-lake-s-core-i5.test | 2 +- .../golden-cove/alder-lake-s-core-i9.test | 4 +- .../golden-cove/alder-lake-s-pentium.test | 2 +- .../golden-cove/alder-lake-u-pentium.test | 4 +- .../golden-cove/raptor-lake-s-core-i5.test | 4 +- .../sapphire-rapids-ws-xeon-w7.test | 2 +- .../sapphire-rapids-ws-xeon-w9.test | 2 +- .../x86-64/haswell/broadwell-e-core-i7.test | 2 +- .../x86-64/haswell/crystal-well-core-i7.test | 2 +- .../intel/x86-64/haswell/haswell-core-i3.test | 2 +- .../intel/x86-64/haswell/haswell-core-i5.test | 2 +- .../intel/x86-64/haswell/haswell-core-i7.test | 2 +- .../lion-cove/arrow-lake-s-core-ultra-5.test | 4 +- .../lion-cove/arrow-lake-s-core-ultra-7.test | 4 +- .../lion-cove/lunar-lake-v-core-ultra-9.test | 4 +- .../x86-64/nehalem/arrandale-core-i5.test | 2 +- .../x86-64/nehalem/arrandale-core-i7.test | 2 +- .../x86-64/nehalem/arrandale-pentium.test | 2 +- .../x86-64/nehalem/bloomfield-core-i7.test | 2 +- .../intel/x86-64/nehalem/bloomfield-xeon.test | 2 +- .../intel/x86-64/nehalem/gainestown-xeon.test | 2 +- .../x86-64/nehalem/gulftown-core-i7.test | 2 +- .../x86-64/nehalem/lynnfield-core-i5.test | 2 +- .../x86-64/nehalem/lynnfield-core-i7.test | 2 +- ...lftown-xeon.test => westmere-ep-xeon.test} | 2 +- .../emerald-rapids-sp-xeon-platinum.test | 2 +- .../raptor-cove/raptor-lake-h-core-i9.test | 4 +- .../raptor-cove/raptor-lake-p-core-i7.test | 4 +- .../raptor-cove/raptor-lake-s-core-i5.test | 4 +- .../raptor-cove/raptor-lake-s-core-i7.test | 4 +- .../raptor-cove/raptor-lake-s-core-i9.test | 4 +- .../raptor-lake-s-refresh-core-i5.test | 4 +- .../raptor-lake-s-refresh-core-i7.test | 4 +- .../raptor-lake-s-refresh-core-i9.test | 4 +- .../raptor-cove/raptor-lake-u-core-i7.test | 2 +- .../meteor-lake-h-core-ultra-5.test | 6 +- .../meteor-lake-h-core-ultra-7.test | 6 +- .../sandy-bridge/ivy-bridge-core-i3.test | 2 +- .../sandy-bridge/ivy-bridge-core-i5.test | 2 +- .../sandy-bridge/ivy-bridge-xeon-e5.test | 2 +- .../sandy-bridge/sandy-bridge-celeron.test | 2 +- .../sandy-bridge/sandy-bridge-core-i7.test | 2 +- .../sandy-bridge/sandy-bridge-e-core-i7.test | 2 +- .../sandy-bridge/sandy-bridge-e-xeon-e5.test | 2 +- .../sandy-bridge/sandy-bridge-xeon-e3.test | 2 +- .../x86-64/skylake/cannon-lake-core-i3-u.test | 2 +- .../skylake/cascade-lake-sp-xeon-gold.test | 2 +- .../cascade-lake-sp-xeon-platinum.test | 2 +- .../skylake/cascade-lake-sp-xeon-silver.test | 2 +- .../x86-64/skylake/cascade-lake-w-xeon-w.test | 2 +- .../skylake/cascade-lake-x-core-i9.test | 2 +- .../x86-64/skylake/coffee-lake-core-i7.test | 2 +- .../x86-64/skylake/comet-lake-core-i7-u.test | 2 +- .../x86-64/skylake/kaby-lake-core-i7-g.test | 2 +- .../x86-64/skylake/kaby-lake-core-i7-u.test | 2 +- .../x86-64/skylake/kaby-lake-r-core-i5.test | 2 +- .../intel/x86-64/skylake/skylake-core-i5.test | 2 +- .../x86-64/skylake/skylake-de-xeon-d.test | 2 +- .../intel/x86-64/skylake/skylake-pentium.test | 2 +- .../skylake/skylake-sp-xeon-bronze.test | 4 +- .../x86-64/skylake/skylake-sp-xeon-gold.test | 4 +- .../skylake/skylake-sp-xeon-platinum.test | 4 +- .../skylake/skylake-sp-xeon-silver.test | 4 +- ...ke-w-xeon-w.test => skylake-w-xeon-d.test} | 2 +- .../x86-64/skylake/skylake-x-core-i7.test | 2 +- .../skylake/whiskey-lake-core-i5-u.test | 2 +- .../x86-64/sunny-cove/ice-lake-d-xeon-d.test | 2 +- .../intel/x86-64/sunny-cove/ice-lake-i5.test | 2 +- .../intel/x86-64/sunny-cove/ice-lake-i7.test | 2 +- .../willow-cove/tiger-lake-core-i5.test | 2 +- .../goldmont-plus/apollo-lake-atom-x5.test | 2 +- .../goldmont-plus/gemini-lake-celeron.test | 2 +- .../gracemont/alder-lake-n-core-i3.test | 2 +- .../x86-atom/gracemont/alder-lake-n95.test | 2 +- .../gracemont/twin-lake-n-core-3.test | 2 +- .../silvermont/bay-trail-d-celeron.test | 2 +- ...e3827.test => bay-trail-i-atom-e3827.test} | 2 +- .../silvermont/bay-trail-m-celeron.test | 2 +- .../silvermont/bay-trail-t-atom-z3740.test | 2 +- .../tremont/elkhart-lake-celeron.test | 2 +- .../x86-atom/tremont/jasper-lake-celeron.test | 2 +- .../x86-atom/tremont/jasper-lake-pentium.test | 2 +- .../x86-atom/tremont/lakefield-core-i5.test | 4 +- 144 files changed, 1018 insertions(+), 2070 deletions(-) delete mode 100644 libcpuid/amd_code_t.h delete mode 100644 libcpuid/centaur_code_t.h delete mode 100644 libcpuid/intel_code_t.h delete mode 100644 libcpuid/libcpuid_ctype.h rename tests/hygon/dhyana/{dhyana_7.test => dhyana.test} (99%) rename tests/intel/x86-64/nehalem/{gulftown-xeon.test => westmere-ep-xeon.test} (99%) rename tests/intel/x86-64/skylake/{skylake-w-xeon-w.test => skylake-w-xeon-d.test} (99%) rename tests/intel/x86-atom/silvermont/{bay-trail-t-atom-e3827.test => bay-trail-i-atom-e3827.test} (99%) diff --git a/CMakeLists.txt b/CMakeLists.txt index 6b13935..ed11047 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -31,12 +31,7 @@ if(${CMAKE_SYSTEM_NAME} STREQUAL "DragonFly" OR ${CMAKE_SYSTEM_NAME} STREQUAL "N find_package(Threads REQUIRED) endif() -# check if popcount64 is available include(CheckSymbolExists) -check_symbol_exists(popcount64 "string.h" HAVE_POPCOUNT64) -if(HAVE_POPCOUNT64) - add_definitions(-DHAVE_POPCOUNT64) -endif(HAVE_POPCOUNT64) # check if auxiliary vector is available if(${CMAKE_SYSTEM_NAME} STREQUAL "Linux") diff --git a/configure.ac b/configure.ac index b726249..8c43a77 100644 --- a/configure.ac +++ b/configure.ac @@ -51,7 +51,6 @@ LT_INIT AM_CPPFLAGS="$CPPFLAGS" AC_CHECK_HEADERS([stdint.h]) -AC_CHECK_FUNCS([popcount64]) AC_CHECK_PROGS([DOXYGEN], [doxygen]) AM_CONDITIONAL([HAVE_DOXYGEN], [test -n "$DOXYGEN"]) diff --git a/libcpuid/Doxyfile.in b/libcpuid/Doxyfile.in index 8a6bebf..9bc44c4 100644 --- a/libcpuid/Doxyfile.in +++ b/libcpuid/Doxyfile.in @@ -990,7 +990,6 @@ RECURSIVE = NO # run. EXCLUDE = @top_srcdir@/libcpuid/libcpuid_internal.h \ - @top_srcdir@/libcpuid/libcpuid_ctype.h \ @top_srcdir@/libcpuid/libcpuid_util.h # The EXCLUDE_SYMLINKS tag can be used to select whether or not files or diff --git a/libcpuid/Makefile.am b/libcpuid/Makefile.am index 43f142a..fd17d55 100644 --- a/libcpuid/Makefile.am +++ b/libcpuid/Makefile.am @@ -32,12 +32,8 @@ libcpuidinclude_HEADERS = \ libcpuid_types.h noinst_HEADERS = \ - amd_code_t.h \ asm-bits.h \ - centaur_code_t.h \ - intel_code_t.h \ libcpuid_arm_driver.h \ - libcpuid_ctype.h \ libcpuid_internal.h \ libcpuid_util.h \ recog_amd.h \ diff --git a/libcpuid/amd_code_t.h b/libcpuid/amd_code_t.h deleted file mode 100644 index 106471b..0000000 --- a/libcpuid/amd_code_t.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright 2016 Veselin Georgiev, - * anrieffNOSPAM @ mgail_DOT.com (convert to gmail) - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * This file contains a list of internal codes we use in detection. It is - * of no external use and isn't a complete list of AMD products. - */ - CODE2(OPTERON_800, 1000), - CODE(PHENOM), - CODE(PHENOM2), - CODE(FUSION_C), - CODE(FUSION_E), - CODE(FUSION_EA), - CODE(FUSION_Z), - CODE(FUSION_A), - CODE(FUSION_RX), - CODE(FUSION_GX), diff --git a/libcpuid/centaur_code_t.h b/libcpuid/centaur_code_t.h deleted file mode 100644 index 5e91aad..0000000 --- a/libcpuid/centaur_code_t.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright 2023 Veselin Georgiev, - * anrieffNOSPAM @ mgail_DOT.com (convert to gmail) - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * This file contains a list of internal codes we use in detection. It is - * of no external use and isn't a complete list of Centaur products. - */ - CODE2(VIA, 3000), - CODE(ZHAOXIN), diff --git a/libcpuid/check-consistency.py b/libcpuid/check-consistency.py index 6766cd4..2cb9c6c 100755 --- a/libcpuid/check-consistency.py +++ b/libcpuid/check-consistency.py @@ -160,7 +160,7 @@ cache_exp = re.compile(r".*([\(/ ][0-9]+K).*") # - Codenames should not exceed 31 characters # - Check for common typos definitions = 0 -match_entry_fields = 12 # this number needs to change if the definition of match_entry_t ever changes +match_entry_fields = 11 # this number needs to change if the definition of match_entry_t ever changes codename_str_max = 64-1 # this number needs to change if the value of CODENAME_STR_MAX ever changes common_cache_sizes = ["8", "16", "32", "64", "128", "256", "512", "1024", "2048", "3072", "4096", "6144", "8192", "12288", "16384"] for fn in glob.glob("%s/*.c" % sys.argv[1]): @@ -177,7 +177,7 @@ for fn in glob.glob("%s/*.c" % sys.argv[1]): if not has_matchtable: continue i = line.find("{") - j = line.find("}") + j = line.rfind("}") if i == -1 or j == -1 or i > j: continue inner = line[i+1:j] diff --git a/libcpuid/intel_code_t.h b/libcpuid/intel_code_t.h deleted file mode 100644 index 41fd15d..0000000 --- a/libcpuid/intel_code_t.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright 2016 Veselin Georgiev, - * anrieffNOSPAM @ mgail_DOT.com (convert to gmail) - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * This file contains a list of internal codes we use in detection. It is - * of no external use and isn't a complete list of intel products. - */ - CODE2(PENTIUM, 2000), - - CODE(IRWIN), - CODE(POTOMAC), - CODE(GAINESTOWN), - CODE(WESTMERE), - - CODE(PENTIUM_M), - CODE(NOT_CELERON), - - CODE(CORE_SOLO), - CODE(MOBILE_CORE_SOLO), - CODE(CORE_DUO), - CODE(MOBILE_CORE_DUO), - - CODE(WOLFDALE), - CODE(MEROM), - CODE(PENRYN), - CODE(QUAD_CORE), - CODE(DUAL_CORE_HT), - CODE(QUAD_CORE_HT), - CODE(MORE_THAN_QUADCORE), - CODE(PENTIUM_D), - - CODE(SILVERTHORNE), - CODE(DIAMONDVILLE), - CODE(PINEVIEW), - CODE(CEDARVIEW), diff --git a/libcpuid/libcpuid.dsp b/libcpuid/libcpuid.dsp index f58da52..dda05b6 100644 --- a/libcpuid/libcpuid.dsp +++ b/libcpuid/libcpuid.dsp @@ -149,10 +149,6 @@ SOURCE=.\libcpuid_constants.h # End Source File # Begin Source File -SOURCE=.\libcpuid_ctype.h -# End Source File -# Begin Source File - SOURCE=.\libcpuid_internal.h # End Source File # Begin Source File diff --git a/libcpuid/libcpuid_ctype.h b/libcpuid/libcpuid_ctype.h deleted file mode 100644 index b4ac7a4..0000000 --- a/libcpuid/libcpuid_ctype.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Copyright 2024 Veselin Georgiev, - * anrieffNOSPAM @ mgail_DOT.com (convert to gmail) - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __LIBCPUID_CTYPE_H__ -#define __LIBCPUID_CTYPE_H__ -/* - * This file contains ctype.h function declarations for OS where this header cannot be included - */ - -#if defined(__OpenBSD__) -/* On OpenBSD, _common_bits_t/_intel_bits_t/_amd_bits_t from libcpuid_internal.h conflict with ctype.h */ -int isalnum(int); -int isalpha(int); -int iscntrl(int); -int isdigit(int); -int isgraph(int); -int islower(int); -int isprint(int); -int ispunct(int); -int isspace(int); -int isupper(int); -int isxdigit(int); -int tolower(int); -int toupper(int); - -# if __BSD_VISIBLE || __ISO_C_VISIBLE >= 1999 || __POSIX_VISIBLE > 200112 \ - || __XPG_VISIBLE > 600 -int isblank(int); -# endif - -# if __BSD_VISIBLE || __XPG_VISIBLE -int isascii(int); -int toascii(int); -int _tolower(int); -int _toupper(int); -# endif /* __BSD_VISIBLE || __XPG_VISIBLE */ - -# if __POSIX_VISIBLE >= 200809 -int isalnum_l(int, locale_t); -int isalpha_l(int, locale_t); -int isblank_l(int, locale_t); -int iscntrl_l(int, locale_t); -int isdigit_l(int, locale_t); -int isgraph_l(int, locale_t); -int islower_l(int, locale_t); -int isprint_l(int, locale_t); -int ispunct_l(int, locale_t); -int isspace_l(int, locale_t); -int isupper_l(int, locale_t); -int isxdigit_l(int, locale_t); -int tolower_l(int, locale_t); -int toupper_l(int, locale_t); -# endif -#else -# include -#endif - -#endif /* __LIBCPUID_CTYPE_H__ */ diff --git a/libcpuid/libcpuid_internal.h b/libcpuid/libcpuid_internal.h index 70d8248..bf743db 100644 --- a/libcpuid/libcpuid_internal.h +++ b/libcpuid/libcpuid_internal.h @@ -33,11 +33,6 @@ #define EXTRACTS_BIT(reg, bit) ((reg >> bit) & 0x1) #define EXTRACTS_BITS(reg, highbit, lowbit) ((reg >> lowbit) & ((1ULL << (highbit - lowbit + 1)) - 1)) -enum _common_codes_t { - NA = 0, - NC, /* No code */ -}; - enum _cache_type_t { L1I, L1D, @@ -48,32 +43,7 @@ enum _cache_type_t { }; typedef enum _cache_type_t cache_type_t; -#define CODE(x) x -#define CODE2(x, y) x = y -enum _amd_code_t { - #include "amd_code_t.h" -}; -typedef enum _amd_code_t amd_code_t; - -enum _centaur_code_t { - #include "centaur_code_t.h" -}; -typedef enum _centaur_code_t centaur_code_t; - -enum _intel_code_t { - #include "intel_code_t.h" -}; -typedef enum _intel_code_t intel_code_t; -#undef CODE -#undef CODE2 - struct internal_id_info_t { - union { - amd_code_t amd; - centaur_code_t centaur; - intel_code_t intel; - } code; - uint64_t bits; int score; // detection (matchtable) score int32_t cache_mask[NUM_CACHE_TYPES]; }; @@ -122,92 +92,6 @@ struct internal_type_info_array_t { struct internal_type_info_t* data; }; -#define LBIT(x) ((1ULL) << x) - -// common detection bits for CPUs: -#define _M_ LBIT( 0 ) -#define MOBILE_ LBIT( 1 ) -#define _MP_ LBIT( 2 ) -#define _3 LBIT( 3 ) -#define _5 LBIT( 4 ) -#define _7 LBIT( 5 ) -#define _9 LBIT( 6 ) -#define _H LBIT( 7 ) // powerful mobile processors for laptop -#define _S LBIT( 8 ) -#define _U LBIT( 9 ) // ultra-low power -#define _X LBIT( 10 ) // CPU with great amount of power -#define _F LBIT( 11 ) // CPU that doesn’t have integrated graphics -#define _G LBIT( 12 ) // CPU with additional built-in integrated graphics -#define _E LBIT( 13 ) // Embedded (Intel) -#define LAST_COMMON_BIT 13 - -// additional detection bits for Intel CPUs: -#define PENTIUM_ LBIT( (LAST_COMMON_BIT + 1) ) -#define CELERON_ LBIT( (LAST_COMMON_BIT + 2) ) -#define CORE_ LBIT( (LAST_COMMON_BIT + 3) ) -#define _I_ LBIT( (LAST_COMMON_BIT + 4) ) -#define XEON_ LBIT( (LAST_COMMON_BIT + 5) ) -#define ATOM_ LBIT( (LAST_COMMON_BIT + 6) ) -#define _K LBIT( (LAST_COMMON_BIT + 7) ) // an unlocked desktop processor that allows for overclocking -#define _P LBIT( (LAST_COMMON_BIT + 8) ) -#define _N LBIT( (LAST_COMMON_BIT + 9) ) -#define _W_ LBIT( (LAST_COMMON_BIT + 10) ) -#define _D_ LBIT( (LAST_COMMON_BIT + 11) ) -#define _BRONZE_ LBIT( (LAST_COMMON_BIT + 12) ) -#define _SILVER_ LBIT( (LAST_COMMON_BIT + 13) ) -#define _GOLD_ LBIT( (LAST_COMMON_BIT + 14) ) -#define _PLATINIUM_ LBIT( (LAST_COMMON_BIT + 15) ) -#define _MAX_ LBIT( (LAST_COMMON_BIT + 16) ) -#define _J_ LBIT( (LAST_COMMON_BIT + 17) ) -#define _N_ LBIT( (LAST_COMMON_BIT + 18) ) -#define _ULTRA_ LBIT( (LAST_COMMON_BIT + 19) ) -#define _V LBIT( (LAST_COMMON_BIT + 20) ) // Lunar Lake -#define _L LBIT( (LAST_COMMON_BIT + 21) ) // LGA package (UL = Power efficient, in LGA package / HL = Highest performance, in LGA package) -#define _T LBIT( (LAST_COMMON_BIT + 22) ) // Power-optimized lifestyle -#define _U_ LBIT( (LAST_COMMON_BIT + 23) ) - -// additional detection bits for AMD CPUs: -#define ATHLON_ LBIT( (LAST_COMMON_BIT + 1) ) -#define _XP_ LBIT( (LAST_COMMON_BIT + 2) ) -#define DURON_ LBIT( (LAST_COMMON_BIT + 3) ) -#define SEMPRON_ LBIT( (LAST_COMMON_BIT + 4) ) -#define OPTERON_ LBIT( (LAST_COMMON_BIT + 5) ) -#define TURION_ LBIT( (LAST_COMMON_BIT + 6) ) -#define RYZEN_ LBIT( (LAST_COMMON_BIT + 7) ) -#define RYZEN_TR_ LBIT( (LAST_COMMON_BIT + 8) ) -#define EPYC_ LBIT( (LAST_COMMON_BIT + 9) ) -#define _LV_ LBIT( (LAST_COMMON_BIT + 10) ) -#define _64_ LBIT( (LAST_COMMON_BIT + 11) ) -#define _X2 LBIT( (LAST_COMMON_BIT + 12) ) -#define _X3 LBIT( (LAST_COMMON_BIT + 13) ) -#define _X4 LBIT( (LAST_COMMON_BIT + 14) ) -#define _X6 LBIT( (LAST_COMMON_BIT + 15) ) -#define _FX LBIT( (LAST_COMMON_BIT + 16) ) -#define _APU_ LBIT( (LAST_COMMON_BIT + 17) ) -#define C86_ LBIT( (LAST_COMMON_BIT + 18) ) -#define _Z LBIT( (LAST_COMMON_BIT + 19) ) -#define _AI_ LBIT( (LAST_COMMON_BIT + 20) ) - -// additional detection bits for Via CPUs: -#define SAMUEL_ LBIT( (LAST_COMMON_BIT + 1) ) -#define EZRA_ LBIT( (LAST_COMMON_BIT + 2) ) -#define NEHEMIAH_ LBIT( (LAST_COMMON_BIT + 3) ) -#define ESTHER_ LBIT( (LAST_COMMON_BIT + 4) ) -#define EDEN_ LBIT( (LAST_COMMON_BIT + 5) ) -#define CNA_ LBIT( (LAST_COMMON_BIT + 6) ) -#define NANO_ LBIT( (LAST_COMMON_BIT + 7) ) -#define QUADCORE_ LBIT( (LAST_COMMON_BIT + 8) ) - -// additional detection bits for Zhaoxin CPUs: -#define KAISHENG_ LBIT( (LAST_COMMON_BIT + 1) ) -#define KAIXIAN_ LBIT( (LAST_COMMON_BIT + 2) ) -#define _KH_ LBIT( (LAST_COMMON_BIT + 3) ) -#define _KX_ LBIT( (LAST_COMMON_BIT + 4) ) -#define _ZX_ LBIT( (LAST_COMMON_BIT + 5) ) -#define __C LBIT( (LAST_COMMON_BIT + 6) ) -#define _D LBIT( (LAST_COMMON_BIT + 7) ) - - int cpu_ident_internal(struct cpu_raw_data_t* raw, struct cpu_id_t* data, struct internal_id_info_t* internal); diff --git a/libcpuid/libcpuid_util.c b/libcpuid/libcpuid_util.c index 1002bdc..5403be1 100644 --- a/libcpuid/libcpuid_util.c +++ b/libcpuid/libcpuid_util.c @@ -28,11 +28,11 @@ #include #include #include +#include #ifdef HAVE_CONFIG_H #include "config.h" #endif #include "libcpuid.h" -#include "libcpuid_ctype.h" #include "libcpuid_util.h" #include "libcpuid_internal.h" @@ -80,24 +80,10 @@ void debugf(int verboselevel, const char* format, ...) _warn_fun(buff); } -#ifndef HAVE_POPCOUNT64 -static unsigned int popcount64(uint64_t mask) +static int score(const struct match_entry_t* entry, const struct cpu_id_t* data) { - unsigned int num_set_bits = 0; - - while (mask) { - mask &= mask - 1; - num_set_bits++; - } - - return num_set_bits; -} -#endif - -static int score(const struct match_entry_t* entry, const struct cpu_id_t* data, - int brand_code, uint64_t bits, int model_code) -{ - int i, tmp, res = 0; + int i, res = 0; + char brand_str[BRAND_STR_MAX]; const struct { const char *field; int entry; int data; int score; } array[] = { { "family", entry->family, data->x86.family, 2 }, { "model", entry->model, data->x86.model, 2 }, @@ -107,36 +93,42 @@ static int score(const struct match_entry_t* entry, const struct cpu_id_t* data, { "ncores", entry->ncores, data->num_cores, 2 }, { "l2cache", entry->l2cache, data->l2_cache, 1 }, { "l3cache", entry->l3cache, data->l3_cache, 1 }, - { "brand_code", entry->brand_code, brand_code, 2 }, - { "model_code", entry->model_code, model_code, 2 }, }; for (i = 0; i < sizeof(array) / sizeof(array[0]); i++) { - if(array[i].entry == array[i].data) { + if ((array[i].entry >= 0) && (array[i].entry == array[i].data)) { res += array[i].score; debugf(4, "Score: %-12s matches, adding %2i (current score for this entry: %2i)\n", array[i].field, array[i].score, res); } } - tmp = popcount64(entry->model_bits & bits) * 2; - res += tmp; - debugf(4, "Score: %-12s matches, adding %2i (current score for this entry: %2i)\n", "model_bits", tmp, res); + if ((entry->brand.score > 0) && (strlen(entry->brand.pattern) > 0)) { + /* Remove useless substrings in brand_str */ + strncpy(brand_str, data->brand_str, BRAND_STR_MAX); + remove_substring(brand_str, "CPU"); + collapse_spaces(brand_str); + /* Test pattern */ + debugf(5, "Test if '%s' brand pattern matches '%s'...\n", entry->brand.pattern, brand_str); + if (match_pattern(brand_str, entry->brand.pattern)) { + res += entry->brand.score; + debugf(4, "Score: %-12s matches, adding %2i (current score for this entry: %2i)\n", "brand", entry->brand.score, res); + } + } + return res; } -int match_cpu_codename(const struct match_entry_t* matchtable, int count, - struct cpu_id_t* data, int brand_code, uint64_t bits, - int model_code) +int match_cpu_codename(const struct match_entry_t* matchtable, int count, struct cpu_id_t* data) { int bestscore = -1; int bestindex = 0; int i, t; - debugf(3, "Matching cpu f:%d, m:%d, s:%d, xf:%d, xm:%d, ncore:%d, l2:%d, bcode:%d, bits:%llu, code:%d\n", + debugf(3, "Matching cpu f:%d, m:%d, s:%d, xf:%d, xm:%d, ncore:%d, l2:%d, l3:%d\n", data->x86.family, data->x86.model, data->x86.stepping, data->x86.ext_family, - data->x86.ext_model, data->num_cores, data->l2_cache, brand_code, (unsigned long long) bits, model_code); + data->x86.ext_model, data->num_cores, data->l2_cache, data->l3_cache); for (i = 0; i < count; i++) { - t = score(&matchtable[i], data, brand_code, bits, model_code); + t = score(&matchtable[i], data); debugf(3, "Entry %d, `%s', score %d\n", i, matchtable[i].name, t); if (t > bestscore) { debugf(2, "Entry `%s' selected - best score so far (%d)\n", matchtable[i].name, t); @@ -192,7 +184,7 @@ static int xmatch_entry(char c, const char* p) { int i, j; if (c == 0) return -1; - if (c == p[0]) return 1; + if (tolower(c) == tolower(p[0])) return 1; if (p[0] == '.') return 1; if (p[0] == '#' && isdigit(c)) return 1; if (p[0] == '[') { @@ -200,7 +192,7 @@ static int xmatch_entry(char c, const char* p) while (p[j] && p[j] != ']') j++; if (!p[j]) return -1; for (i = 1; i < j; i++) - if (p[i] == c) return j + 1; + if (tolower(p[i]) == tolower(c)) return j + 1; } return -1; } @@ -224,6 +216,39 @@ int match_pattern(const char* s, const char* p) return 0; } +void remove_substring(char* string, const char* substring) +{ + size_t len; + char *pos = strstr(string, substring); + + if (pos != NULL) { + len = strlen(substring); + memmove(pos, pos + len, strlen(pos + len) + 1); + } +} + +void collapse_spaces(char* string) +{ + size_t i, j = 0; + bool in_space = false; + const size_t len = strlen(string); + + for (i = 0; i < len; i++) { + if (isspace(string[i])) { + if (!in_space) { + string[j++] = ' '; + in_space = true; + } + } + else { + string[j++] = string[i]; + in_space = false; + } + } + + string[j] = '\0'; +} + struct cpu_id_t* get_cached_cpuid(void) { static int initialized = 0; diff --git a/libcpuid/libcpuid_util.h b/libcpuid/libcpuid_util.h index 47287d1..12315d5 100644 --- a/libcpuid/libcpuid_util.h +++ b/libcpuid/libcpuid_util.h @@ -39,18 +39,20 @@ struct feature_map_t { void match_features(const struct feature_map_t* matchtable, int count, uint32_t reg, struct cpu_id_t* data); + struct match_entry_t { int family, model, stepping, ext_family, ext_model; - int ncores, l2cache, l3cache, brand_code; - uint64_t model_bits; - int model_code; + int ncores, l2cache, l3cache; + struct { + char pattern[BRAND_STR_MAX]; + int score; + } brand; char name[CODENAME_STR_MAX]; }; // returns the match score: -int match_cpu_codename(const struct match_entry_t* matchtable, int count, - struct cpu_id_t* data, int brand_code, uint64_t bits, - int model_code); + +int match_cpu_codename(const struct match_entry_t* matchtable, int count, struct cpu_id_t* data); void warnf(const char* format, ...) #ifdef __GNUC__ @@ -77,6 +79,16 @@ void generic_get_cpu_list(const struct match_entry_t* matchtable, int count, */ int match_pattern(const char* haystack, const char* pattern); +/* + * Remove a substring from a string +*/ +void remove_substring(char* string, const char* substring); + +/* + * Remove useless spaces from a string + */ +void collapse_spaces(char* string); + /* * Gets an initialized cpu_id_t. It is cached, so that internal libcpuid * machinery doesn't need to issue cpu_identify more than once. diff --git a/libcpuid/libcpuid_vc10.vcxproj b/libcpuid/libcpuid_vc10.vcxproj index 2689980..f22068b 100644 --- a/libcpuid/libcpuid_vc10.vcxproj +++ b/libcpuid/libcpuid_vc10.vcxproj @@ -200,7 +200,6 @@ - diff --git a/libcpuid/libcpuid_vc10.vcxproj.filters b/libcpuid/libcpuid_vc10.vcxproj.filters index d183a79..09433ed 100644 --- a/libcpuid/libcpuid_vc10.vcxproj.filters +++ b/libcpuid/libcpuid_vc10.vcxproj.filters @@ -62,9 +62,6 @@ Header Files - - Header Files - Header Files diff --git a/libcpuid/libcpuid_vc71.vcproj b/libcpuid/libcpuid_vc71.vcproj index 6f2bf6f..00923f2 100644 --- a/libcpuid/libcpuid_vc71.vcproj +++ b/libcpuid/libcpuid_vc71.vcproj @@ -187,18 +187,9 @@ Name="Header Files" Filter="h;hpp;hxx;hm;inl;inc;xsd" UniqueIdentifier="{93995380-89BD-4b04-88EB-625FBE52EBFB}"> - - - - - - @@ -208,9 +199,6 @@ - - diff --git a/libcpuid/rdmsr.c b/libcpuid/rdmsr.c index fa23096..e79fe77 100644 --- a/libcpuid/rdmsr.c +++ b/libcpuid/rdmsr.c @@ -765,13 +765,7 @@ static int msr_platform_info_supported(struct msr_info_t *info) return supported; } -static int msr_temperature_target_supported(struct msr_info_t *info) -{ - /* It seems MSR_TEMPERATURE_TARGET was added with MSR_PLATFORM_INFO, i.e. since "Intel Core ix" CPUs */ - return msr_platform_info_supported(info); -} - -static int msr_perf_status_supported(struct msr_info_t *info) +static int msr_intel_core_supported(struct msr_info_t *info) { int i; static int supported = -1; @@ -882,7 +876,7 @@ static int get_amd_multipliers(struct msr_info_t *info, uint32_t pstate, double /* Constant values for common families */ const int magic_constant = (info->id->x86.ext_family == 0x11) ? 0x8 : 0x10; - const int is_apu = ((FUSION_C <= info->internal->code.amd) && (info->internal->code.amd <= FUSION_A)) || (info->internal->bits & _APU_); + const int is_apu = (strstr(info->id->brand_str, "APU") != NULL) || (strstr(info->id->brand_str, "with AMD Radeon ") != NULL); const double divisor = is_apu ? 1.0 : 2.0; /* Check if P-state is valid */ @@ -1037,17 +1031,19 @@ static double get_info_cur_multiplier(struct msr_info_t *info) double mult; uint64_t reg; - if(info->id->vendor == VENDOR_INTEL && info->internal->code.intel == PENTIUM) { - err = cpu_rdmsr(info->handle, MSR_EBL_CR_POWERON, ®); - if (!err) return (double) ((reg>>22) & 0x1f); - } - else if(info->id->vendor == VENDOR_INTEL && info->internal->code.intel != PENTIUM) { - /* Refer links above - Table 35-2. IA-32 Architectural MSRs (Contd.) - IA32_PERF_STATUS[15:0] is Current performance State Value - [7:0] is 0x0, [15:8] looks like current ratio */ - err = cpu_rdmsr_range(info->handle, IA32_PERF_STATUS, 15, 8, ®); - if (!err) return (double) reg; + if(info->id->vendor == VENDOR_INTEL) { + if(!msr_intel_core_supported(info)) { + err = cpu_rdmsr(info->handle, MSR_EBL_CR_POWERON, ®); + if (!err) return (double) ((reg>>22) & 0x1f); + } + else { + /* Refer links above + Table 35-2. IA-32 Architectural MSRs (Contd.) + IA32_PERF_STATUS[15:0] is Current performance State Value + [7:0] is 0x0, [15:8] looks like current ratio */ + err = cpu_rdmsr_range(info->handle, IA32_PERF_STATUS, 15, 8, ®); + if (!err) return (double) reg; + } } else if(info->id->vendor == VENDOR_AMD || info->id->vendor == VENDOR_HYGON) { /* Refer links above @@ -1066,28 +1062,30 @@ static double get_info_max_multiplier(struct msr_info_t *info) double mult; uint64_t reg; - if(info->id->vendor == VENDOR_INTEL && info->internal->code.intel == PENTIUM) { - err = cpu_rdmsr(info->handle, IA32_PERF_STATUS, ®); - if (!err) return (double) ((reg >> 40) & 0x1f); - } - else if(info->id->vendor == VENDOR_INTEL && info->internal->code.intel != PENTIUM) { - /* Refer links above - Table 35-10. Specific MSRs Supported by Intel® Atom™ Processor C2000 Series with CPUID Signature 06_4DH - Table 35-12. MSRs in Next Generation Intel Atom Processors Based on the Goldmont Microarchitecture (Contd.) - Table 35-13. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.) - Table 35-14. Additional MSRs in Intel® Xeon® Processor 5500 and 3400 Series - Table 35-16. Additional MSRs Supported by Intel Processors (Based on Intel® Microarchitecture Code Name Westmere) - Table 35-19. MSRs Supported by 2nd Generation Intel® Core™ Processors (Intel® microarchitecture code name Sandy Bridge) - Table 35-21. Selected MSRs Supported by Intel® Xeon® Processors E5 Family (based on Sandy Bridge microarchitecture) - Table 35-28. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell microarchitecture) (Contd.) - Table 35-30. Additional MSRs Supported by Intel® Xeon® Processor E5 v3 Family - Table 35-33. Additional MSRs Supported by Intel® Core™ M Processors and 5th Generation Intel® Core™ Processors - Table 35-34. Additional MSRs Common to Intel® Xeon® Processor D and Intel Xeon Processors E5 v4 Family Based on the Broadwell Microarchitecture - Table 35-37. Additional MSRs Supported by 6th Generation Intel® Core™ Processors Based on Skylake Microarchitecture - Table 35-40. Selected MSRs Supported by Next Generation Intel® Xeon Phi™ Processors with DisplayFamily_DisplayModel Signature 06_57H - MSR_TURBO_RATIO_LIMIT[7:0] is Maximum Ratio Limit for 1C */ - err = cpu_rdmsr_range(info->handle, MSR_TURBO_RATIO_LIMIT, 7, 0, ®); - if (!err) return (double) reg; + if(info->id->vendor == VENDOR_INTEL) { + if(!msr_intel_core_supported(info)) { + err = cpu_rdmsr(info->handle, IA32_PERF_STATUS, ®); + if (!err) return (double) ((reg >> 40) & 0x1f); + } + else { + /* Refer links above + Table 35-10. Specific MSRs Supported by Intel® Atom™ Processor C2000 Series with CPUID Signature 06_4DH + Table 35-12. MSRs in Next Generation Intel Atom Processors Based on the Goldmont Microarchitecture (Contd.) + Table 35-13. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem (Contd.) + Table 35-14. Additional MSRs in Intel® Xeon® Processor 5500 and 3400 Series + Table 35-16. Additional MSRs Supported by Intel Processors (Based on Intel® Microarchitecture Code Name Westmere) + Table 35-19. MSRs Supported by 2nd Generation Intel® Core™ Processors (Intel® microarchitecture code name Sandy Bridge) + Table 35-21. Selected MSRs Supported by Intel® Xeon® Processors E5 Family (based on Sandy Bridge microarchitecture) + Table 35-28. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell microarchitecture) (Contd.) + Table 35-30. Additional MSRs Supported by Intel® Xeon® Processor E5 v3 Family + Table 35-33. Additional MSRs Supported by Intel® Core™ M Processors and 5th Generation Intel® Core™ Processors + Table 35-34. Additional MSRs Common to Intel® Xeon® Processor D and Intel Xeon Processors E5 v4 Family Based on the Broadwell Microarchitecture + Table 35-37. Additional MSRs Supported by 6th Generation Intel® Core™ Processors Based on Skylake Microarchitecture + Table 35-40. Selected MSRs Supported by Next Generation Intel® Xeon Phi™ Processors with DisplayFamily_DisplayModel Signature 06_57H + MSR_TURBO_RATIO_LIMIT[7:0] is Maximum Ratio Limit for 1C */ + err = cpu_rdmsr_range(info->handle, MSR_TURBO_RATIO_LIMIT, 7, 0, ®); + if (!err) return (double) reg; + } } else if(info->id->vendor == VENDOR_AMD || info->id->vendor == VENDOR_HYGON) { /* Refer links above @@ -1105,7 +1103,7 @@ static int get_info_temperature(struct msr_info_t *info) int err; uint64_t DigitalReadout, ReadingValid, TemperatureTarget; - if(msr_temperature_target_supported(info)) { + if(msr_intel_core_supported(info)) { /* Refer links above Table 35-2. IA-32 Architectural MSRs IA32_THERM_STATUS[22:16] is Digital Readout @@ -1133,7 +1131,7 @@ static double get_info_voltage(struct msr_info_t *info) double VIDStep; uint64_t reg, CpuVid; - if(msr_perf_status_supported(info)) { + if(msr_intel_core_supported(info)) { /* Refer links above Table 35-18. MSRs Supported by Intel® Processors based on Intel® microarchitecture code name Sandy Bridge (Contd.) MSR_PERF_STATUS[47:32] is Core Voltage diff --git a/libcpuid/recog_amd.c b/libcpuid/recog_amd.c index 6479d29..a433833 100644 --- a/libcpuid/recog_amd.c +++ b/libcpuid/recog_amd.c @@ -26,374 +26,355 @@ #include #include +#include #include "libcpuid.h" -#include "libcpuid_ctype.h" #include "libcpuid_util.h" #include "libcpuid_internal.h" #include "recog_amd.h" -const struct amd_code_str { amd_code_t code; char *str; } amd_code_str[] = { - #define CODE(x) { x, #x } - #define CODE2(x, y) CODE(x) - #include "amd_code_t.h" - #undef CODE -}; - -struct amd_code_and_bits_t { - int code; - uint64_t bits; -}; - const struct match_entry_t cpudb_amd[] = { -// F M S EF EM #cores L2$ L3$ BC ModelBits ModelCode Name - { -1, -1, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Unknown AMD CPU" }, + +// F M S EF EM #cores L2$ L3$ Pattern Name + { -1, -1, -1, -1, -1, 1, -1, -1, { "", 0 }, "Unknown AMD CPU" }, /* 486 and the likes */ - { 4, -1, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Unknown AMD 486" }, - { 4, 3, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "AMD 486DX2" }, - { 4, 7, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "AMD 486DX2WB" }, - { 4, 8, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "AMD 486DX4" }, - { 4, 9, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "AMD 486DX4WB" }, + { 4, -1, -1, -1, -1, 1, -1, -1, { "", 0 }, "Unknown AMD 486" }, + { 4, 3, -1, -1, -1, 1, -1, -1, { "", 0 }, "AMD 486DX2" }, + { 4, 7, -1, -1, -1, 1, -1, -1, { "", 0 }, "AMD 486DX2WB" }, + { 4, 8, -1, -1, -1, 1, -1, -1, { "", 0 }, "AMD 486DX4" }, + { 4, 9, -1, -1, -1, 1, -1, -1, { "", 0 }, "AMD 486DX4WB" }, /* Pentia clones */ - { 5, -1, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Unknown AMD 586" }, - { 5, 0, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "K5" }, - { 5, 1, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "K5" }, - { 5, 2, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "K5" }, - { 5, 3, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "K5" }, + { 5, -1, -1, -1, -1, 1, -1, -1, { "", 0 }, "Unknown AMD 586" }, + { 5, 0, -1, -1, -1, 1, -1, -1, { "", 0 }, "K5" }, + { 5, 1, -1, -1, -1, 1, -1, -1, { "", 0 }, "K5" }, + { 5, 2, -1, -1, -1, 1, -1, -1, { "", 0 }, "K5" }, + { 5, 3, -1, -1, -1, 1, -1, -1, { "", 0 }, "K5" }, /* The K6 */ - { 5, 6, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "K6" }, - { 5, 7, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "K6" }, + { 5, 6, -1, -1, -1, 1, -1, -1, { "", 0 }, "K6" }, + { 5, 7, -1, -1, -1, 1, -1, -1, { "", 0 }, "K6" }, - { 5, 8, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "K6-2" }, - { 5, 9, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "K6-III" }, - { 5, 10, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Unknown K6" }, - { 5, 11, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Unknown K6" }, - { 5, 12, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Unknown K6" }, - { 5, 13, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "K6-2+" }, + { 5, 8, -1, -1, -1, 1, -1, -1, { "", 0 }, "K6-2" }, + { 5, 9, -1, -1, -1, 1, -1, -1, { "", 0 }, "K6-III" }, + { 5, 10, -1, -1, -1, 1, -1, -1, { "", 0 }, "Unknown K6" }, + { 5, 11, -1, -1, -1, 1, -1, -1, { "", 0 }, "Unknown K6" }, + { 5, 12, -1, -1, -1, 1, -1, -1, { "", 0 }, "Unknown K6" }, + { 5, 13, -1, -1, -1, 1, -1, -1, { "", 0 }, "K6-2+" }, /* Athlon et al. */ - { 6, 1, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Athlon (Slot-A)" }, - { 6, 2, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Athlon (Slot-A)" }, - { 6, 3, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Duron (Spitfire)" }, - { 6, 4, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Athlon (ThunderBird)" }, + { 6, 1, -1, -1, -1, 1, -1, -1, { "", 0 }, "Athlon (Slot-A)" }, + { 6, 2, -1, -1, -1, 1, -1, -1, { "", 0 }, "Athlon (Slot-A)" }, + { 6, 3, -1, -1, -1, 1, -1, -1, { "", 0 }, "Duron (Spitfire)" }, + { 6, 4, -1, -1, -1, 1, -1, -1, { "", 0 }, "Athlon (ThunderBird)" }, - { 6, 6, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Unknown Athlon" }, - { 6, 6, -1, -1, -1, 1, -1, -1, NC, ATHLON_ , 0, "Athlon (Palomino)" }, - { 6, 6, -1, -1, -1, 1, -1, -1, NC, ATHLON_|_MP_ , 0, "Athlon MP (Palomino)" }, - { 6, 6, -1, -1, -1, 1, -1, -1, NC, DURON_ , 0, "Duron (Palomino)" }, - { 6, 6, -1, -1, -1, 1, -1, -1, NC, ATHLON_|_XP_ , 0, "Athlon XP" }, + { 6, 6, -1, -1, -1, 1, -1, -1, { "", 0 }, "Unknown Athlon" }, + { 6, 6, -1, -1, -1, 1, -1, -1, { "Athlon", 2 }, "Athlon (Palomino)" }, + { 6, 6, -1, -1, -1, 1, -1, -1, { "Athlon(tm) MP", 4 }, "Athlon MP (Palomino)" }, + { 6, 6, -1, -1, -1, 1, -1, -1, { "Duron(tm)", 2 }, "Duron (Palomino)" }, + { 6, 6, -1, -1, -1, 1, -1, -1, { "Athlon(tm) XP", 4 }, "Athlon XP" }, - { 6, 7, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Unknown Athlon XP" }, - { 6, 7, -1, -1, -1, 1, -1, -1, NC, DURON_ , 0, "Duron (Morgan)" }, + { 6, 7, -1, -1, -1, 1, -1, -1, { "", 0 }, "Unknown Athlon XP" }, + { 6, 7, -1, -1, -1, 1, -1, -1, { "Duron(tm)", 2 }, "Duron (Morgan)" }, - { 6, 8, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Athlon XP" }, - { 6, 8, -1, -1, -1, 1, -1, -1, NC, ATHLON_ , 0, "Athlon XP (Thoroughbred)" }, - { 6, 8, -1, -1, -1, 1, -1, -1, NC, ATHLON_|_XP_ , 0, "Athlon XP (Thoroughbred)" }, - { 6, 8, -1, -1, -1, 1, -1, -1, NC, DURON_ , 0, "Duron (Applebred)" }, - { 6, 8, -1, -1, -1, 1, -1, -1, NC, SEMPRON_ , 0, "Sempron (Thoroughbred)" }, - { 6, 8, -1, -1, -1, 1, 128, -1, NC, SEMPRON_ , 0, "Sempron (Thoroughbred)" }, - { 6, 8, -1, -1, -1, 1, 256, -1, NC, SEMPRON_ , 0, "Sempron (Thoroughbred)" }, - { 6, 8, -1, -1, -1, 1, -1, -1, NC, ATHLON_|_MP_ , 0, "Athlon MP (Thoroughbred)" }, - { 6, 8, -1, -1, -1, 1, -1, -1, NC, ATHLON_|_XP_|_M_ , 0, "Mobile Athlon (T-Bred)" }, - { 6, 8, -1, -1, -1, 1, -1, -1, NC, ATHLON_|_XP_|_M_|_LV_, 0, "Mobile Athlon (T-Bred)" }, + { 6, 8, -1, -1, -1, 1, -1, -1, { "", 0 }, "Athlon XP" }, + { 6, 8, -1, -1, -1, 1, -1, -1, { "Athlon", 2 }, "Athlon XP (Thoroughbred)" }, + { 6, 8, -1, -1, -1, 1, -1, -1, { "Athlon(tm) XP", 4 }, "Athlon XP (Thoroughbred)" }, + { 6, 8, -1, -1, -1, 1, -1, -1, { "Duron(tm)", 2 }, "Duron (Applebred)" }, + { 6, 8, -1, -1, -1, 1, -1, -1, { "Sempron(tm)", 2 }, "Sempron (Thoroughbred)" }, + { 6, 8, -1, -1, -1, 1, 128, -1, { "Sempron(tm)", 2 }, "Sempron (Thoroughbred)" }, + { 6, 8, -1, -1, -1, 1, 256, -1, { "Sempron(tm)", 2 }, "Sempron (Thoroughbred)" }, + { 6, 8, -1, -1, -1, 1, -1, -1, { "Athlon(tm) MP", 4 }, "Athlon MP (Thoroughbred)" }, + { 6, 8, -1, -1, -1, 1, -1, -1, { "Athlon(tm) XP-M", 6 }, "Mobile Athlon (T-Bred)" }, - { 6, 10, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Athlon XP (Barton)" }, - { 6, 10, -1, -1, -1, 1, 512, -1, NC, ATHLON_|_XP_ , 0, "Athlon XP (Barton)" }, - { 6, 10, -1, -1, -1, 1, 512, -1, NC, SEMPRON_ , 0, "Sempron (Barton)" }, - { 6, 10, -1, -1, -1, 1, 256, -1, NC, SEMPRON_ , 0, "Sempron (Thorton)" }, - { 6, 10, -1, -1, -1, 1, 256, -1, NC, ATHLON_|_XP_ , 0, "Athlon XP (Thorton)" }, - { 6, 10, -1, -1, -1, 1, -1, -1, NC, ATHLON_|_MP_ , 0, "Athlon MP (Barton)" }, - { 6, 10, -1, -1, -1, 1, -1, -1, NC, ATHLON_|_XP_|_M_ , 0, "Mobile Athlon (Barton)" }, - { 6, 10, -1, -1, -1, 1, -1, -1, NC, ATHLON_|_XP_|_M_|_LV_, 0, "Mobile Athlon (Barton)" }, + { 6, 10, -1, -1, -1, 1, -1, -1, { "", 0 }, "Athlon XP (Barton)" }, + { 6, 10, -1, -1, -1, 1, 512, -1, { "Athlon(tm) XP", 4 }, "Athlon XP (Barton)" }, + { 6, 10, -1, -1, -1, 1, 512, -1, { "Sempron(tm)", 2 }, "Sempron (Barton)" }, + { 6, 10, -1, -1, -1, 1, 256, -1, { "Sempron(tm)", 2 }, "Sempron (Thorton)" }, + { 6, 10, -1, -1, -1, 1, 256, -1, { "Athlon(tm) XP", 4 }, "Athlon XP (Thorton)" }, + { 6, 10, -1, -1, -1, 1, -1, -1, { "Athlon(tm) MP", 4 }, "Athlon MP (Barton)" }, + { 6, 10, -1, -1, -1, 1, -1, -1, { "Athlon(tm) XP-M", 6 }, "Mobile Athlon (Barton)" }, /* K8 Architecture */ - { 15, -1, -1, 15, -1, 1, -1, -1, NC, 0 , 0, "Unknown K8" }, - { 15, -1, -1, 16, -1, 1, -1, -1, NC, 0 , 0, "Unknown K9" }, + { 15, -1, -1, 15, -1, 1, -1, -1, { "", 0 }, "Unknown K8" }, + { 15, -1, -1, 16, -1, 1, -1, -1, { "", 0 }, "Unknown K9" }, - { 15, -1, -1, 15, -1, 1, -1, -1, NC, 0 , 0, "Unknown A64" }, - { 15, -1, -1, 15, -1, 1, -1, -1, NC, OPTERON_ , 0, "Opteron" }, - { 15, -1, -1, 15, -1, 2, -1, -1, NC, OPTERON_|_X2 , 0, "Opteron (Dual Core)" }, - { 15, 3, -1, 15, -1, 1, -1, -1, NC, OPTERON_ , 0, "Opteron" }, - { 15, 3, -1, 15, -1, 2, -1, -1, NC, OPTERON_|_X2 , 0, "Opteron (Dual Core)" }, - { 15, -1, -1, 15, -1, 1, 512, -1, NC, ATHLON_|_64_ , 0, "Athlon 64 (512K)" }, - { 15, -1, -1, 15, -1, 1, 1024, -1, NC, ATHLON_|_64_ , 0, "Athlon 64 (1024K)" }, - { 15, -1, -1, 15, -1, 1, -1, -1, NC, ATHLON_|_FX , 0, "Athlon FX" }, - { 15, -1, -1, 15, -1, 1, -1, -1, NC, ATHLON_|_64_|_FX , 0, "Athlon 64 FX" }, - { 15, 3, -1, 15, 35, 2, -1, -1, NC, ATHLON_|_64_|_FX , 0, "Athlon 64 FX X2 (Toledo)" }, - { 15, -1, -1, 15, -1, 2, 512, -1, NC, ATHLON_|_64_|_X2 , 0, "Athlon 64 X2 (512K)" }, - { 15, -1, -1, 15, -1, 2, 1024, -1, NC, ATHLON_|_64_|_X2 , 0, "Athlon 64 X2 (1024K)" }, - { 15, -1, -1, 15, -1, 1, 512, -1, NC, TURION_|_64_ , 0, "Turion 64 (512K)" }, - { 15, -1, -1, 15, -1, 1, 1024, -1, NC, TURION_|_64_ , 0, "Turion 64 (1024K)" }, - { 15, -1, -1, 15, -1, 2, 512, -1, NC, TURION_|_X2 , 0, "Turion 64 X2 (512K)" }, - { 15, -1, -1, 15, -1, 2, 1024, -1, NC, TURION_|_X2 , 0, "Turion 64 X2 (1024K)" }, - { 15, -1, -1, 15, -1, 1, 128, -1, NC, SEMPRON_ , 0, "A64 Sempron (128K)" }, - { 15, -1, -1, 15, -1, 1, 256, -1, NC, SEMPRON_ , 0, "A64 Sempron (256K)" }, - { 15, -1, -1, 15, -1, 1, 512, -1, NC, SEMPRON_ , 0, "A64 Sempron (512K)" }, - { 15, -1, -1, 15, 0x4f, 1, 512, -1, NC, ATHLON_|_64_ , 0, "Athlon 64 (Orleans/512K)" }, - { 15, -1, -1, 15, 0x5f, 1, 512, -1, NC, ATHLON_|_64_ , 0, "Athlon 64 (Orleans/512K)" }, - { 15, -1, -1, 15, 0x2f, 1, 512, -1, NC, ATHLON_|_64_ , 0, "Athlon 64 (Venice/512K)" }, - { 15, -1, -1, 15, 0x2c, 1, 512, -1, NC, ATHLON_|_64_ , 0, "Athlon 64 (Venice/512K)" }, - { 15, -1, -1, 15, 0x1f, 1, 512, -1, NC, ATHLON_|_64_ , 0, "Athlon 64 (Winchester/512K)" }, - { 15, -1, -1, 15, 0x0c, 1, 512, -1, NC, ATHLON_|_64_ , 0, "Athlon 64 (Newcastle/512K)" }, - { 15, -1, -1, 15, 0x27, 1, 512, -1, NC, ATHLON_|_64_ , 0, "Athlon 64 (San Diego/512K)" }, - { 15, -1, -1, 15, 0x37, 1, 512, -1, NC, ATHLON_|_64_ , 0, "Athlon 64 (San Diego/512K)" }, - { 15, -1, -1, 15, 0x04, 1, 512, -1, NC, ATHLON_|_64_ , 0, "Athlon 64 (ClawHammer/512K)" }, + { 15, -1, -1, 15, -1, 1, -1, -1, { "", 0 }, "Unknown A64" }, + { 15, -1, -1, 15, -1, 1, -1, -1, { "Opteron(tm)", 2 }, "Opteron" }, + { 15, -1, -1, 15, -1, 2, -1, -1, { "Dual Core AMD Opteron", 8 }, "Opteron (Dual Core)" }, + { 15, 3, -1, 15, -1, 1, -1, -1, { "Opteron(tm)", 2 }, "Opteron" }, + { 15, 3, -1, 15, -1, 2, -1, -1, { "Dual Core AMD Opteron", 8 }, "Opteron (Dual Core)" }, + { 15, -1, -1, 15, -1, 1, 512, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (512K)" }, + { 15, -1, -1, 15, -1, 1, 1024, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (1024K)" }, + { 15, -1, -1, 15, -1, 1, -1, -1, { "Athlon(tm) FX", 4 }, "Athlon FX" }, + { 15, -1, -1, 15, -1, 1, -1, -1, { "Athlon(tm) 64 FX", 6 }, "Athlon 64 FX" }, + { 15, 3, -1, 15, 35, 2, -1, -1, { "Athlon(tm) 64 FX", 6 }, "Athlon 64 FX X2 (Toledo)" }, + { 15, -1, -1, 15, -1, 2, 512, -1, { "Athlon(tm) 64 X2", 6 }, "Athlon 64 X2 (512K)" }, + { 15, -1, -1, 15, -1, 2, 1024, -1, { "Athlon(tm) 64 X2", 6 }, "Athlon 64 X2 (1024K)" }, + { 15, -1, -1, 15, -1, 1, 512, -1, { "Turion(tm) 64", 4 }, "Turion 64 (512K)" }, + { 15, -1, -1, 15, -1, 1, 1024, -1, { "Turion(tm) 64", 4 }, "Turion 64 (1024K)" }, + { 15, -1, -1, 15, -1, 2, 512, -1, { "Turion(tm) X2", 4 }, "Turion 64 X2 (512K)" }, + { 15, -1, -1, 15, -1, 2, 1024, -1, { "Turion(tm) X2", 4 }, "Turion 64 X2 (1024K)" }, + { 15, -1, -1, 15, -1, 1, 128, -1, { "Sempron(tm)", 2 }, "A64 Sempron (128K)" }, + { 15, -1, -1, 15, -1, 1, 256, -1, { "Sempron(tm)", 2 }, "A64 Sempron (256K)" }, + { 15, -1, -1, 15, -1, 1, 512, -1, { "Sempron(tm)", 2 }, "A64 Sempron (512K)" }, + { 15, -1, -1, 15, 0x4f, 1, 512, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (Orleans/512K)" }, + { 15, -1, -1, 15, 0x5f, 1, 512, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (Orleans/512K)" }, + { 15, -1, -1, 15, 0x2f, 1, 512, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (Venice/512K)" }, + { 15, -1, -1, 15, 0x2c, 1, 512, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (Venice/512K)" }, + { 15, -1, -1, 15, 0x1f, 1, 512, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (Winchester/512K)" }, + { 15, -1, -1, 15, 0x0c, 1, 512, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (Newcastle/512K)" }, + { 15, -1, -1, 15, 0x27, 1, 512, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (San Diego/512K)" }, + { 15, -1, -1, 15, 0x37, 1, 512, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (San Diego/512K)" }, + { 15, -1, -1, 15, 0x04, 1, 512, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (ClawHammer/512K)" }, - { 15, -1, -1, 15, 0x5f, 1, 1024, -1, NC, ATHLON_|_64_ , 0, "Athlon 64 (Orleans/1024K)" }, - { 15, -1, -1, 15, 0x27, 1, 1024, -1, NC, ATHLON_|_64_ , 0, "Athlon 64 (San Diego/1024K)" }, - { 15, -1, -1, 15, 0x04, 1, 1024, -1, NC, ATHLON_|_64_ , 0, "Athlon 64 (ClawHammer/1024K)" }, + { 15, -1, -1, 15, 0x5f, 1, 1024, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (Orleans/1024K)" }, + { 15, -1, -1, 15, 0x27, 1, 1024, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (San Diego/1024K)" }, + { 15, -1, -1, 15, 0x04, 1, 1024, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (ClawHammer/1024K)" }, - { 15, -1, -1, 15, 0x4b, 2, 256, -1, NC, SEMPRON_ , 0, "Athlon 64 X2 (Windsor/256K)" }, + { 15, -1, -1, 15, 0x4b, 2, 256, -1, { "Athlon(tm) 64 X2", 6 }, "Athlon 64 X2 (Windsor/256K)" }, - { 15, -1, -1, 15, 0x23, 2, 512, -1, NC, ATHLON_|_64_|_X2 , 0, "Athlon 64 X2 (Toledo/512K)" }, - { 15, -1, -1, 15, 0x4b, 2, 512, -1, NC, ATHLON_|_64_|_X2 , 0, "Athlon 64 X2 (Windsor/512K)" }, - { 15, -1, -1, 15, 0x43, 2, 512, -1, NC, ATHLON_|_64_|_X2 , 0, "Athlon 64 X2 (Windsor/512K)" }, - { 15, -1, -1, 15, 0x6b, 2, 512, -1, NC, ATHLON_|_64_|_X2 , 0, "Athlon 64 X2 (Brisbane/512K)" }, - { 15, -1, -1, 15, 0x2b, 2, 512, -1, NC, ATHLON_|_64_|_X2 , 0, "Athlon 64 X2 (Manchester/512K)"}, + { 15, -1, -1, 15, 0x23, 2, 512, -1, { "Athlon(tm) 64 X2", 6 }, "Athlon 64 X2 (Toledo/512K)" }, + { 15, -1, -1, 15, 0x4b, 2, 512, -1, { "Athlon(tm) 64 X2", 6 }, "Athlon 64 X2 (Windsor/512K)" }, + { 15, -1, -1, 15, 0x43, 2, 512, -1, { "Athlon(tm) 64 X2", 6 }, "Athlon 64 X2 (Windsor/512K)" }, + { 15, -1, -1, 15, 0x6b, 2, 512, -1, { "Athlon(tm) 64 X2", 6 }, "Athlon 64 X2 (Brisbane/512K)" }, + { 15, -1, -1, 15, 0x2b, 2, 512, -1, { "Athlon(tm) 64 X2", 6 }, "Athlon 64 X2 (Manchester/512K)"}, - { 15, -1, -1, 15, 0x23, 2, 1024, -1, NC, ATHLON_|_64_|_X2 , 0, "Athlon 64 X2 (Toledo/1024K)" }, - { 15, -1, -1, 15, 0x43, 2, 1024, -1, NC, ATHLON_|_64_|_X2 , 0, "Athlon 64 X2 (Windsor/1024K)" }, + { 15, -1, -1, 15, 0x23, 2, 1024, -1, { "Athlon(tm) 64 X2", 6 }, "Athlon 64 X2 (Toledo/1024K)" }, + { 15, -1, -1, 15, 0x43, 2, 1024, -1, { "Athlon(tm) 64 X2", 6 }, "Athlon 64 X2 (Windsor/1024K)" }, - { 15, -1, -1, 15, 0x08, 1, 128, -1, NC, MOBILE_|SEMPRON_ , 0, "Mobile Sempron 64 (Dublin/128K)"}, - { 15, -1, -1, 15, 0x08, 1, 256, -1, NC, MOBILE_|SEMPRON_ , 0, "Mobile Sempron 64 (Dublin/256K)"}, - { 15, -1, -1, 15, 0x0c, 1, 256, -1, NC, SEMPRON_ , 0, "Sempron 64 (Paris)" }, - { 15, -1, -1, 15, 0x1c, 1, 128, -1, NC, SEMPRON_ , 0, "Sempron 64 (Palermo/128K)" }, - { 15, -1, -1, 15, 0x1c, 1, 256, -1, NC, SEMPRON_ , 0, "Sempron 64 (Palermo/256K)" }, - { 15, -1, -1, 15, 0x1c, 1, 128, -1, NC, MOBILE_| SEMPRON_ , 0, "Mobile Sempron 64 (Sonora/128K)"}, - { 15, -1, -1, 15, 0x1c, 1, 256, -1, NC, MOBILE_| SEMPRON_ , 0, "Mobile Sempron 64 (Sonora/256K)"}, - { 15, -1, -1, 15, 0x2c, 1, 128, -1, NC, SEMPRON_ , 0, "Sempron 64 (Palermo/128K)" }, - { 15, -1, -1, 15, 0x2c, 1, 256, -1, NC, SEMPRON_ , 0, "Sempron 64 (Palermo/256K)" }, - { 15, -1, -1, 15, 0x2c, 1, 128, -1, NC, MOBILE_| SEMPRON_ , 0, "Mobile Sempron 64 (Albany/128K)"}, - { 15, -1, -1, 15, 0x2c, 1, 256, -1, NC, MOBILE_| SEMPRON_ , 0, "Mobile Sempron 64 (Albany/256K)"}, - { 15, -1, -1, 15, 0x2f, 1, 128, -1, NC, SEMPRON_ , 0, "Sempron 64 (Palermo/128K)" }, - { 15, -1, -1, 15, 0x2f, 1, 256, -1, NC, SEMPRON_ , 0, "Sempron 64 (Palermo/256K)" }, - { 15, -1, -1, 15, 0x4f, 1, 128, -1, NC, SEMPRON_ , 0, "Sempron 64 (Manila/128K)" }, - { 15, -1, -1, 15, 0x4f, 1, 256, -1, NC, SEMPRON_ , 0, "Sempron 64 (Manila/256K)" }, - { 15, -1, -1, 15, 0x5f, 1, 128, -1, NC, SEMPRON_ , 0, "Sempron 64 (Manila/128K)" }, - { 15, -1, -1, 15, 0x5f, 1, 256, -1, NC, SEMPRON_ , 0, "Sempron 64 (Manila/256K)" }, - { 15, -1, -1, 15, 0x6b, 2, 256, -1, NC, SEMPRON_ , 0, "Sempron 64 Dual (Sherman/256K)"}, - { 15, -1, -1, 15, 0x6b, 2, 512, -1, NC, SEMPRON_ , 0, "Sempron 64 Dual (Sherman/512K)"}, - { 15, -1, -1, 15, 0x7c, 1, 512, -1, NC, ATHLON_ , 0, "Athlon 64 (Sherman/512K)" }, - { 15, -1, -1, 15, 0x7f, 1, 256, -1, NC, SEMPRON_ , 0, "Sempron 64 (Sparta/256K)" }, - { 15, -1, -1, 15, 0x7f, 1, 512, -1, NC, SEMPRON_ , 0, "Sempron 64 (Sparta/512K)" }, - { 15, -1, -1, 15, 0x4c, 1, 256, -1, NC, MOBILE_| SEMPRON_ , 0, "Mobile Sempron 64 (Keene/256K)"}, - { 15, -1, -1, 15, 0x4c, 1, 512, -1, NC, MOBILE_| SEMPRON_ , 0, "Mobile Sempron 64 (Keene/512K)"}, - { 15, -1, -1, 15, -1, 2, -1, -1, NC, SEMPRON_ , 0, "Sempron Dual Core" }, + { 15, -1, -1, 15, 0x08, 1, 128, -1, { "Mobile AMD Sempron(tm)", 6 }, "Mobile Sempron 64 (Dublin/128K)"}, + { 15, -1, -1, 15, 0x08, 1, 256, -1, { "Mobile AMD Sempron(tm)", 6 }, "Mobile Sempron 64 (Dublin/256K)"}, + { 15, -1, -1, 15, 0x0c, 1, 256, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Paris)" }, + { 15, -1, -1, 15, 0x1c, 1, 128, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Palermo/128K)" }, + { 15, -1, -1, 15, 0x1c, 1, 256, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Palermo/256K)" }, + { 15, -1, -1, 15, 0x1c, 1, 128, -1, { "Mobile AMD Sempron(tm)", 6 }, "Mobile Sempron 64 (Sonora/128K)"}, + { 15, -1, -1, 15, 0x1c, 1, 256, -1, { "Mobile AMD Sempron(tm)", 6 }, "Mobile Sempron 64 (Sonora/256K)"}, + { 15, -1, -1, 15, 0x2c, 1, 128, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Palermo/128K)" }, + { 15, -1, -1, 15, 0x2c, 1, 256, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Palermo/256K)" }, + { 15, -1, -1, 15, 0x2c, 1, 128, -1, { "Mobile AMD Sempron(tm)", 6 }, "Mobile Sempron 64 (Albany/128K)"}, + { 15, -1, -1, 15, 0x2c, 1, 256, -1, { "Mobile AMD Sempron(tm)", 6 }, "Mobile Sempron 64 (Albany/256K)"}, + { 15, -1, -1, 15, 0x2f, 1, 128, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Palermo/128K)" }, + { 15, -1, -1, 15, 0x2f, 1, 256, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Palermo/256K)" }, + { 15, -1, -1, 15, 0x4f, 1, 128, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Manila/128K)" }, + { 15, -1, -1, 15, 0x4f, 1, 256, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Manila/256K)" }, + { 15, -1, -1, 15, 0x5f, 1, 128, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Manila/128K)" }, + { 15, -1, -1, 15, 0x5f, 1, 256, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Manila/256K)" }, + { 15, -1, -1, 15, 0x6b, 2, 256, -1, { "Sempron(tm)", 2 }, "Sempron 64 Dual (Sherman/256K)"}, + { 15, -1, -1, 15, 0x6b, 2, 512, -1, { "Sempron(tm)", 2 }, "Sempron 64 Dual (Sherman/512K)"}, + { 15, -1, -1, 15, 0x7c, 1, 512, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (Sherman/512K)" }, + { 15, -1, -1, 15, 0x7f, 1, 256, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Sparta/256K)" }, + { 15, -1, -1, 15, 0x7f, 1, 512, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Sparta/512K)" }, + { 15, -1, -1, 15, 0x4c, 1, 256, -1, { "Mobile AMD Sempron(tm)", 6 }, "Mobile Sempron 64 (Keene/256K)"}, + { 15, -1, -1, 15, 0x4c, 1, 512, -1, { "Mobile AMD Sempron(tm)", 6 }, "Mobile Sempron 64 (Keene/512K)"}, - { 15, -1, -1, 15, 0x24, 1, 512, -1, NC, TURION_|_64_ , 0, "Turion 64 (Lancaster/512K)" }, - { 15, -1, -1, 15, 0x24, 1, 1024, -1, NC, TURION_|_64_ , 0, "Turion 64 (Lancaster/1024K)" }, - { 15, -1, -1, 15, 0x48, 2, 256, -1, NC, TURION_|_X2 , 0, "Turion X2 (Taylor)" }, - { 15, -1, -1, 15, 0x48, 2, 512, -1, NC, TURION_|_X2 , 0, "Turion X2 (Trinidad)" }, - { 15, -1, -1, 15, 0x4c, 1, 512, -1, NC, TURION_|_64_ , 0, "Turion 64 (Richmond)" }, - { 15, -1, -1, 15, 0x68, 2, 256, -1, NC, TURION_|_X2 , 0, "Turion X2 (Tyler/256K)" }, - { 15, -1, -1, 15, 0x68, 2, 512, -1, NC, TURION_|_X2 , 0, "Turion X2 (Tyler/512K)" }, - { 15, -1, -1, 17, 3, 2, 512, -1, NC, TURION_|_X2 , 0, "Turion X2 (Griffin/512K)" }, - { 15, -1, -1, 17, 3, 2, 1024, -1, NC, TURION_|_X2 , 0, "Turion X2 (Griffin/1024K)" }, + { 15, -1, -1, 15, 0x24, 1, 512, -1, { "Turion(tm) 64", 4 }, "Turion 64 (Lancaster/512K)" }, + { 15, -1, -1, 15, 0x24, 1, 1024, -1, { "Turion(tm) 64", 4 }, "Turion 64 (Lancaster/1024K)" }, + { 15, -1, -1, 15, 0x48, 2, 256, -1, { "Turion(tm) X2", 4 }, "Turion X2 (Taylor)" }, + { 15, -1, -1, 15, 0x48, 2, 512, -1, { "Turion(tm) X2", 4 }, "Turion X2 (Trinidad)" }, + { 15, -1, -1, 15, 0x4c, 1, 512, -1, { "Turion(tm) 64", 4 }, "Turion 64 (Richmond)" }, + { 15, -1, -1, 15, 0x68, 2, 256, -1, { "Turion(tm) X2", 4 }, "Turion X2 (Tyler/256K)" }, + { 15, -1, -1, 15, 0x68, 2, 512, -1, { "Turion(tm) X2", 4 }, "Turion X2 (Tyler/512K)" }, + { 15, -1, -1, 17, 3, 2, 512, -1, { "Turion(tm) X2", 4 }, "Turion X2 (Griffin/512K)" }, + { 15, -1, -1, 17, 3, 2, 1024, -1, { "Turion(tm) X2", 4 }, "Turion X2 (Griffin/1024K)" }, /* K10 Architecture (2007) */ - { 15, -1, -1, 16, -1, 1, -1, -1, PHENOM, 0 , 0, "Unknown AMD Phenom" }, - { 15, 2, -1, 16, -1, 1, -1, -1, PHENOM, 0 , 0, "Phenom" }, - { 15, 2, -1, 16, -1, 3, -1, -1, PHENOM, 0 , 0, "Phenom X3 (Toliman)" }, - { 15, 2, -1, 16, -1, 4, -1, -1, PHENOM, 0 , 0, "Phenom X4 (Agena)" }, - { 15, 2, -1, 16, -1, 3, 512, -1, PHENOM, 0 , 0, "Phenom X3 (Toliman/256K)" }, - { 15, 2, -1, 16, -1, 3, 512, -1, PHENOM, 0 , 0, "Phenom X3 (Toliman/512K)" }, - { 15, 2, -1, 16, -1, 4, 128, -1, PHENOM, 0 , 0, "Phenom X4 (Agena/128K)" }, - { 15, 2, -1, 16, -1, 4, 256, -1, PHENOM, 0 , 0, "Phenom X4 (Agena/256K)" }, - { 15, 2, -1, 16, -1, 4, 512, -1, PHENOM, 0 , 0, "Phenom X4 (Agena/512K)" }, - { 15, 2, -1, 16, -1, 2, 512, -1, NC, ATHLON_|_64_|_X2 , 0, "Athlon X2 (Kuma)" }, + { 15, 2, -1, 16, -1, 3, -1, -1, { "Phenom(tm)", 2 }, "Phenom X3 (Toliman)" }, + { 15, 2, -1, 16, -1, 4, -1, -1, { "Phenom(tm)", 2 }, "Phenom X4 (Agena)" }, + { 15, 2, -1, 16, -1, 3, 512, -1, { "Phenom(tm)", 2 }, "Phenom X3 (Toliman/256K)" }, + { 15, 2, -1, 16, -1, 3, 512, -1, { "Phenom(tm)", 2 }, "Phenom X3 (Toliman/512K)" }, + { 15, 2, -1, 16, -1, 4, 128, -1, { "Phenom(tm)", 2 }, "Phenom X4 (Agena/128K)" }, + { 15, 2, -1, 16, -1, 4, 256, -1, { "Phenom(tm)", 2 }, "Phenom X4 (Agena/256K)" }, + { 15, 2, -1, 16, -1, 4, 512, -1, { "Phenom(tm)", 2 }, "Phenom X4 (Agena/512K)" }, + { 15, 2, -1, 16, -1, 2, 512, -1, { "Athlon(tm) 64 X2", 6 }, "Athlon X2 (Kuma)" }, /* Phenom II derivates: */ - { 15, 4, -1, 16, -1, 4, -1, -1, NC, 0 , 0, "Phenom (Deneb-based)" }, - { 15, 4, -1, 16, -1, 1, 1024, -1, NC, SEMPRON_ , 0, "Sempron (Sargas)" }, - { 15, 4, -1, 16, -1, 2, 512, -1, PHENOM2, 0 , 0, "Phenom II X2 (Callisto)" }, - { 15, 4, -1, 16, -1, 3, 512, -1, PHENOM2, 0 , 0, "Phenom II X3 (Heka)" }, - { 15, 4, -1, 16, -1, 4, 512, -1, PHENOM2, 0 , 0, "Phenom II X4" }, - { 15, 4, -1, 16, 4, 4, 512, -1, PHENOM2, 0 , 0, "Phenom II X4 (Deneb)" }, - { 15, 5, -1, 16, 5, 4, 512, -1, PHENOM2, 0 , 0, "Phenom II X4 (Deneb)" }, - { 15, 4, -1, 16, 10, 4, 512, -1, PHENOM2, 0 , 0, "Phenom II X4 (Zosma)" }, - { 15, 4, -1, 16, 10, 6, 512, -1, PHENOM2, 0 , 0, "Phenom II X6 (Thuban)" }, + { 15, 4, -1, 16, -1, 1, 1024, -1, { "Sempron(tm)", 2 }, "Sempron (Sargas)" }, + { 15, 4, -1, 16, -1, 2, 512, -1, { "Phenom(tm) II", 4 }, "Phenom II X2 (Callisto)" }, + { 15, 4, -1, 16, -1, 3, 512, -1, { "Phenom(tm) II", 4 }, "Phenom II X3 (Heka)" }, + { 15, 4, -1, 16, 4, 4, 512, -1, { "Phenom(tm) II", 4 }, "Phenom II X4 (Deneb)" }, + { 15, 5, -1, 16, 5, 4, 512, -1, { "Phenom(tm) II", 4 }, "Phenom II X4 (Deneb)" }, + { 15, 4, -1, 16, 10, 4, 512, -1, { "Phenom(tm) II", 4 }, "Phenom II X4 (Zosma)" }, + { 15, 4, -1, 16, 10, 6, 512, -1, { "Phenom(tm) II", 4 }, "Phenom II X6 (Thuban)" }, /* Athlon II derivates: */ - { 15, 6, -1, 16, 6, 2, 512, -1, NC, ATHLON_|_X2 , 0, "Athlon II (Champlain)" }, - { 15, 6, -1, 16, 6, 2, 512, -1, NC, ATHLON_|_64_|_X2 , 0, "Athlon II X2 (Regor)" }, - { 15, 6, -1, 16, 6, 2, 1024, -1, NC, ATHLON_|_64_|_X2 , 0, "Athlon II X2 (Regor)" }, - { 15, 5, -1, 16, 5, 3, 512, -1, NC, ATHLON_|_64_|_X3 , 0, "Athlon II X3 (Rana)" }, - { 15, 5, -1, 16, 5, 4, 512, -1, NC, ATHLON_|_64_|_X4 , 0, "Athlon II X4 (Propus)" }, + { 15, 6, -1, 16, 6, 2, 512, -1, { "Athlon(tm) II", 4 }, "Athlon II (Champlain)" }, + { 15, 6, -1, 16, 6, 2, 512, -1, { "Athlon(tm) II X2", 6 }, "Athlon II X2 (Regor)" }, + { 15, 6, -1, 16, 6, 2, 1024, -1, { "Athlon(tm) II X2", 6 }, "Athlon II X2 (Regor)" }, + { 15, 5, -1, 16, 5, 3, 512, -1, { "Athlon(tm) II X3", 6 }, "Athlon II X3 (Rana)" }, + { 15, 5, -1, 16, 5, 4, 512, -1, { "Athlon(tm) X4", 4 }, "Athlon II X4 (Propus)" }, + { 15, 5, -1, 16, 5, 4, 512, -1, { "Athlon(tm) II X4", 6 }, "Athlon II X4 (Propus)" }, /* Opteron derivates: */ - { 15, 9, -1, 22, 9, 8, -1, -1, NC, OPTERON_ , 0, "Magny-Cours Opteron" }, + { 15, 9, -1, 22, 9, 8, -1, -1, { "Opteron(tm)", 2 }, "Opteron (Magny-Cours)" }, + /* Llano APUs (2011): */ - { 15, 1, -1, 18, 1, 2, -1, -1, FUSION_EA, 0 , 0, "Llano X2" }, - { 15, 1, -1, 18, 1, 3, -1, -1, FUSION_EA, 0 , 0, "Llano X3" }, - { 15, 1, -1, 18, 1, 4, -1, -1, FUSION_EA, 0 , 0, "Llano X4" }, + { 15, 1, -1, 18, 1, -1, -1, -1, { "E2-3###", 4 }, "E-Series (Llano)" }, + { 15, 1, -1, 18, 1, -1, -1, -1, { "A[468]-3###", 4 }, "A-Series (Llano)" }, /* Family 14h: Bobcat Architecture (2011) */ - { 15, 2, -1, 20, -1, 1, -1, -1, FUSION_C, 0 , 0, "Brazos Ontario" }, - { 15, 2, -1, 20, -1, 2, -1, -1, FUSION_C, 0 , 0, "Brazos Ontario (Dual-core)" }, - { 15, 1, -1, 20, -1, 1, -1, -1, FUSION_E, 0 , 0, "Brazos Zacate" }, - { 15, 1, -1, 20, -1, 2, -1, -1, FUSION_E, 0 , 0, "Brazos Zacate (Dual-core)" }, - { 15, 2, -1, 20, -1, 2, -1, -1, FUSION_Z, 0 , 0, "Brazos Desna (Dual-core)" }, + { 15, 2, -1, 20, -1, -1, -1, -1, { "C([356]#", 4 }, "C-Series (Ontario)" }, + { 15, 1, -1, 20, -1, -1, -1, -1, { "E-[234]##", 4 }, "E-Series (Zacate)" }, + { 15, 2, -1, 20, -1, -1, -1, -1, { "Z-##", 4 }, "Z-Series (Desna)" }, /* Family 15h: Bulldozer Architecture (2011) */ - { 15, -1, -1, 21, 0, 4, -1, -1, NC, 0 , 0, "Zambezi X2" }, - { 15, -1, -1, 21, 1, 4, -1, -1, NC, 0 , 0, "Zambezi X2" }, - { 15, -1, -1, 21, 1, 6, -1, -1, NC, 0 , 0, "Zambezi X3" }, - { 15, -1, -1, 21, 1, 8, -1, -1, NC, 0 , 0, "Zambezi X4" }, - { 15, -1, -1, 21, 1, -1, -1, -1, NC, OPTERON_ , 0, "Interlagos" }, + { 15, -1, -1, 21, 0, -1, -1, -1, { "FX(tm)-[468]###", 4 }, "FX (Zambezi)" }, + { 15, -1, -1, 21, 1, -1, -1, -1, { "FX(tm)-[468]###", 4 }, "FX (Zambezi)" }, + { 15, -1, -1, 21, 1, -1, -1, -1, { "Opteron(tm)", 2 }, "Opteron (Interlagos)" }, /* 2nd-gen, Piledriver core (2012): */ - { 15, -1, -1, 21, 2, 4, -1, -1, NC, 0 , 0, "Vishera X2" }, - { 15, -1, -1, 21, 2, 6, -1, -1, NC, 0 , 0, "Vishera X3" }, - { 15, -1, -1, 21, 2, 8, -1, -1, NC, 0 , 0, "Vishera X4" }, - { 15, 0, -1, 21, 16, 2, -1, -1, FUSION_A, 0 , 0, "Trinity X2" }, - { 15, 0, -1, 21, 16, 4, -1, -1, FUSION_A, 0 , 0, "Trinity X4" }, - { 15, 3, -1, 21, 19, 2, -1, -1, FUSION_A, 0 , 0, "Richland X2" }, - { 15, 3, -1, 21, 19, 4, -1, -1, FUSION_A, 0 , 0, "Richland X4" }, - { 15, 2, -1, 21, 2, -1, -1, -1, NC, OPTERON_ , 0, "Abu Dhabi" }, + { 15, -1, -1, 21, 2, -1, -1, -1, { "FX(tm)-[4689]###", 4 }, "FX (Vishera)" }, + { 15, 0, -1, 21, 16, -1, -1, -1, { "A[468]-4###", 4 }, "A-Series (Trinity)" }, + { 15, 0, -1, 21, 16, -1, -1, -1, { "A10-4###", 4 }, "A-Series (Trinity)" }, + { 15, 0, -1, 21, 19, -1, -1, -1, { "A[468]-5###", 4 }, "A-Series (Richland)" }, + { 15, 0, -1, 21, 19, -1, -1, -1, { "A10-5###", 4 }, "A-Series (Richland)" }, + { 15, 2, -1, 21, 2, -1, -1, -1, { "Opteron(tm)", 2 }, "Opteron (Abu Dhabi)" }, /* 3rd-gen, Steamroller core (2014): */ - { 15, 0, -1, 21, 48, 2, -1, -1, FUSION_A, 0 , 0, "Kaveri X2" }, - { 15, 0, -1, 21, 48, 4, -1, -1, FUSION_A, 0 , 0, "Kaveri X4" }, - { 15, 8, -1, 21, 56, 2, -1, -1, FUSION_A, 0 , 0, "Godavari X2" }, - { 15, 8, -1, 21, 56, 4, -1, -1, FUSION_A, 0 , 0, "Godavari X4" }, - { 15, 8, -1, 21, 56, 4, -1, -1, NC , ATHLON_|_X4 , 0, "Godavari X4" }, - { 15, 0, -1, 21, 48, 2, -1, -1, FUSION_RX, 0 , 0, "Bald Eagle X2" }, - { 15, 0, -1, 21, 48, 4, -1, -1, FUSION_RX, 0 , 0, "Bald Eagle X4" }, + { 15, 8, -1, 21, 48, -1, -1, -1, { "A[468-[78]###", 4 }, "A-Series (Kaveri)" }, + { 15, 8, -1, 21, 48, -1, -1, -1, { "A10-[78]###", 4 }, "A-Series (Kaveri)" }, + { 15, 8, -1, 21, 48, 2, -1, -1, { "Athlon(tm) X2", 4 }, "Athlon X2 (Kaveri)" }, + { 15, 8, -1, 21, 48, 4, -1, -1, { "Athlon(tm) X4", 4 }, "Athlon X4 (Kaveri)" }, + { 15, 8, -1, 21, 56, -1, -1, -1, { "A[468-[78]###", 4 }, "A-Series (Godavari)" }, + { 15, 8, -1, 21, 56, -1, -1, -1, { "A10-[78]###", 4 }, "A-Series (Godavari)" }, + { 15, 8, -1, 21, 56, 4, -1, -1, { "Athlon(tm) X4", 4 }, "Athlon X4 (Godavari)" }, + { 15, 0, -1, 21, 48, -1, -1, -1, { "RX-###", 4 }, "R-Series (Bald Eagle)" }, /* 4th-gen, Excavator core (2015): */ - { 15, 1, -1, 21, 96, 2, -1, -1, FUSION_A, 0 , 0, "Carrizo X2" }, - { 15, 1, -1, 21, 96, 4, -1, -1, FUSION_A, 0 , 0, "Carrizo X4" }, - { 15, 5, -1, 21, 101, 2, -1, -1, FUSION_A, 0 , 0, "Bristol Ridge X2" }, - { 15, 5, -1, 21, 101, 4, -1, -1, FUSION_A, 0 , 0, "Bristol Ridge X4" }, - { 15, 0, -1, 21, 112, 2, -1, -1, FUSION_A, 0 , 0, "Stoney Ridge X2" }, - { 15, 0, -1, 21, 112, 2, -1, -1, FUSION_E, 0 , 0, "Stoney Ridge X2" }, + { 15, 1, -1, 21, 96, -1, -1, -1, { "A[68]-8###", 4 }, "A-Series (Carrizo)" }, + { 15, 1, -1, 21, 96, -1, -1, -1, { "A1[02]-8###", 4 }, "A-Series (Carrizo)" }, + { 15, 5, -1, 21, 101, -1, -1, -1, { "A[68]-9###", 4 }, "A-Series (Bristol Ridge)" }, + { 15, 5, -1, 21, 101, -1, -1, -1, { "A1[02]-9###", 4 }, "A-Series (Bristol Ridge)" }, + { 15, 0, -1, 21, 112, 2, -1, -1, { "A[469]-9###", 4 }, "A-Series (Stoney Ridge)" }, + { 15, 0, -1, 21, 112, -1, -1, -1, { "E2-9###", 4 }, "E-Series (Stoney Ridge)" }, /* Family 16h: Jaguar Architecture (2013) */ - { 15, 0, -1, 22, 0, 2, -1, -1, FUSION_A, 0 , 0, "Kabini X2" }, - { 15, 0, -1, 22, 0, 4, -1, -1, FUSION_A, 0 , 0, "Kabini X4" }, - { 15, 0, -1, 22, 0, 2, -1, -1, NC, SEMPRON_|_X2 , 0, "Kabini X2" }, - { 15, 0, -1, 22, 0, 4, -1, -1, NC, SEMPRON_|_X4 , 0, "Kabini X4" }, - { 15, 0, -1, 22, 0, 4, -1, -1, NC, ATHLON_|_X4 , 0, "Kabini X4" }, + { 15, 0, -1, 22, 0, -1, -1, -1, { "E1-2###", 4 }, "E-Series (Kabini)" }, + { 15, 0, -1, 22, 0, -1, -1, -1, { "E2-3###", 4 }, "E-Series (Kabini)" }, + { 15, 0, -1, 22, 0, -1, -1, -1, { "A[46]-5###", 4 }, "A-Series (Kabini)" }, + { 15, 0, -1, 22, 0, -1, -1, -1, { "A4 PRO-3###", 6 }, "A-Series (Kabini)" }, + { 15, 0, -1, 22, 0, -1, -1, -1, { "Sempron(tm)", 2 }, "Sempron (Kabini)" }, + { 15, 0, -1, 22, 0, 4, -1, -1, { "Athlon(tm) 5###", 4 }, "Athlon X4 (Kabini)" }, + { 15, 0, -1, 22, 0, 4, -1, -1, { "Athlon(tm) X4", 4 }, "Athlon X4 (Kabini)" }, /* 2nd-gen, Puma core (2013): */ - { 15, 0, -1, 22, 48, 2, -1, -1, FUSION_E, 0 , 0, "Mullins X2" }, - { 15, 0, -1, 22, 48, 4, -1, -1, FUSION_A, 0 , 0, "Mullins X4" }, - { 15, 0, 1, 22, 48, 2, -1, -1, FUSION_A, 0 , 0, "Beema X2" }, - { 15, 0, 1, 22, 48, 4, -1, -1, FUSION_A, 0 , 0, "Beema X4" }, - { 15, 0, 1, 22, 48, 2, -1, -1, FUSION_GX, 0 , 0, "Steppe Eagle X2" }, - { 15, 0, 1, 22, 48, 4, -1, -1, FUSION_GX, 0 , 0, "Steppe Eagle X4" }, + { 15, 0, -1, 22, 48, 2, -1, -1, { "E1 Micro-62##T", 8 }, "E-Series (Mullins)" }, + { 15, 0, -1, 22, 48, 4, -1, -1, { "A4 Micro-64##T", 8 }, "A-Series (Mullins)" }, + { 15, 0, -1, 22, 48, 4, -1, -1, { "A10 Micro-67##T", 8 }, "A-Series (Mullins)" }, + { 15, 0, 1, 22, 48, -1, -1, -1, { "E[12]-6###", 4 }, "E-Series (Beema)" }, + { 15, 0, 1, 22, 48, -1, -1, -1, { "A[468]-6###", 4 }, "A-Series (Beema)" }, + { 15, 0, 1, 22, 48, -1, -1, -1, { "GX-###", 4 }, "G-Series (Steppe Eagle)" }, /* Family 17h */ /* Zen (2017) => https://en.wikichip.org/wiki/amd/microarchitectures/zen */ - { 15, -1, -1, 23, 1, -1, -1, -1, NC, EPYC_ , 0, "EPYC (Naples)" }, - { 15, -1, -1, 23, 1, -1, -1, -1, NC, RYZEN_TR_ , 0, "Threadripper (Whitehaven)" }, - { 15, -1, -1, 23, 1, -1, -1, -1, NC, RYZEN_|_7 , 0, "Ryzen 7 (Summit Ridge)" }, - { 15, -1, -1, 23, 1, -1, -1, -1, NC, RYZEN_|_5 , 0, "Ryzen 5 (Summit Ridge)" }, - { 15, -1, -1, 23, 1, -1, -1, -1, NC, RYZEN_|_3 , 0, "Ryzen 3 (Summit Ridge)" }, - { 15, -1, -1, 23, 17, -1, -1, -1, NC, RYZEN_|_7 , 0, "Ryzen 7 (Raven Ridge)" }, - { 15, -1, -1, 23, 17, -1, -1, -1, NC, RYZEN_|_5 , 0, "Ryzen 5 (Raven Ridge)" }, - { 15, -1, -1, 23, 17, -1, -1, -1, NC, RYZEN_|_3 , 0, "Ryzen 3 (Raven Ridge)" }, - { 15, -1, -1, 23, 17, -1, -1, -1, NC, ATHLON_ , 0, "Athlon (Raven Ridge)" }, - { 15, -1, -1, 23, 32, -1, -1, -1, NC, RYZEN_|_3 , 0, "Ryzen 3 (Dali)" }, - { 15, -1, -1, 23, 32, -1, -1, -1, NC, ATHLON_ , 0, "Athlon (Dali)" }, - { 15, -1, 1, 23, 32, -1, -1, -1, NC, 0 , 0, "Dali" }, + { 15, -1, -1, 23, 1, -1, -1, -1, { "EPYC 7##1", 4 }, "EPYC (Naples)" }, + { 15, -1, -1, 23, 1, -1, -1, -1, { "Threadripper 1###", 4 }, "Threadripper (Whitehaven)" }, + { 15, -1, -1, 23, 1, -1, -1, -1, { "Ryzen 7 1###", 6 }, "Ryzen 7 (Summit Ridge)" }, + { 15, -1, -1, 23, 1, -1, -1, -1, { "Ryzen 5 1###", 6 }, "Ryzen 5 (Summit Ridge)" }, + { 15, -1, -1, 23, 1, -1, -1, -1, { "Ryzen 3 1###", 6 }, "Ryzen 3 (Summit Ridge)" }, + { 15, -1, -1, 23, 17, -1, -1, -1, { "Ryzen 7 2###", 6 }, "Ryzen 7 (Raven Ridge)" }, + { 15, -1, -1, 23, 17, -1, -1, -1, { "Ryzen 5 2###", 6 }, "Ryzen 5 (Raven Ridge)" }, + { 15, -1, -1, 23, 17, -1, -1, -1, { "Ryzen 3 2###", 6 }, "Ryzen 3 (Raven Ridge)" }, + { 15, -1, -1, 23, 17, -1, -1, -1, { "Athlon", 2 }, "Athlon (Raven Ridge)" }, + { 15, -1, -1, 23, 32, -1, -1, -1, { "Ryzen 3 3###", 6 }, "Ryzen 3 (Dali)" }, + { 15, -1, -1, 23, 32, -1, -1, -1, { "Athlon", 2 }, "Athlon (Dali)" }, + { 15, -1, 1, 23, 32, -1, -1, -1, { "", 0 }, "Dali" }, /* AMD 3020e */ /* Zen+ (2018) => https://en.wikichip.org/wiki/amd/microarchitectures/zen%2B */ - { 15, -1, -1, 23, 8, -1, -1, -1, NC, RYZEN_TR_ , 0, "Threadripper (Colfax)" }, - { 15, -1, -1, 23, 8, -1, -1, -1, NC, RYZEN_|_7 , 0, "Ryzen 7 (Pinnacle Ridge)" }, - { 15, -1, -1, 23, 8, -1, -1, -1, NC, RYZEN_|_5 , 0, "Ryzen 5 (Pinnacle Ridge)" }, - { 15, -1, -1, 23, 8, -1, -1, -1, NC, RYZEN_|_3 , 0, "Ryzen 3 (Pinnacle Ridge)" }, - { 15, -1, -1, 23, 24, -1, -1, -1, NC, RYZEN_|_7 , 0, "Ryzen 7 (Picasso)" }, - { 15, -1, -1, 23, 24, -1, -1, -1, NC, RYZEN_|_5 , 0, "Ryzen 5 (Picasso)" }, - { 15, -1, -1, 23, 24, -1, -1, -1, NC, RYZEN_|_3 , 0, "Ryzen 3 (Picasso)" }, - { 15, -1, -1, 23, 24, -1, -1, -1, NC, ATHLON_ , 0, "Athlon (Picasso)" }, + { 15, -1, -1, 23, 8, -1, -1, -1, { "Threadripper 2###", 4 }, "Threadripper (Colfax)" }, + { 15, -1, -1, 23, 8, -1, -1, -1, { "Ryzen 7 2###", 6 }, "Ryzen 7 (Pinnacle Ridge)" }, + { 15, -1, -1, 23, 8, -1, -1, -1, { "Ryzen 5 2###", 6 }, "Ryzen 5 (Pinnacle Ridge)" }, + { 15, -1, -1, 23, 8, -1, -1, -1, { "Ryzen 3 2###", 6 }, "Ryzen 3 (Pinnacle Ridge)" }, + { 15, -1, -1, 23, 24, -1, -1, -1, { "Ryzen 7 3###", 6 }, "Ryzen 7 (Picasso)" }, + { 15, -1, -1, 23, 24, -1, -1, -1, { "Ryzen 5 3###", 6 }, "Ryzen 5 (Picasso)" }, + { 15, -1, -1, 23, 24, -1, -1, -1, { "Ryzen 3 3###", 6 }, "Ryzen 3 (Picasso)" }, + { 15, -1, -1, 23, 24, -1, -1, -1, { "Athlon", 2 }, "Athlon (Picasso)" }, /* Zen 2 (2019) => https://en.wikichip.org/wiki/amd/microarchitectures/zen_2 */ - { 15, -1, -1, 23, 49, -1, -1, -1, NC, EPYC_ , 0, "EPYC (Rome)" }, - { 15, -1, -1, 23, 49, -1, -1, -1, NC, RYZEN_TR_ , 0, "Threadripper (Castle Peak)" }, - { 15, -1, -1, 23, 113, -1, -1, -1, NC, RYZEN_|_9 , 0, "Ryzen 9 (Matisse)" }, - { 15, -1, -1, 23, 113, -1, -1, -1, NC, RYZEN_|_7 , 0, "Ryzen 7 (Matisse)" }, - { 15, -1, -1, 23, 113, -1, -1, -1, NC, RYZEN_|_5 , 0, "Ryzen 5 (Matisse)" }, - { 15, -1, -1, 23, 113, -1, -1, -1, NC, RYZEN_|_3 , 0, "Ryzen 3 (Matisse)" }, - { 15, -1, -1, 23, 96, -1, -1, -1, NC, RYZEN_|_9 , 0, "Ryzen 9 (Renoir)" }, - { 15, -1, -1, 23, 96, -1, -1, -1, NC, RYZEN_|_7 , 0, "Ryzen 7 (Renoir)" }, - { 15, -1, -1, 23, 96, -1, -1, -1, NC, RYZEN_|_5 , 0, "Ryzen 5 (Renoir)" }, - { 15, -1, -1, 23, 96, -1, -1, -1, NC, RYZEN_|_3 , 0, "Ryzen 3 (Renoir)" }, - { 15, -1, -1, 23, 104, -1, -1, -1, NC, RYZEN_|_7 , 0, "Ryzen 7 (Lucienne)" }, - { 15, -1, -1, 23, 104, -1, -1, -1, NC, RYZEN_|_5 , 0, "Ryzen 5 (Lucienne)" }, - { 15, -1, -1, 23, 104, -1, -1, -1, NC, RYZEN_|_3 , 0, "Ryzen 3 (Lucienne)" }, - { 15, -1, -1, 23, 71, -1, -1, -1, NC, 0 , 0, "Desktop Kit (Zen 2)" }, /* 4700S Desktop Kit */ - { 15, -1, -1, 23, 132, -1, -1, -1, NC, 0 , 0, "Desktop Kit (Zen 2)" }, /* 4800S Desktop Kit */ - { 15, -1, 2, 23, 144, -1, -1, -1, NC, 0 , 0, "Van Gogh" }, /* Custom APU 0405 */ - { 15, -1, 0, 23, 145, -1, -1, -1, NC, 0 , 0, "Van Gogh" }, /* Custom APU 0932 */ - { 15, -1, -1, 23, 160, -1, -1, -1, NC, RYZEN_|_5 , 0, "Ryzen 5 (Mendocino)" }, - { 15, -1, -1, 23, 160, -1, -1, -1, NC, RYZEN_|_3 , 0, "Ryzen 3 (Mendocino)" }, - { 15, -1, -1, 23, 160, -1, -1, -1, NC, ATHLON_ , 0, "Athlon (Mendocino)" }, + { 15, -1, -1, 23, 49, -1, -1, -1, { "EPYC 7##2", 4 }, "EPYC (Rome)" }, + { 15, -1, -1, 23, 49, -1, -1, -1, { "Threadripper 3###", 4 }, "Threadripper (Castle Peak)" }, + { 15, -1, -1, 23, 113, -1, -1, -1, { "Ryzen 9 3###", 6 }, "Ryzen 9 (Matisse)" }, + { 15, -1, -1, 23, 113, -1, -1, -1, { "Ryzen 7 3###", 6 }, "Ryzen 7 (Matisse)" }, + { 15, -1, -1, 23, 113, -1, -1, -1, { "Ryzen 5 3###", 6 }, "Ryzen 5 (Matisse)" }, + { 15, -1, -1, 23, 113, -1, -1, -1, { "Ryzen 3 3###", 6 }, "Ryzen 3 (Matisse)" }, + { 15, -1, -1, 23, 96, -1, -1, -1, { "Ryzen 9 4###", 6 }, "Ryzen 9 (Renoir)" }, + { 15, -1, -1, 23, 96, -1, -1, -1, { "Ryzen 7 4###", 6 }, "Ryzen 7 (Renoir)" }, + { 15, -1, -1, 23, 96, -1, -1, -1, { "Ryzen 5 4###", 6 }, "Ryzen 5 (Renoir)" }, + { 15, -1, -1, 23, 96, -1, -1, -1, { "Ryzen 3 4###", 6 }, "Ryzen 3 (Renoir)" }, + { 15, -1, -1, 23, 104, -1, -1, -1, { "Ryzen 7 5###", 6 }, "Ryzen 7 (Lucienne)" }, + { 15, -1, -1, 23, 104, -1, -1, -1, { "Ryzen 5 5###", 6 }, "Ryzen 5 (Lucienne)" }, + { 15, -1, -1, 23, 104, -1, -1, -1, { "Ryzen 3 5###", 6 }, "Ryzen 3 (Lucienne)" }, + { 15, -1, -1, 23, 71, -1, -1, -1, { "Desktop Kit", 4 }, "Desktop Kit (Zen 2)" }, /* 4700S Desktop Kit */ + { 15, -1, -1, 23, 132, -1, -1, -1, { "Desktop Kit", 4 }, "Desktop Kit (Zen 2)" }, /* 4800S Desktop Kit */ + { 15, -1, 2, 23, 144, -1, -1, -1, { "Custom APU", 4 }, "Van Gogh" }, /* Custom APU 0405 */ + { 15, -1, 0, 23, 145, -1, -1, -1, { "Custom APU", 4 }, "Van Gogh" }, /* Custom APU 0932 */ + { 15, -1, -1, 23, 160, -1, -1, -1, { "Ryzen 5 7###", 6 }, "Ryzen 5 (Mendocino)" }, + { 15, -1, -1, 23, 160, -1, -1, -1, { "Ryzen 3 7###", 6 }, "Ryzen 3 (Mendocino)" }, + { 15, -1, -1, 23, 160, -1, -1, -1, { "Athlon", 2 }, "Athlon (Mendocino)" }, /* Family 18h */ - /* Zen Architecture for Hygon (2018) => https://en.wikichip.org/wiki/amd/microarchitectures/zen */ - { 15, -1, -1, 24, 0, -1, -1, -1, NC, C86_|_7 , 0, "C86 7 (Dhyana)" }, - { 15, -1, -1, 24, 0, -1, -1, -1, NC, C86_|_5 , 0, "C86 5 (Dhyana)" }, - { 15, -1, -1, 24, 0, -1, -1, -1, NC, C86_|_3 , 0, "C86 3 (Dhyana)" }, + /* Zen Architecture for Hygon (2018) => https://en.wikichip.org/wiki/hygon/microarchitectures/dhyana */ + { 15, -1, -1, 24, 0, -1, -1, -1, { "C86", 2 }, "C86 (Dhyana)" }, /* Family 19h */ /* Zen 3 (2020) => https://en.wikichip.org/wiki/amd/microarchitectures/zen_3 */ - { 15, -1, -1, 25, 1, -1, -1, -1, NC, EPYC_ , 0, "EPYC (Milan)" }, - { 15, -1, -1, 25, 8, -1, -1, -1, NC, RYZEN_TR_ , 0, "Threadripper (Chagall)" }, - { 15, -1, -1, 25, 33, -1, -1, -1, NC, RYZEN_|_9 , 0, "Ryzen 9 (Vermeer)" }, - { 15, -1, -1, 25, 33, -1, -1, -1, NC, RYZEN_|_7 , 0, "Ryzen 7 (Vermeer)" }, - { 15, -1, -1, 25, 33, -1, -1, -1, NC, RYZEN_|_5 , 0, "Ryzen 5 (Vermeer)" }, - { 15, -1, -1, 25, 33, -1, -1, -1, NC, RYZEN_|_3 , 0, "Ryzen 3 (Vermeer)" }, - { 15, -1, -1, 25, 80, -1, -1, -1, NC, RYZEN_|_9 , 0, "Ryzen 9 (Cezanne)" }, - { 15, -1, -1, 25, 80, -1, -1, -1, NC, RYZEN_|_7 , 0, "Ryzen 7 (Cezanne)" }, - { 15, -1, -1, 25, 80, -1, -1, -1, NC, RYZEN_|_5 , 0, "Ryzen 5 (Cezanne)" }, - { 15, -1, -1, 25, 80, -1, -1, -1, NC, RYZEN_|_3 , 0, "Ryzen 3 (Cezanne)" }, + { 15, -1, -1, 25, 1, -1, -1, -1, { "EPYC 7##3", 4 }, "EPYC (Milan)" }, + { 15, -1, -1, 25, 8, -1, -1, -1, { "Threadripper 5###", 4 }, "Threadripper (Chagall)" }, + { 15, -1, -1, 25, 33, -1, -1, -1, { "Ryzen 9 5###", 6 }, "Ryzen 9 (Vermeer)" }, + { 15, -1, -1, 25, 33, -1, -1, -1, { "Ryzen 7 5###", 6 }, "Ryzen 7 (Vermeer)" }, + { 15, -1, -1, 25, 33, -1, -1, -1, { "Ryzen 5 5###", 6 }, "Ryzen 5 (Vermeer)" }, + { 15, -1, -1, 25, 33, -1, -1, -1, { "Ryzen 3 5###", 6 }, "Ryzen 3 (Vermeer)" }, + { 15, -1, -1, 25, 80, -1, -1, -1, { "Ryzen 9 5###", 6 }, "Ryzen 9 (Cezanne)" }, + { 15, -1, -1, 25, 80, -1, -1, -1, { "Ryzen 7 5###", 6 }, "Ryzen 7 (Cezanne)" }, + { 15, -1, -1, 25, 80, -1, -1, -1, { "Ryzen 5 5###", 6 }, "Ryzen 5 (Cezanne)" }, + { 15, -1, -1, 25, 80, -1, -1, -1, { "Ryzen 3 5###", 6 }, "Ryzen 3 (Cezanne)" }, /* Zen 3+ (2022) */ - { 15, -1, -1, 25, 68, -1, -1, -1, NC, RYZEN_|_9 , 0, "Ryzen 9 (Rembrandt)" }, - { 15, -1, -1, 25, 68, -1, -1, -1, NC, RYZEN_|_7 , 0, "Ryzen 7 (Rembrandt)" }, - { 15, -1, -1, 25, 68, -1, -1, -1, NC, RYZEN_|_5 , 0, "Ryzen 5 (Rembrandt)" }, - { 15, -1, -1, 25, 68, -1, -1, -1, NC, RYZEN_|_3 , 0, "Ryzen 3 (Rembrandt)" }, + { 15, -1, -1, 25, 68, -1, -1, -1, { "Ryzen 9 6###", 6 }, "Ryzen 9 (Rembrandt)" }, + { 15, -1, -1, 25, 68, -1, -1, -1, { "Ryzen 7 6###", 6 }, "Ryzen 7 (Rembrandt)" }, + { 15, -1, -1, 25, 68, -1, -1, -1, { "Ryzen 5 6###", 6 }, "Ryzen 5 (Rembrandt)" }, + { 15, -1, -1, 25, 68, -1, -1, -1, { "Ryzen 3 6###", 6 }, "Ryzen 3 (Rembrandt)" }, + { 15, -1, -1, 25, 68, -1, -1, -1, { "Ryzen 7 7###", 6 }, "Ryzen 7 (Rembrandt-R)" }, + { 15, -1, -1, 25, 68, -1, -1, -1, { "Ryzen 5 7###", 6 }, "Ryzen 5 (Rembrandt-R)" }, + { 15, -1, -1, 25, 68, -1, -1, -1, { "Ryzen 3 7###", 6 }, "Ryzen 3 (Rembrandt-R)" }, /* Zen 4 (2022) => https://en.wikichip.org/wiki/amd/microarchitectures/zen_4 */ - { 15, -1, -1, 25, 17, -1, -1, -1, NC, EPYC_ , 0, "EPYC (Genoa)" }, - { 15, -1, -1, 25, 24, -1, -1, -1, NC, RYZEN_TR_ , 0, "Threadripper (Storm Peak)" }, + { 15, -1, -1, 25, 17, -1, -1, -1, { "EPYC 9##4", 4 }, "EPYC (Genoa)" }, + { 15, -1, -1, 25, 24, -1, -1, -1, { "Threadripper 7###", 4 }, "Threadripper (Storm Peak)" }, /* => Raphael (7000 series, Zen 4/RDNA2 based) */ - { 15, -1, 2, 25, 97, -1, -1, -1, NC, RYZEN_|_9 , 0, "Ryzen 9 (Raphael)" }, - { 15, -1, 2, 25, 97, -1, -1, -1, NC, RYZEN_|_7 , 0, "Ryzen 7 (Raphael)" }, - { 15, -1, 2, 25, 97, -1, -1, -1, NC, RYZEN_|_5 , 0, "Ryzen 5 (Raphael)" }, - { 15, -1, 2, 25, 97, -1, -1, -1, NC, RYZEN_|_3 , 0, "Ryzen 3 (Raphael)" }, + { 15, -1, 2, 25, 97, -1, -1, -1, { "Ryzen 9 7###", 6 }, "Ryzen 9 (Raphael)" }, + { 15, -1, 2, 25, 97, -1, -1, -1, { "Ryzen 7 7###", 6 }, "Ryzen 7 (Raphael)" }, + { 15, -1, 2, 25, 97, -1, -1, -1, { "Ryzen 5 7###", 6 }, "Ryzen 5 (Raphael)" }, + { 15, -1, 2, 25, 97, -1, -1, -1, { "Ryzen 3 7###", 6 }, "Ryzen 3 (Raphael)" }, /* => Dragon Range (7045 series, Zen 4/RDNA2 based) */ - { 15, -1, -1, 25, 97, -1, -1, -1, NC, RYZEN_|_9|_H , 0, "Ryzen 9 (Dragon Range)" }, - { 15, -1, -1, 25, 97, -1, -1, -1, NC, RYZEN_|_7|_H , 0, "Ryzen 7 (Dragon Range)" }, - { 15, -1, -1, 25, 97, -1, -1, -1, NC, RYZEN_|_5|_H , 0, "Ryzen 5 (Dragon Range)" }, + { 15, -1, -1, 25, 97, -1, -1, -1, { "Ryzen 9 7###H", 8 }, "Ryzen 9 (Dragon Range)" }, + { 15, -1, -1, 25, 97, -1, -1, -1, { "Ryzen 7 7###H", 8 }, "Ryzen 7 (Dragon Range)" }, + { 15, -1, -1, 25, 97, -1, -1, -1, { "Ryzen 5 7###H", 8 }, "Ryzen 5 (Dragon Range)" }, /* => Phoenix (7040 series, Zen 4/RDNA3/XDNA based) */ - { 15, -1, -1, 25, 116, -1, -1, -1, NC, RYZEN_|_9|_H , 0, "Ryzen 9 (Phoenix)" }, - { 15, -1, -1, 25, 116, -1, -1, -1, NC, RYZEN_|_7|_H , 0, "Ryzen 7 (Phoenix)" }, - { 15, -1, -1, 25, 116, -1, -1, -1, NC, RYZEN_|_7|_U , 0, "Ryzen 7 (Phoenix)" }, - { 15, -1, -1, 25, 116, -1, -1, -1, NC, RYZEN_|_5|_H , 0, "Ryzen 5 (Phoenix)" }, - { 15, -1, -1, 25, 116, -1, -1, -1, NC, RYZEN_|_5|_U , 0, "Ryzen 5 (Phoenix)" }, - { 15, -1, -1, 25, 116, -1, -1, -1, NC, RYZEN_|_3|_U , 0, "Ryzen 3 (Phoenix)" }, - { 15, -1, -1, 25, 116, -1, -1, -1, NC, RYZEN_|_Z , 0, "Ryzen Z1 (Phoenix)" }, + { 15, -1, -1, 25, 116, -1, -1, -1, { "Ryzen 9 7###H", 8 }, "Ryzen 9 (Phoenix)" }, + { 15, -1, -1, 25, 116, -1, -1, -1, { "Ryzen 7 7###H", 8 }, "Ryzen 7 (Phoenix)" }, + { 15, -1, -1, 25, 116, -1, -1, -1, { "Ryzen 7 7###U", 8 }, "Ryzen 7 (Phoenix)" }, + { 15, -1, -1, 25, 116, -1, -1, -1, { "Ryzen 5 7###H", 8 }, "Ryzen 5 (Phoenix)" }, + { 15, -1, -1, 25, 116, -1, -1, -1, { "Ryzen 5 7###U", 8 }, "Ryzen 5 (Phoenix)" }, + { 15, -1, -1, 25, 116, -1, -1, -1, { "Ryzen 3 7###U", 8 }, "Ryzen 3 (Phoenix)" }, + { 15, -1, -1, 25, 116, -1, -1, -1, { "Ryzen Z1", 4 }, "Ryzen Z1 (Phoenix)" }, /* => Phoenix (8000 series, Zen 4 based) */ - { 15, -1, -1, 25, 117, -1, -1, -1, NC, RYZEN_|_7|_F , 0, "Ryzen 7 (Phoenix)" }, - { 15, -1, -1, 25, 117, -1, -1, -1, NC, RYZEN_|_5|_F , 0, "Ryzen 5 (Phoenix)" }, + { 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 7 8###F", 8 }, "Ryzen 7 (Phoenix)" }, + { 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 5 8###F", 8 }, "Ryzen 5 (Phoenix)" }, /* => Phoenix (8000 series with Radeon Graphics, Zen 4/RDNA3/XDNA based) */ - { 15, -1, -1, 25, 117, -1, -1, -1, NC, RYZEN_|_9|_G , 0, "Ryzen 9 (Phoenix)" }, - { 15, -1, -1, 25, 117, -1, -1, -1, NC, RYZEN_|_7|_G , 0, "Ryzen 7 (Phoenix)" }, - { 15, -1, -1, 25, 117, -1, -1, -1, NC, RYZEN_|_5|_G , 0, "Ryzen 5 (Phoenix)" }, - { 15, -1, -1, 25, 117, -1, -1, -1, NC, RYZEN_|_3|_G , 0, "Ryzen 3 (Phoenix)" }, + { 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 9 8###G", 8 }, "Ryzen 9 (Phoenix)" }, + { 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 7 8###G", 8 }, "Ryzen 7 (Phoenix)" }, + { 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 5 8###G", 8 }, "Ryzen 5 (Phoenix)" }, + { 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 3 8###G", 8 }, "Ryzen 3 (Phoenix)" }, /* => Hawk Point (8040 series, Zen 4/RDNA3/XDNA based) */ - { 15, -1, -1, 25, 117, -1, -1, -1, NC, RYZEN_|_9|_H , 0, "Ryzen 9 (Hawk Point)" }, - { 15, -1, -1, 25, 117, -1, -1, -1, NC, RYZEN_|_7|_H , 0, "Ryzen 7 (Hawk Point)" }, - { 15, -1, -1, 25, 117, -1, -1, -1, NC, RYZEN_|_7|_U , 0, "Ryzen 7 (Hawk Point)" }, - { 15, -1, -1, 25, 117, -1, -1, -1, NC, RYZEN_|_5|_H , 0, "Ryzen 5 (Hawk Point)" }, - { 15, -1, -1, 25, 117, -1, -1, -1, NC, RYZEN_|_5|_U , 0, "Ryzen 5 (Hawk Point)" }, - { 15, -1, -1, 25, 117, -1, -1, -1, NC, RYZEN_|_3|_U , 0, "Ryzen 3 (Hawk Point)" }, + { 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 9 8###H", 8 }, "Ryzen 9 (Hawk Point)" }, + { 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 7 8###H", 8 }, "Ryzen 7 (Hawk Point)" }, + { 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 7 8###U", 8 }, "Ryzen 7 (Hawk Point)" }, + { 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 5 8###H", 8 }, "Ryzen 5 (Hawk Point)" }, + { 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 5 8###U", 8 }, "Ryzen 5 (Hawk Point)" }, + { 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 3 8###U", 8 }, "Ryzen 3 (Hawk Point)" }, /* Zen 5 (2024) => https://en.wikichip.org/wiki/amd/microarchitectures/zen_5 */ - { 15, -1, -1, 26, 2, -1, -1, -1, NC, EPYC_ , 0, "EPYC (Turin)" }, - { 15, -1, -1, 26, 17, -1, -1, -1, NC, EPYC_ , 0, "EPYC (Turin Dense)" }, + { 15, -1, -1, 26, 2, -1, -1, -1, { "EPYC 9##5", 4 }, "EPYC (Turin)" }, + { 15, -1, -1, 26, 17, -1, -1, -1, { "EPYC 9##5", 4 }, "EPYC (Turin Dense)" }, /* => Granite Ridge (9000 series, Zen 5 based) */ - { 15, -1, -1, 26, 68, -1, -1, -1, NC, RYZEN_|_9 , 0, "Ryzen 9 (Granite Ridge)" }, - { 15, -1, -1, 26, 68, -1, -1, -1, NC, RYZEN_|_7 , 0, "Ryzen 7 (Granite Ridge)" }, - { 15, -1, -1, 26, 68, -1, -1, -1, NC, RYZEN_|_5 , 0, "Ryzen 5 (Granite Ridge)" }, - { 15, -1, -1, 26, 68, -1, -1, -1, NC, RYZEN_|_3 , 0, "Ryzen 3 (Granite Ridge)" }, + { 15, -1, -1, 26, 68, -1, -1, -1, { "Ryzen 9 9###", 6 }, "Ryzen 9 (Granite Ridge)" }, + { 15, -1, -1, 26, 68, -1, -1, -1, { "Ryzen 7 9###", 6 }, "Ryzen 7 (Granite Ridge)" }, + { 15, -1, -1, 26, 68, -1, -1, -1, { "Ryzen 5 9###", 6 }, "Ryzen 5 (Granite Ridge)" }, + { 15, -1, -1, 26, 68, -1, -1, -1, { "Ryzen 3 9###", 6 }, "Ryzen 3 (Granite Ridge)" }, /* => Strix Point (Zen 5/RDNA3.5/XDNA2 based) */ - { 15, -1, -1, 26, 36, -1, -1, -1, NC, RYZEN_|_AI_|_9 , 0, "Ryzen AI 9 (Strix Point)" }, - { 15, -1, -1, 26, 36, -1, -1, -1, NC, RYZEN_|_AI_|_7 , 0, "Ryzen AI 7 (Strix Point)" }, - /* F M S EF EM #cores L2$ L3$ BC ModelBits ModelCode Name */ + { 15, -1, -1, 26, 36, -1, -1, -1, { "Ryzen AI 9", 6 }, "Ryzen AI 9 (Strix Point)" }, + { 15, -1, -1, 26, 36, -1, -1, -1, { "Ryzen AI 7", 6 }, "Ryzen AI 7 (Strix Point)" }, +// F M S EF EM #cores L2$ L3$ Pattern Name }; @@ -525,163 +506,6 @@ static void decode_amd_number_of_cores(struct cpu_raw_data_t* raw, struct cpu_id } } -static int amd_has_turion_modelname(const char *bs) -{ - /* We search for something like TL-60. Ahh, I miss regexes...*/ - int i, l, k; - char code[3] = {0}; - const char* codes[] = { "ML", "MT", "MK", "TK", "TL", "RM", "ZM", "" }; - l = (int) strlen(bs); - for (i = 3; i < l - 2; i++) { - if (bs[i] == '-' && - isupper(bs[i-1]) && isupper(bs[i-2]) && !isupper(bs[i-3]) && - isdigit(bs[i+1]) && isdigit(bs[i+2]) && !isdigit(bs[i+3])) - { - code[0] = bs[i-2]; - code[1] = bs[i-1]; - for (k = 0; codes[k][0]; k++) - if (!strcmp(codes[k], code)) return 1; - } - } - return 0; -} - -static struct amd_code_and_bits_t decode_amd_codename_part1(const char *bs) -{ - amd_code_t code = (amd_code_t) NC; - struct amd_code_and_bits_t result; - uint64_t bits = 0; - int i = 0; - const size_t n = strlen(bs); - - const struct { amd_code_t c; const char *search; } code_matchtable[] = { - { PHENOM2, "Phenom(tm) II" }, - { PHENOM, "Phenom(tm)" }, - { FUSION_C, "C-##" }, - { FUSION_E, "E-###" }, - { FUSION_Z, "Z-##" }, - { FUSION_EA, "[EA]#-####" }, - { FUSION_RX, "RX-###" }, - { FUSION_GX, "GX-###" }, - }; - - const struct { uint64_t bit; const char *search; } bit_matchtable[] = { - { _X2, "Dual[- ]Core" }, - { _X2, " X2 " }, - { _X3, " X3 " }, - { _X4, " X4 " }, - { OPTERON_, "Opteron" }, - { ATHLON_, "Athlon" }, - { SEMPRON_, "Sempron(tm)" }, - { DURON_, "Duron" }, - { _64_, " 64 " }, - { _FX, " FX" }, - { _MP_, " MP" }, - { ATHLON_|_64_, "Athlon(tm) 64" }, - { ATHLON_|_64_, "Athlon(tm) II X" }, - { ATHLON_|_64_, "Athlon(tm) X#" }, - { TURION_, "Turion" }, - { MOBILE_, "[mM]obile" }, - { _XP_, "XP" }, - { _M_, "XP-M" }, - { _LV_, "(LV)" }, - { _APU_, " APU " }, - { EPYC_, "EPYC" }, - { RYZEN_TR_, "Ryzen Threadripper" }, - { C86_, "C86" }, - }; - - for (i = 0; i < COUNT_OF(bit_matchtable); i++) { - if (match_pattern(bs, bit_matchtable[i].search)) - bits |= bit_matchtable[i].bit; - } - if (amd_has_turion_modelname(bs)) { - bits |= TURION_; - } - if (((i = match_pattern(bs, "Ryzen [3579Z]")) != 0) || ((i = match_pattern(bs, "Ryzen AI [3579]")) != 0)) { - bits |= RYZEN_; - i--; - if ((bs[i + 6] == 'A') && (bs[i + 7] == 'I')) { - bits |= _AI_; - i += 3; // "AI " offset - } - switch (bs[i + 6]) { - case '3': bits |= _3; break; - case '5': bits |= _5; break; - case '7': bits |= _7; break; - case '9': bits |= _9; break; - case 'Z': bits |= _Z; break; - } - /* Stop the loop after a whitespace to avoid to read some words like "Graphics". - Example: bs="AMD Ryzen 7 8845HS w/ Radeon 780M Graphics" - => loop i from 12 to 17, i.e. "8845HS" in such example - */ - for(i = i + 8; (i < n) && (bs[i] != ' '); i++) { - switch (bs[i]) { - case 'F': bits |= _F; break; - case 'G': bits |= _G; break; - case 'H': bits |= _H; break; - case 'S': bits |= _S; break; - case 'U': bits |= _U; break; - case 'X': bits |= _X; break; - } - } - } - - if ((i = match_pattern(bs, "C86 [357]")) != 0) { - bits |= C86_; - i--; - switch (bs[i + 6]) { - case '3': bits |= _3; break; - case '5': bits |= _5; break; - case '7': bits |= _7; break; - } - } - - for (i = 0; i < COUNT_OF(code_matchtable); i++) - if (match_pattern(bs, code_matchtable[i].search)) { - code = code_matchtable[i].c; - break; - } - - result.code = code; - result.bits = bits; - return result; -} - -static void decode_amd_codename(struct cpu_id_t* data, struct internal_id_info_t* internal) -{ - struct amd_code_and_bits_t code_and_bits = decode_amd_codename_part1(data->brand_str); - int i = 0; - char* code_str = NULL; - int model_code = 0; - - for (i = 0; i < COUNT_OF(amd_code_str); i++) { - if (code_and_bits.code == amd_code_str[i].code) { - code_str = amd_code_str[i].str; - break; - } - } - if (/*code == ATHLON_64_X2*/ match_all(code_and_bits.bits, ATHLON_|_64_|_X2) && data->l2_cache < 512) { - code_and_bits.bits &= ~(ATHLON_ | _64_); - code_and_bits.bits |= SEMPRON_; - } - if (code_str) - debugf(2, "Detected AMD brand code: %d (%s)\n", code_and_bits.code, code_str); - else - debugf(2, "Detected AMD brand code: %d\n", code_and_bits.code); - - if (code_and_bits.bits) { - debugf(2, "Detected AMD bits: "); - debug_print_lbits(2, code_and_bits.bits); - } - - internal->code.amd = code_and_bits.code; - internal->bits = code_and_bits.bits; - internal->score = match_cpu_codename(cpudb_amd, COUNT_OF(cpudb_amd), data, code_and_bits.code, - code_and_bits.bits, model_code); -} - int cpuid_identify_amd(struct cpu_raw_data_t* raw, struct cpu_id_t* data, struct internal_id_info_t* internal) { load_amd_features(raw, data); @@ -690,9 +514,10 @@ int cpuid_identify_amd(struct cpu_raw_data_t* raw, struct cpu_id_t* data, struct else decode_amd_cache_info(raw, data); decode_amd_number_of_cores(raw, data); - decode_amd_codename(data, internal); decode_architecture_version_x86(data); data->purpose = cpuid_identify_purpose_amd(raw); + internal->score = match_cpu_codename(cpudb_amd, COUNT_OF(cpudb_amd), data); + return 0; } diff --git a/libcpuid/recog_arm.c b/libcpuid/recog_arm.c index 7facfa9..ed6e8fc 100644 --- a/libcpuid/recog_arm.c +++ b/libcpuid/recog_arm.c @@ -27,9 +27,9 @@ #include #include #include +#include #include #include "libcpuid.h" -#include "libcpuid_ctype.h" #include "libcpuid_util.h" #include "libcpuid_internal.h" #include "recog_arm.h" diff --git a/libcpuid/recog_centaur.c b/libcpuid/recog_centaur.c index 10f14cf..17c3bb2 100644 --- a/libcpuid/recog_centaur.c +++ b/libcpuid/recog_centaur.c @@ -26,211 +26,72 @@ #include #include +#include #include "libcpuid.h" -#include "libcpuid_ctype.h" #include "libcpuid_util.h" #include "libcpuid_internal.h" #include "recog_centaur.h" -const struct centaur_code_str { centaur_code_t code; char *str; } centaur_code_str[] = { - #define CODE(x) { x, #x } - #define CODE2(x, y) CODE(x) - #include "centaur_code_t.h" - #undef CODE -}; - -typedef struct { - int code; - uint64_t bits; -} centaur_code_and_bits_t; - -enum _centaur_model_t { - UNKNOWN = -1, - _4000 = 100, /* Zhaoxin KaiXian (KX) / KaisHeng (KH) Zhangjiang */ - _5000, /* Zhaoxin KaiXian (KX) WuDaoKou */ - _6000, /* Zhaoxin KaiXian (KX) LuJiaZui */ - _7000, /* Zhaoxin KaiXian (KX) Yongfeng */ - _20000 = 1000, /* Zhaoxin KaisHeng (KH) WuDaoKou */ - _30000, /* Zhaoxin KaisHeng (KH) LuJiaZui */ - _40000, /* Zhaoxin KaisHeng (KH) Yongfeng */ -}; -typedef enum _centaur_model_t centaur_model_t; const struct match_entry_t cpudb_centaur[] = { -// F M S EF EM #cores L2$ L3$ BC ModelBits ModelCode Name - { -1, -1, -1, -1, -1, -1, -1, -1, NC, 0, 0, "Unknown Centaur CPU" }, -// F M S EF EM #cores L2$ L3$ BC ModelBits ModelCode Name +// F M S EF EM #cores L2$ L3$ Pattern Name + { -1, -1, -1, -1, -1, -1, -1, -1, { "", 0 }, "Unknown Centaur CPU" }, +// F M S EF EM #cores L2$ L3$ Pattern Name /* VIA */ -// F M S EF EM #cores L2$ L3$ BC ModelBits ModelCode Name - { 6, -1, -1, -1, -1, -1, -1, -1, VIA, 0 , 0, "Unknown VIA CPU" }, +// F M S EF EM #cores L2$ L3$ Pattern Name + { 6, -1, -1, -1, -1, -1, -1, -1, { "VIA", 2 }, "Unknown VIA CPU" }, + /* Samuel (2000, 180 nm) */ - { 6, 6, -1, -1, -1, -1, -1, -1, VIA, SAMUEL_ , 0, "VIA Cyrix III (Samuel)" }, + { 6, 6, -1, -1, -1, -1, -1, -1, { "VIA Samuel", 4 }, "VIA Cyrix III (Samuel)" }, /* Samuel 2 (2001, 150 nm) */ - { 6, 7, -1, -1, -1, -1, -1, -1, VIA, SAMUEL_ , 0, "VIA C3 (Samuel 2)" }, + { 6, 7, -1, -1, -1, -1, -1, -1, { "VIA Samuel 2", 6 }, "VIA C3 (Samuel 2)" }, /* Ezra (2001, 130 nm) */ - { 6, 7, -1, -1, -1, -1, -1, -1, VIA, EZRA_ , 0, "VIA C3 (Ezra)" }, - { 6, 8, -1, -1, -1, -1, -1, -1, VIA, EZRA_ , 0, "VIA C3 (Ezra-T)" }, + { 6, 7, -1, -1, -1, -1, -1, -1, { "VIA Ezra", 4 }, "VIA C3 (Ezra)" }, + { 6, 8, -1, -1, -1, -1, -1, -1, { "VIA C3 Ezra", 6 }, "VIA C3 (Ezra-T)" }, /* Nehemiah (2003, 130 nm) */ - { 6, 9, -1, -1, -1, -1, -1, -1, VIA, NEHEMIAH_ , 0, "VIA C3 (Nehemiah)" }, + { 6, 9, -1, -1, -1, -1, -1, -1, { "VIA Nehemiah", 4 }, "VIA C3 (Nehemiah)" }, /* Esther (2005, 90 nm) */ - { 6, 10, -1, -1, -1, -1, -1, -1, VIA, ESTHER_ , 0, "VIA C7 (Esther)" }, - { 6, 13, -1, -1, -1, -1, -1, -1, VIA, ESTHER_ , 0, "VIA C7-M (Esther)" }, + { 6, 10, -1, -1, -1, -1, -1, -1, { "VIA Esther", 4 }, "VIA C7 (Esther)" }, + { 6, 13, -1, -1, -1, -1, -1, -1, { "VIA C7-M", 4 }, "VIA C7-M (Esther)" }, /* Isaiah (2008, 65 nm) */ - { 6, 15, -1, -1, -1, -1, -1, -1, VIA, CNA_ , 0, "VIA Nano (Isaiah)" }, - { 6, 15, -1, -1, -1, 1, -1, -1, VIA, NANO_ , 0, "VIA Nano (Isaiah)" }, - { 6, 15, -1, -1, -1, 2, -1, -1, VIA, NANO_ , 0, "VIA Nano X2 (Isaiah)" }, - { 6, 15, -1, -1, -1, -1, -1, -1, VIA, QUADCORE_ , 0, "VIA Nano X4 (Isaiah)" }, - { 6, 15, -1, -1, -1, 4, -1, -1, VIA, EDEN_ , 0, "VIA Eden X4 (Isaiah)" }, -// F M S EF EM #cores L2$ L3$ BC ModelBits ModelCode Name + { 6, 15, -1, -1, -1, -1, -1, -1, { "VIA Nano", 4 }, "VIA Nano (Isaiah)" }, + { 6, 15, -1, -1, -1, 1, -1, -1, { "VIA Nano", 4 }, "VIA Nano (Isaiah)" }, + { 6, 15, -1, -1, -1, 2, -1, -1, { "VIA Nano", 4 }, "VIA Nano X2 (Isaiah)" }, + { 6, 15, -1, -1, -1, -1, -1, -1, { "VIA QuadCore", 4 }, "VIA Nano X4 (Isaiah)" }, + { 6, 15, -1, -1, -1, 4, -1, -1, { "VIA Eden X4", 6 }, "VIA Eden X4 (Isaiah)" }, +// F M S EF EM #cores L2$ L3$ Pattern Name /* Zhaoxin */ -// F M S EF EM #cores L2$ L3$ BC ModelBits ModelCode Name - { 7, -1, -1, -1, -1, -1, -1, -1, ZHAOXIN, 0 , 0, "Unknown Zhaoxin CPU" }, +// F M S EF EM #cores L2$ L3$ Pattern Name + { 7, -1, -1, -1, -1, -1, -1, -1, {"ZHAOXIN", 2 }, "Unknown Zhaoxin CPU" }, + /* Zhangjiang (2015, 28 nm) */ - { 7, -1, -1, -1, 15, -1, -1, -1, ZHAOXIN, KAISHENG_|_KH_|__C, 0, "Zhaoxin KaisHeng (ZhangJiang)" }, // C+ (4000) - { 7, -1, -1, -1, 15, -1, -1, -1, ZHAOXIN, KAIXIAN_|_ZX_|__C , 0, "Zhaoxin KaiXian (ZhangJiang)" }, // C/C+ (4000) + { 7, -1, -1, -1, 15, -1, -1, -1, { "ZHAOXIN KaisHeng KH-C", 8 }, "Zhaoxin KaisHeng (ZhangJiang)" }, // C+ (4000) + { 7, -1, -1, -1, 15, -1, -1, -1, { "ZHAOXIN KaiXian ZX-C", 8 }, "Zhaoxin KaiXian (ZhangJiang)" }, // C/C+ (4000) /* WuDaoKou (2017, 28 nm) */ - { 7, -1, -1, -1, 27, -1, -1, -1, ZHAOXIN, KAISHENG_|_KH_ , _20000, "Zhaoxin KaisHeng (WuDaoKou)" }, // KH (20000) - { 7, -1, -1, -1, 27, -1, -1, -1, ZHAOXIN, KAIXIAN_|_KX_ , _5000, "Zhaoxin KaiXian (WuDaoKou)" }, // KX (5000) + { 7, -1, -1, -1, 27, -1, -1, -1, { "ZHAOXIN KaisHeng KH-20###", 8 }, "Zhaoxin KaisHeng (WuDaoKou)" }, // KH (20000) + { 7, -1, -1, -1, 27, -1, -1, -1, { "ZHAOXIN KaiXian KX-5###", 8 }, "Zhaoxin KaiXian (WuDaoKou)" }, // KX (5000) + { 7, -1, -1, -1, 27, -1, -1, -1, { "ZHAOXIN KaiXian KX-U5###", 8 }, "Zhaoxin KaiXian (WuDaoKou)" }, // KX (U5000) /* LuJiaZui (2019, 16 nm) */ - { 7, -1, -1, -1, 59, -1, -1, -1, ZHAOXIN, KAISHENG_|_KH_ , _30000, "Zhaoxin KaisHeng (LuJiaZui)" }, // KH (30000) - { 7, -1, -1, -1, 59, -1, -1, -1, ZHAOXIN, KAIXIAN_|_KX_ , _6000, "Zhaoxin KaiXian (LuJiaZui)" }, // KX (6000) + { 7, -1, -1, -1, 59, -1, -1, -1, { "ZHAOXIN KaisHeng KH-30###", 8 }, "Zhaoxin KaisHeng (LuJiaZui)" }, // KH (30000) + { 7, -1, -1, -1, 59, -1, -1, -1, { "ZHAOXIN KaiXian KX-6###", 8 }, "Zhaoxin KaiXian (LuJiaZui)" }, // KX (6000) + { 7, -1, -1, -1, 59, -1, -1, -1, { "ZHAOXIN KaiXian KX-U6###", 8 }, "Zhaoxin KaiXian (LuJiaZui)" }, // KX (U6000) /* Yongfeng (2022, 16 nm) */ - { 7, -1, -1, -1, 91, -1, -1, -1, ZHAOXIN, KAISHENG_|_KH_ , _40000, "Zhaoxin KaisHeng (Yongfeng)" }, // KH (40000) - { 7, -1, -1, -1, 91, -1, -1, -1, ZHAOXIN, KAIXIAN_|_KX_ , _7000, "Zhaoxin KaiXian (Yongfeng)" }, // KX (7000) -// F M S EF EM #cores L2$ L3$ BC ModelBits ModelCode Name + { 7, -1, -1, -1, 91, -1, -1, -1, { "ZHAOXIN KaisHeng KH-40###", 8 }, "Zhaoxin KaisHeng (Yongfeng)" }, // KH (40000) + { 7, -1, -1, -1, 91, -1, -1, -1, { "ZHAOXIN KaiXian KX-7###", 8 }, "Zhaoxin KaiXian (Yongfeng)" }, // KX (7000) +// F M S EF EM #cores L2$ L3$ Pattern Name }; -static centaur_code_and_bits_t get_brand_code_and_bits(struct cpu_id_t* data) -{ - centaur_code_t code = (centaur_code_t) NC; - centaur_code_and_bits_t result; - uint64_t bits = 0; - int i = 0; - - const char* bs = data->brand_str; - const struct { centaur_code_t c; const char *search; } code_matchtable[] = { - { VIA, "VIA" }, - { ZHAOXIN, "ZHAOXIN" }, - }; - - const struct { uint64_t bit; const char* search; } bit_matchtable_via[] = { - { SAMUEL_, "Samuel" }, - { EZRA_, "Ezra" }, - { NEHEMIAH_, "Nehemiah" }, - { ESTHER_, "Esther" }, - { EDEN_, "Eden" }, - { CNA_, "CNA" }, - { NANO_, "Nano" }, - { QUADCORE_, "QuadCore" }, - }; - const struct { uint64_t bit; const char* search; } bit_matchtable_zhaoxin[] = { - { KAISHENG_, "KaisHeng" }, - { KAIXIAN_, "KaiXian" }, - { _KH_, "KH" }, - { _KX_, "KX" }, - { _ZX_, "ZX" }, - { __C, "-C" }, - { _D, "-D" }, - { _E, "-E" }, - }; - - for (i = 0; i < COUNT_OF(code_matchtable); i++) { - if (match_pattern(bs, code_matchtable[i].search)) { - code = code_matchtable[i].c; - break; - } - } - - if (code == VIA) { - for (i = 0; i < COUNT_OF(bit_matchtable_via); i++) { - if (match_pattern(bs, bit_matchtable_via[i].search)) - bits |= bit_matchtable_via[i].bit; - } - } - else if (code == ZHAOXIN) { - for (i = 0; i < COUNT_OF(bit_matchtable_zhaoxin); i++) { - if (match_pattern(bs, bit_matchtable_zhaoxin[i].search)) - bits |= bit_matchtable_zhaoxin[i].bit; - } - } - - result.code = code; - result.bits = bits; - return result; -} - -static centaur_model_t get_model_code(struct cpu_id_t* data, centaur_code_and_bits_t brand) -{ - int i = 0; - int l = (int) strlen(data->brand_str); - const char *bs = data->brand_str; - - if (brand.code == ZHAOXIN) { - if ((i = match_pattern(bs, "KaiSheng KH-")) != 0) { - i += 11; - if (i + 4 >= l) return UNKNOWN; - switch(bs[i]) { - case '2': return _20000; - case '3': return _30000; - case '4': return _40000; - default: return UNKNOWN; - } - } - else if ((i = match_pattern(bs, "KaiXian KX-")) != 0) { - i += 10; - if (bs[i] == 'U') i++; - if (i + 3 >= l) return UNKNOWN; - switch(bs[i]) { - case '4': return _4000; - case '5': return _5000; - case '6': return _6000; - case '7': return _7000; - default: return UNKNOWN; - } - } - } - - return UNKNOWN; -} - int cpuid_identify_centaur(struct cpu_raw_data_t* raw, struct cpu_id_t* data, struct internal_id_info_t* internal) { - centaur_code_and_bits_t brand; - centaur_model_t model_code; - int i; - char* brand_code_str = NULL; - if (raw->basic_cpuid[0][EAX] >= 4) decode_deterministic_cache_info_x86(raw->intel_fn4, MAX_INTELFN4_LEVEL, data, internal); decode_number_of_cores_x86(raw, data); decode_architecture_version_x86(data); - - brand = get_brand_code_and_bits(data); - model_code = get_model_code(data, brand); - for (i = 0; i < COUNT_OF(centaur_code_str); i++) { - if (brand.code == centaur_code_str[i].code) { - brand_code_str = centaur_code_str[i].str; - break; - } - } - if (brand_code_str) - debugf(2, "Detected Centaur brand code: %d (%s)\n", brand.code, brand_code_str); - else - debugf(2, "Detected Centaur brand code: %d\n", brand.code); - if (brand.bits) { - debugf(2, "Detected Centaur bits: "); - debug_print_lbits(2, brand.bits); - } - debugf(2, "Detected Centaur model code: %d\n", model_code); - - internal->code.centaur = brand.code; - internal->bits = brand.bits; - internal->score = match_cpu_codename(cpudb_centaur, COUNT_OF(cpudb_centaur), data, - brand.code, brand.bits, model_code); + internal->score = match_cpu_codename(cpudb_centaur, COUNT_OF(cpudb_centaur), data); return 0; } diff --git a/libcpuid/recog_intel.c b/libcpuid/recog_intel.c index 1e7e3d9..540ba1c 100644 --- a/libcpuid/recog_intel.c +++ b/libcpuid/recog_intel.c @@ -24,577 +24,507 @@ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include +#include #include "libcpuid.h" -#include "libcpuid_ctype.h" #include "libcpuid_util.h" #include "libcpuid_internal.h" #include "recog_intel.h" -const struct intel_bcode_str { intel_code_t code; char *str; } intel_bcode_str[] = { - #define CODE(x) { x, #x } - #define CODE2(x, y) CODE(x) - #include "intel_code_t.h" - #undef CODE -}; - -typedef struct { - int code; - uint64_t bits; -} intel_code_and_bits_t; - -enum _intel_model_t { - UNKNOWN = -1, - _3000 = 100, - _3100, - _3200, - X3200, - _3300, - X3300, - _5100, - _5200, - _5300, - _5400, - _2xxx, /* Core i[357] 2xxx */ - _3xxx, /* Core i[357] 3xxx */ - _4xxx, /* Core i[357] 4xxx */ - _5xxx, /* Core i[357] 5xxx */ - _6xxx, /* Core i[357] 6xxx */ - _7xxx, /* Core i[3579] 7xxx */ - _8xxx, /* Core i[3579] 8xxx */ - _9xxx, /* Core i[3579] 9xxx */ - _10xxx, /* Core i[3579] 10xxx */ - _11xxx, /* Core i[3579] 11xxx */ - _12xxx, /* Core i[3579] 12xxx */ - _13xxx, /* Core i[3579] 13xxx */ - _14xxx, /* Core i[3579] 14xxx */ - _x1xx, /* Xeon Bronze/Silver/Gold/Platinum x1xx */ - _x2xx, /* Xeon Bronze/Silver/Gold/Platinum x2xx */ - _x3xx, /* Xeon Bronze/Silver/Gold/Platinum x3xx */ - _x4xx, /* Xeon Bronze/Silver/Gold/Platinum/Max x4xx */ - _x5xx, /* Xeon Bronze/Silver/Gold/Platinum x5xx */ - _1xx, /* Core Ultra [3579] 1xx */ - _2xx, /* Core Ultra [3579] 2xx */ - _x5x, /* Intel Processor/Core 3 x5x (Twin lake-N) */ -}; -typedef enum _intel_model_t intel_model_t; const struct match_entry_t cpudb_intel[] = { -// F M S EF EM #cores L2$ L3$ BC ModelBits ModelCode Name - { -1, -1, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Unknown Intel CPU" }, +// F M S EF EM #cores L2$ L3$ Pattern Name + { -1, -1, -1, -1, -1, 1, -1, -1, { "", 0 }, "Unknown Intel CPU" }, /* i486 */ - { 4, -1, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Unknown i486" }, - { 4, 0, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "i486 DX-25/33" }, - { 4, 1, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "i486 DX-50" }, - { 4, 2, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "i486 SX" }, - { 4, 3, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "i486 DX2" }, - { 4, 4, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "i486 SL" }, - { 4, 5, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "i486 SX2" }, - { 4, 7, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "i486 DX2 WriteBack" }, - { 4, 8, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "i486 DX4" }, - { 4, 9, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "i486 DX4 WriteBack" }, + { 4, -1, -1, -1, -1, 1, -1, -1, { "", 0 }, "Unknown i486" }, + { 4, 0, -1, -1, -1, 1, -1, -1, { "", 0 }, "i486 DX-25/33" }, + { 4, 1, -1, -1, -1, 1, -1, -1, { "", 0 }, "i486 DX-50" }, + { 4, 2, -1, -1, -1, 1, -1, -1, { "", 0 }, "i486 SX" }, + { 4, 3, -1, -1, -1, 1, -1, -1, { "", 0 }, "i486 DX2" }, + { 4, 4, -1, -1, -1, 1, -1, -1, { "", 0 }, "i486 SL" }, + { 4, 5, -1, -1, -1, 1, -1, -1, { "", 0 }, "i486 SX2" }, + { 4, 7, -1, -1, -1, 1, -1, -1, { "", 0 }, "i486 DX2 WriteBack" }, + { 4, 8, -1, -1, -1, 1, -1, -1, { "", 0 }, "i486 DX4" }, + { 4, 9, -1, -1, -1, 1, -1, -1, { "", 0 }, "i486 DX4 WriteBack" }, - /* All Pentia: - Pentium 1 */ - { 5, -1, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Unknown Pentium" }, - { 5, 0, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Pentium A-Step" }, - { 5, 1, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Pentium 1 (0.8u)" }, - { 5, 2, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Pentium 1 (0.35u)" }, - { 5, 3, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Pentium OverDrive" }, - { 5, 4, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Pentium 1 (0.35u)" }, - { 5, 7, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Pentium 1 (0.35u)" }, - { 5, 8, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Pentium MMX (0.25u)" }, + /* P6 CPUs */ + { 5, 0, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium A-Step" }, + { 5, 1, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium 1 (0.8u)" }, + { 5, 2, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium 1 (0.35u)" }, + { 5, 3, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium OverDrive" }, + { 5, 4, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium 1 (0.35u)" }, + { 5, 7, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium 1 (0.35u)" }, + { 5, 8, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium MMX (0.25u)" }, - /* Pentium 2 / 3 / M / Conroe / whatsnext - all P6 based. */ - { 6, -1, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Unknown P6" }, - { 6, 0, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Pentium Pro" }, - { 6, 1, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Pentium Pro" }, - { 6, 3, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Pentium II (Klamath)" }, - { 6, 5, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Pentium II (Deschutes)" }, - { 6, 5, -1, -1, -1, 1, -1, -1, NC, MOBILE_|PENTIUM_, 0, "Mobile Pentium II (Tonga)"}, - { 6, 6, -1, -1, -1, 1, -1, -1, NC,0 , 0, "Pentium II (Dixon)" }, + /* P6 CPUs */ + { 6, 0, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium Pro" }, + { 6, 1, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium Pro" }, + { 6, 3, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium II (Klamath)" }, + { 6, 5, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium II (Deschutes)" }, + { 6, 5, -1, -1, -1, 1, -1, -1, { "Pentium(R) M", 4 }, "Mobile Pentium II (Tonga)" }, + { 6, 6, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium II (Dixon)" }, + { 6, 3, -1, -1, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "P-II Xeon (Klamath)" }, + { 6, 5, -1, -1, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "P-II Xeon (Drake)" }, + { 6, 6, -1, -1, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "P-II Xeon (Dixon)" }, + { 6, 5, -1, -1, -1, 1, -1, -1, { "Celeron(R)", 2 }, "P-II Celeron (Covington)" }, + { 6, 6, -1, -1, -1, 1, -1, -1, { "Celeron(R)", 2 }, "P-II Celeron (Mendocino)" }, + { 6, 7, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium III (Katmai)" }, + { 6, 8, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium III (Coppermine)" }, + { 6, 10, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium III (Coppermine)" }, + { 6, 11, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium III (Tualatin)" }, + { 6, 11, -1, -1, -1, 1, 512, -1, { "Pentium(R)", 2 }, "Pentium III (Tualatin)" }, + { 6, 7, -1, -1, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "P-III Xeon (Tanner)" }, + { 6, 8, -1, -1, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "P-III Xeon (Cascades)" }, + { 6, 10, -1, -1, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "P-III Xeon (Cascades)" }, + { 6, 11, -1, -1, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "P-III Xeon (Tualatin)" }, + { 6, 7, -1, -1, -1, 1, 128, -1, { "Celeron(R)", 2 }, "P-III Celeron (Katmai)" }, + { 6, 8, -1, -1, -1, 1, 128, -1, { "Celeron(R)", 2 }, "P-III Celeron (Coppermine)" }, + { 6, 10, -1, -1, -1, 1, 128, -1, { "Celeron(R)", 2 }, "P-III Celeron (Coppermine)" }, + { 6, 11, -1, -1, -1, 1, 256, -1, { "Celeron(R)", 2 }, "P-III Celeron (Tualatin)" }, - { 6, 3, -1, -1, -1, 1, -1, -1, NC, XEON_ , 0, "P-II Xeon (Klamath)" }, - { 6, 5, -1, -1, -1, 1, -1, -1, NC, XEON_ , 0, "P-II Xeon (Drake)" }, - { 6, 6, -1, -1, -1, 1, -1, -1, NC, XEON_ , 0, "P-II Xeon (Dixon)" }, + /* NetBurst CPUs */ + /* Willamette (180nm): */ + { 15, 0, -1, 15, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium 4 (Willamette)" }, + { 15, 1, -1, 15, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium 4 (Willamette)" }, + { 15, 0, -1, 15, -1, 1, -1, -1, { "Pentium(R) 4 - M", 4 }, "Mobile P-4 (Willamette)" }, + { 15, 1, -1, 15, -1, 1, -1, -1, { "Pentium(R) 4 - M", 4 }, "Mobile P-4 (Willamette)" }, + { 15, 1, -1, 15, -1, 1, -1, -1, { "Celeron(R)", 2 }, "P-4 Celeron (Willamette)" }, + { 15, 0, -1, 15, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "Xeon (Foster)" }, + { 15, 1, -1, 15, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "Xeon (Foster)" }, + /* Northwood / Mobile Pentium 4 / Banias (130nm): */ + { 15, 2, -1, 15, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium 4 (Northwood)" }, + { 15, 2, -1, 15, -1, 1, -1, -1, { "Pentium(R) 4 - M", 4 }, "Mobile P-4 (Northwood)" }, + { 15, 2, -1, 15, -1, 1, -1, -1, { "Celeron(R)", 2 }, "P-4 Celeron (Northwood)" }, + { 6, 9, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium M (Banias)" }, + { 6, 9, -1, -1, -1, 1, -1, -1, { "Pentium(R) 4 - M", 4 }, "Pentium M (Banias)" }, + { 6, 9, -1, -1, -1, 1, -1, -1, { "Celeron(R)", 2 }, "Celeron M (Banias)" }, + { 6, 9, -1, -1, -1, 1, -1, -1, { "Celeron(R) M", 4 }, "Celeron M (Banias)" }, + { 15, 2, -1, 15, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "Xeon (Prestonia)" }, + { 15, 2, -1, 15, -1, 1, -1, -1, { "Xeon(TM) MP", 4 }, "Xeon (Gallatin)" }, + /* Prescott / Dothan (90nm): */ + { 15, 3, -1, 15, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium 4 (Prescott)" }, + { 15, 4, -1, 15, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium 4 (Prescott)" }, + { 15, 3, -1, 15, -1, 1, -1, -1, { "Pentium(R) 4 - M", 4 }, "Mobile P-4 (Prescott)" }, + { 15, 4, -1, 15, -1, 1, -1, -1, { "Pentium(R) 4 - M", 4 }, "Mobile P-4 (Prescott)" }, + { 15, 3, -1, 15, -1, 1, -1, -1, { "Celeron(R)", 2 }, "P-4 Celeron D (Prescott)" }, + { 15, 4, -1, 15, -1, 1, -1, -1, { "Celeron(R)", 2 }, "P-4 Celeron D (Prescott)" }, + { 15, 4, -1, 15, -1, 1, -1, -1, { "Pentium(R) D", 4 }, "Pentium D (SmithField)" }, + { 6, 13, -1, -1, -1, 1, -1, -1, { "Pentium(R) M", 4 }, "Pentium M (Dothan)" }, + { 6, 13, -1, -1, -1, 1, -1, -1, { "Pentium(R) 4 - M", 4 }, "Pentium M (Dothan)" }, + { 6, 13, -1, -1, -1, 1, -1, -1, { "Celeron(R)", 2 }, "Celeron M (Dothan)" }, + { 6, 13, -1, -1, -1, 1, -1, -1, { "Celeron(R) M", 4 }, "Celeron M (Dothan)" }, + { 15, 3, -1, 15, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "Xeon (Nocona)" }, + { 15, 4, -1, 15, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "Xeon (Nocona)" }, + { 15, 4, 3, 15, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "Xeon (Irwindale)" }, + { 15, 4, 10, 15, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "Xeon (Irwindale)" }, + { 15, 4, 1, 15, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "Xeon (Cranford)" }, + { 15, 4, -1, 15, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "Xeon (Potomac)" }, + /* Cedar Mill / Yonah / Presler (65nm): */ + { 15, 6, -1, 15, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium 4 (Cedar Mill)" }, + { 15, 6, -1, 15, -1, 1, -1, -1, { "Pentium(R) 4 - M", 4 }, "Mobile P-4 (Cedar Mill)" }, + { 15, 6, -1, 15, -1, 1, -1, -1, { "Celeron(R)", 2 }, "P-4 Celeron D (Cedar Mill)" }, + { 6, 14, -1, -1, -1, 1, -1, -1, { "Core(TM) [UT]1###", 6 }, "Core Solo (Yonah)" }, + { 6, 14, -1, -1, -1, 2, -1, -1, { "Core(TM) Duo [UTL]2###", 6 }, "Core Duo (Yonah)" }, + { 15, 6, -1, 15, -1, 1, -1, -1, { "Pentium(R) D", 4 }, "Pentium D (Presler)" }, + { 15, 6, -1, 15, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "Xeon (Dempsey)" }, - { 6, 5, -1, -1, -1, 1, -1, -1, NC, CELERON_ , 0, "P-II Celeron (Covington)" }, - { 6, 6, -1, -1, -1, 1, -1, -1, NC, CELERON_ , 0, "P-II Celeron (Mendocino)" }, + /* Bonnell CPUs (first generation cores, 45nm): */ + { 6, 12, -1, -1, -1, -1, -1, -1, { "Atom(TM) Z5##", 6 }, "Atom (Silverthorne)" }, + { 6, 12, -1, -1, -1, -1, -1, -1, { "Atom(TM) N2##", 6 }, "Atom (Diamondville)" }, + { 6, 12, -1, -1, -1, -1, -1, -1, { "Atom(TM) [23]##", 6 }, "Atom (Diamondville)" }, + /* Bonnell CPUs (second generation cores, 45nm): */ + { 6, 12, -1, -1, -1, -1, -1, -1, { "Atom(TM) [ND][45]##", 6 }, "Atom (Pineview)" }, + { 6, 12, -1, -1, -1, -1, -1, -1, { "Atom(TM) Z6##", 6 }, "Atom (Lincroft)" }, + /* Bonnell CPUs (third generation cores, 32nm): */ + { 6, 12, -1, -1, -1, -1, -1, -1, { "Atom(TM) [ND]2###", 6 }, "Atom (Cedarview)" }, + { 6, 6, -1, -1, -1, -1, -1, -1, { "Atom(TM) [ND]2###", 6 }, "Atom (Cedarview)" }, - /* -------------------------------------------------- */ + /* Conroe CPUs (65nm): https://en.wikipedia.org/wiki/Conroe_(microprocessor) */ + { 6, 15, -1, -1, -1, 2, 2048, -1, { "Core(TM)2 Duo E6###", 8 }, "Core 2 Duo (Conroe-2M)" }, + { 6, 15, -1, -1, -1, 2, 4096, -1, { "Core(TM)2 Duo E6###", 8 }, "Core 2 Duo (Conroe)" }, + { 6, 15, -1, -1, -1, 2, 4096, -1, { "Core(TM)2 6###", 4 }, "Core 2 Duo (Conroe)" }, + { 6, 15, -1, -1, -1, 4, 4096, -1, { "Core(TM)2 Quad Q6###", 8 }, "Core 2 Quad (Kentsfield)" }, + { 6, 15, -1, -1, -1, 2, 2048, -1, { "Core(TM)2 Duo E4###", 8 }, "Core 2 Duo (Allendale)" }, + { 6, 15, -1, -1, 15, 2, 2048, -1, { "Core(TM)2 U7###", 6 }, "Core 2 Duo (Merom-2M)" }, + { 6, 15, -1, -1, 15, 2, 2048, -1, { "Core(TM)2 T[57]###", 6 }, "Core 2 Duo (Merom-2M)" }, + { 6, 15, -1, -1, 15, 2, 4096, -1, { "Core(TM)2 T7###", 6 }, "Core 2 Duo (Merom)" }, + { 6, 15, -1, -1, 15, 2, 4096, -1, { "Core(TM)2 S[LP]7###", 6 }, "Core 2 Duo (Merom)" }, + { 6, 15, -1, -1, 15, 2, 4096, -1, { "Core(TM)2 L7###", 6 }, "Core 2 Duo (Merom)" }, + { 6, 15, -1, -1, 15, 2, -1, -1, { "Pentium(R) Dual E2###", 8 }, "Pentium Dual-Core (Allendale)" }, + { 6, 15, -1, -1, 15, 2, -1, -1, { "Celeron(R) E1###", 6 }, "Celeron (Allendale)" }, + { 6, 6, -1, -1, 22, 1, -1, -1, { "Celeron(R) [24]##", 4 }, "Celeron (Conroe-L)" }, - { 6, 7, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Pentium III (Katmai)" }, - { 6, 8, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Pentium III (Coppermine)"}, - { 6, 10, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Pentium III (Coppermine)"}, - { 6, 11, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Pentium III (Tualatin)" }, - { 6, 11, -1, -1, -1, 1, 512, -1, NC, 0 , 0, "Pentium III (Tualatin)" }, - - { 6, 7, -1, -1, -1, 1, -1, -1, NC, XEON_ , 0, "P-III Xeon (Tanner)" }, - { 6, 8, -1, -1, -1, 1, -1, -1, NC, XEON_ , 0, "P-III Xeon (Cascades)" }, - { 6, 10, -1, -1, -1, 1, -1, -1, NC, XEON_ , 0, "P-III Xeon (Cascades)" }, - { 6, 11, -1, -1, -1, 1, -1, -1, NC, XEON_ , 0, "P-III Xeon (Tualatin)" }, - - { 6, 7, -1, -1, -1, 1, 128, -1, NC, CELERON_ , 0, "P-III Celeron (Katmai)" }, - { 6, 8, -1, -1, -1, 1, 128, -1, NC, CELERON_ , 0, "P-III Celeron (Coppermine)" }, - { 6, 10, -1, -1, -1, 1, 128, -1, NC, CELERON_ , 0, "P-III Celeron (Coppermine)" }, - { 6, 11, -1, -1, -1, 1, 256, -1, NC, CELERON_ , 0, "P-III Celeron (Tualatin)" }, - - /* Netburst based (Pentium 4 and later) - classic P4s */ - { 15, -1, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Unknown Pentium 4" }, - { 15, -1, -1, 15, -1, 1, -1, -1, NC, CELERON_ , 0, "Unknown P-4 Celeron" }, - { 15, -1, -1, 15, -1, 1, -1, -1, NC, XEON_ , 0, "Unknown Xeon" }, - - { 15, 0, -1, 15, -1, 1, -1, -1, NC, PENTIUM_ , 0, "Pentium 4 (Willamette)" }, - { 15, 1, -1, 15, -1, 1, -1, -1, NC, PENTIUM_ , 0, "Pentium 4 (Willamette)" }, - { 15, 2, -1, 15, -1, 1, -1, -1, NC, PENTIUM_ , 0, "Pentium 4 (Northwood)" }, - { 15, 3, -1, 15, -1, 1, -1, -1, NC, PENTIUM_ , 0, "Pentium 4 (Prescott)" }, - { 15, 4, -1, 15, -1, 1, -1, -1, NC, PENTIUM_ , 0, "Pentium 4 (Prescott)" }, - { 15, 6, -1, 15, -1, 1, -1, -1, NC, PENTIUM_ , 0, "Pentium 4 (Cedar Mill)" }, - { 15, 0, -1, 15, -1, 1, -1, -1, NC, MOBILE_|PENTIUM_, 0, "Mobile P-4 (Willamette)" }, - { 15, 1, -1, 15, -1, 1, -1, -1, NC, MOBILE_|PENTIUM_, 0, "Mobile P-4 (Willamette)" }, - { 15, 2, -1, 15, -1, 1, -1, -1, NC, MOBILE_|PENTIUM_, 0, "Mobile P-4 (Northwood)" }, - { 15, 3, -1, 15, -1, 1, -1, -1, NC, MOBILE_|PENTIUM_, 0, "Mobile P-4 (Prescott)" }, - { 15, 4, -1, 15, -1, 1, -1, -1, NC, MOBILE_|PENTIUM_, 0, "Mobile P-4 (Prescott)" }, - { 15, 6, -1, 15, -1, 1, -1, -1, NC, MOBILE_|PENTIUM_, 0, "Mobile P-4 (Cedar Mill)" }, - - /* server CPUs */ - { 15, 0, -1, 15, -1, 1, -1, -1, NC, XEON_ , 0, "Xeon (Foster)" }, - { 15, 1, -1, 15, -1, 1, -1, -1, NC, XEON_ , 0, "Xeon (Foster)" }, - { 15, 2, -1, 15, -1, 1, -1, -1, NC, XEON_ , 0, "Xeon (Prestonia)" }, - { 15, 2, -1, 15, -1, 1, -1, -1, NC, XEON_|_MP_ , 0, "Xeon (Gallatin)" }, - { 15, 3, -1, 15, -1, 1, -1, -1, NC, XEON_ , 0, "Xeon (Nocona)" }, - { 15, 4, -1, 15, -1, 1, -1, -1, NC, XEON_ , 0, "Xeon (Nocona)" }, - { 15, 4, -1, 15, -1, 1, -1, -1, IRWIN, XEON_ , 0, "Xeon (Irwindale)" }, - { 15, 4, -1, 15, -1, 1, -1, -1, NC, XEON_|_MP_ , 0, "Xeon (Cranford)" }, - { 15, 4, -1, 15, -1, 1, -1, -1, POTOMAC, XEON_ , 0, "Xeon (Potomac)" }, - { 15, 6, -1, 15, -1, 1, -1, -1, NC, XEON_ , 0, "Xeon (Dempsey)" }, - - /* Pentium Ds */ - { 15, 4, 4, 15, -1, 1, -1, -1, NC, 0 , 0, "Pentium D (SmithField)" }, - { 15, 4, -1, 15, -1, 1, -1, -1, PENTIUM_D, 0 , 0, "Pentium D (SmithField)" }, - { 15, 4, 7, 15, -1, 1, -1, -1, NC, 0 , 0, "Pentium D (SmithField)" }, - { 15, 6, -1, 15, -1, 1, -1, -1, PENTIUM_D, 0 , 0, "Pentium D (Presler)" }, - - /* Celeron and Celeron Ds */ - { 15, 1, -1, 15, -1, 1, -1, -1, NC, CELERON_ , 0, "P-4 Celeron (Willamette)" }, - { 15, 2, -1, 15, -1, 1, -1, -1, NC, CELERON_ , 0, "P-4 Celeron (Northwood)" }, - { 15, 3, -1, 15, -1, 1, -1, -1, NC, CELERON_ , 0, "P-4 Celeron D (Prescott)" }, - { 15, 4, -1, 15, -1, 1, -1, -1, NC, CELERON_ , 0, "P-4 Celeron D (Prescott)" }, - { 15, 6, -1, 15, -1, 1, -1, -1, NC, CELERON_ , 0, "P-4 Celeron D (Cedar Mill)" }, - - /* -------------------------------------------------- */ - /* Intel Core microarchitecture - P6-based */ - - { 6, 9, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Unknown Pentium M" }, - { 6, 9, -1, -1, -1, 1, -1, -1, PENTIUM_M, 0 , 0, "Unknown Pentium M" }, - { 6, 9, -1, -1, -1, 1, -1, -1, NC, PENTIUM_ , 0, "Pentium M (Banias)" }, - { 6, 9, -1, -1, -1, 1, -1, -1, PENTIUM_M, 0 , 0, "Pentium M (Banias)" }, - { 6, 9, -1, -1, -1, 1, -1, -1, NC, CELERON_ , 0, "Celeron M" }, - { 6, 13, -1, -1, -1, 1, -1, -1, NC, PENTIUM_ , 0, "Pentium M (Dothan)" }, - { 6, 13, -1, -1, -1, 1, -1, -1, PENTIUM_M, 0 , 0, "Pentium M (Dothan)" }, - { 6, 13, -1, -1, -1, 1, -1, -1, NC, CELERON_ , 0, "Celeron M" }, - - { 6, 12, -1, -1, -1, -1, -1, -1, NC, ATOM_ , 0, "Unknown Atom" }, - { 6, 12, -1, -1, -1, -1, -1, -1, DIAMONDVILLE,ATOM_, 0, "Atom (Diamondville)" }, - { 6, 12, -1, -1, -1, -1, -1, -1, SILVERTHORNE,ATOM_, 0, "Atom (Silverthorne)" }, - { 6, 12, -1, -1, -1, -1, -1, -1, CEDARVIEW, ATOM_ , 0, "Atom (Cedarview)" }, - { 6, 6, -1, -1, -1, -1, -1, -1, CEDARVIEW, ATOM_ , 0, "Atom (Cedarview)" }, - { 6, 12, -1, -1, -1, -1, -1, -1, PINEVIEW, ATOM_ , 0, "Atom (Pineview)" }, - - /* -------------------------------------------------- */ - - { 6, 14, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Unknown Yonah" }, - { 6, 14, -1, -1, -1, 1, -1, -1, CORE_SOLO, 0 , 0, "Yonah (Core Solo)" }, - { 6, 14, -1, -1, -1, 2, -1, -1, CORE_DUO, 0 , 0, "Yonah (Core Duo)" }, - { 6, 14, -1, -1, -1, 1, -1, -1, CORE_SOLO, MOBILE_, 0, "Yonah (Core Solo)" }, - { 6, 14, -1, -1, -1, 2, -1, -1, CORE_DUO , MOBILE_, 0, "Yonah (Core Duo)" }, - { 6, 14, -1, -1, -1, 1, -1, -1, CORE_SOLO, 0 , 0, "Yonah (Core Solo)" }, - - { 6, 15, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Unknown Core 2" }, - { 6, 15, -1, -1, -1, 2, 4096, -1, CORE_DUO, 0 , 0, "Conroe (Core 2 Duo)" }, - { 6, 15, -1, -1, -1, 2, 1024, -1, CORE_DUO, 0 , 0, "Conroe (Core 2 Duo) 1024K" }, - { 6, 15, -1, -1, -1, 2, 512, -1, CORE_DUO, 0 , 0, "Conroe (Core 2 Duo) 512K" }, - { 6, 15, -1, -1, -1, 4, -1, -1, QUAD_CORE, 0 , 0, "Kentsfield (Core 2 Quad)" }, - { 6, 15, -1, -1, -1, 4, 4096, -1, QUAD_CORE, 0 , 0, "Kentsfield (Core 2 Quad)" }, - { 6, 15, -1, -1, -1, 400, -1, -1, MORE_THAN_QUADCORE, 0, 0, "More than quad-core" }, - { 6, 15, -1, -1, -1, 2, 2048, -1, CORE_DUO, 0 , 0, "Allendale (Core 2 Duo)" }, - { 6, 15, -1, -1, -1, 2, -1, -1, MOBILE_CORE_DUO, 0, 0, "Merom (Core 2 Duo)" }, - { 6, 15, -1, -1, -1, 2, 2048, -1, MEROM, 0 , 0, "Merom (Core 2 Duo) 2048K" }, - { 6, 15, -1, -1, -1, 2, 4096, -1, MEROM, 0 , 0, "Merom (Core 2 Duo) 4096K" }, - - { 6, 15, -1, -1, 15, 2, -1, -1, NC, PENTIUM_ , 0, "Allendale (Pentium)" }, - { 6, 15, -1, -1, 15, 2, -1, -1, NC, CELERON_ , 0, "Allendale (Celeron)" }, - { 6, 6, -1, -1, 22, 1, -1, -1, NC, CELERON_ , 0, "Conroe-L (Celeron)" }, - - - { 6, 6, -1, -1, 22, 1, -1, -1, NC, 0 , 0, "Unknown Core ?" }, - { 6, 7, -1, -1, 23, 1, -1, -1, NC, 0 , 0, "Unknown Core ?" }, - { 6, 6, -1, -1, 22, 400, -1, -1, MORE_THAN_QUADCORE, 0, 0, "More than quad-core" }, - { 6, 7, -1, -1, 23, 400, -1, -1, MORE_THAN_QUADCORE, 0, 0, "More than quad-core" }, - - { 6, 7, -1, -1, 23, 1, -1, -1, CORE_SOLO , 0, 0, "Unknown Core 45nm" }, - { 6, 7, -1, -1, 23, 1, -1, -1, CORE_DUO , 0, 0, "Unknown Core 45nm" }, - { 6, 7, -1, -1, 23, 2, 1024, -1, WOLFDALE , 0, 0, "Celeron Wolfdale 1M" }, - { 6, 7, -1, -1, 23, 2, 2048, -1, WOLFDALE , 0, 0, "Wolfdale (Core 2 Duo) 2M" }, - { 6, 7, -1, -1, 23, 2, 3072, -1, WOLFDALE , 0, 0, "Wolfdale (Core 2 Duo) 3M" }, - { 6, 7, -1, -1, 23, 2, 6144, -1, WOLFDALE , 0, 0, "Wolfdale (Core 2 Duo) 6M" }, - { 6, 7, -1, -1, 23, 1, 1024, -1, PENRYN, CELERON_, 0, "Celeron Penryn L" }, - { 6, 7, -1, -1, 23, 1, -1, -1, MOBILE_CORE_DUO , 0, 0, "Penryn (Core 2 Duo)" }, - { 6, 7, -1, -1, 23, 2, 1024, -1, PENRYN , 0, 0, "Penryn (Core 2 Duo)" }, - { 6, 7, -1, -1, 23, 2, 3072, -1, PENRYN , 0, 0, "Penryn (Core 2 Duo) 3M" }, - { 6, 7, -1, -1, 23, 2, 6144, -1, PENRYN , 0, 0, "Penryn (Core 2 Duo) 6M" }, - { 6, 7, -1, -1, 23, 4, 2048, -1, NC , 0, 0, "Yorkfield (Core 2 Quad) 2M"}, - { 6, 7, -1, -1, 23, 4, 3072, -1, NC , 0, 0, "Yorkfield (Core 2 Quad) 3M"}, - { 6, 7, -1, -1, 23, 4, 6144, -1, NC , 0, 0, "Yorkfield (Core 2 Quad) 6M"}, + /* Penryn CPUs (45nm): https://en.wikipedia.org/wiki/Penryn_(microarchitecture)#CPU_List */ + { 6, 7, -1, -1, 23, 2, 1024, -1, { "Celeron(R) E3###", 6 }, "Celeron (Wolfdale-3M)" }, + { 6, 7, -1, -1, 23, 2, 1024, -1, { "Pentium(R) E2###", 6 }, "Celeron (Wolfdale-3M)" }, + { 6, 7, -1, -1, 23, 2, 2048, -1, { "Pentium(R) E[56]###", 6 }, "Pentium (Wolfdale-3M)" }, + { 6, 7, -1, -1, 23, 2, 3072, -1, { "Core(TM)2 Duo E7###", 8 }, "Core 2 Duo (Wolfdale-3M)" }, + { 6, 7, -1, -1, 23, 2, 6144, -1, { "Core(TM)2 Duo E8###", 8 }, "Core 2 Duo (Wolfdale)" }, + { 6, 7, -1, -1, 23, 2, 1024, -1, { "Pentium(R) Dual-Core T4###", 8 }, "Pentium Dual-Core (Penryn-L)" }, + { 6, 7, -1, -1, 23, 1, 1024, -1, { "Celeron(R) [79]##", 4 }, "Celeron (Penryn-L)" }, + { 6, 7, -1, -1, 23, 2, 3072, -1, { "Core(TM)2 Duo SU[78]###", 8 }, "Core 2 Duo (Penryn-3M)" }, + { 6, 7, -1, -1, 23, 2, 3072, -1, { "Core(TM)2 Duo P[78]###", 8 }, "Core 2 Duo (Penryn-3M)" }, + { 6, 7, -1, -1, 23, 2, 2048, -1, { "Core(TM)2 Duo T6###", 8 }, "Core 2 Duo (Penryn-3M)" }, + { 6, 7, -1, -1, 23, 2, 3072, -1, { "Core(TM)2 Duo T8###", 8 }, "Core 2 Duo (Penryn-3M)" }, + { 6, 7, -1, -1, 23, 2, 6144, -1, { "Core(TM)2 Duo S[LP]9###", 8 }, "Core 2 Duo (Penryn)" }, + { 6, 7, -1, -1, 23, 2, 6144, -1, { "Core(TM)2 Duo [PT]9###", 8 }, "Core 2 Duo (Penryn)" }, + { 6, 7, -1, -1, 23, 2, 6144, -1, { "Core(TM)2 Duo E8###", 8 }, "Core 2 Duo (Penryn)" }, + { 6, 7, -1, -1, 23, 4, 2048, -1, { "Core(TM)2 Quad Q8###", 8 }, "Core 2 Quad (Yorkfield-6M)" }, // 2×2 MB L2$ + { 6, 7, -1, -1, 23, 4, 3072, -1, { "Core(TM)2 Quad Q9#0#", 8 }, "Core 2 Quad (Yorkfield-6M)" }, // 2×3 MB L2$ + { 6, 7, -1, -1, 23, 4, 6144, -1, { "Core(TM)2 Quad Q9#5#", 8 }, "Core 2 Quad (Yorkfield)" }, // 2×6 MB L2$ /* Core microarchitecture-based Xeons: */ - { 6, 14, -1, -1, 14, 1, -1, -1, NC, XEON_ , 0, "Xeon LV" }, - { 6, 15, -1, -1, 15, 2, 4096, -1, NC, XEON_ , _5100, "Xeon (Woodcrest)" }, - { 6, 15, -1, -1, 15, 2, 2048, -1, NC, XEON_ , _3000, "Xeon (Conroe/2M)" }, - { 6, 15, -1, -1, 15, 2, 4096, -1, NC, XEON_ , _3000, "Xeon (Conroe/4M)" }, - { 6, 15, -1, -1, 15, 4, 4096, -1, NC, XEON_ , X3200, "Xeon (Kentsfield)" }, - { 6, 15, -1, -1, 15, 4, 4096, -1, NC, XEON_ , _5300, "Xeon (Clovertown)" }, - { 6, 7, -1, -1, 23, 2, 6144, -1, NC, XEON_ , _3100, "Xeon (Wolfdale)" }, - { 6, 7, -1, -1, 23, 2, 6144, -1, NC, XEON_ , _5200, "Xeon (Wolfdale DP)" }, - { 6, 7, -1, -1, 23, 4, 6144, -1, NC, XEON_ , _5400, "Xeon (Harpertown)" }, - { 6, 7, -1, -1, 23, 4, 3072, -1, NC, XEON_ , X3300, "Xeon (Yorkfield/3M)" }, - { 6, 7, -1, -1, 23, 4, 6144, -1, NC, XEON_ , X3300, "Xeon (Yorkfield/6M)" }, + { 6, 14, -1, -1, 14, 1, -1, -1, { "Xeon(R) 51##", 4 }, "Xeon LV (Woodcrest)" }, + { 6, 15, -1, -1, 15, 2, -1, -1, { "Xeon(R) 51##", 4 }, "Xeon (Woodcrest)" }, + { 6, 15, -1, -1, 15, 2, -1, -1, { "Xeon(R) 30##", 4 }, "Xeon (Conroe)" }, + { 6, 15, -1, -1, 15, 4, -1, -1, { "Xeon(R) X32##", 6 }, "Xeon (Kentsfield)" }, + { 6, 15, -1, -1, 15, 4, -1, -1, { "Xeon(R) [EXL]53##", 6 }, "Xeon (Clovertown)" }, + { 6, 7, -1, -1, 23, 2, -1, -1, { "Xeon(R) [EL]31##", 6 }, "Xeon (Wolfdale)" }, + { 6, 7, -1, -1, 23, 2, -1, -1, { "Xeon(R) [EXL]52##", 6 }, "Xeon (Wolfdale DP)" }, + { 6, 7, -1, -1, 23, 4, -1, -1, { "Xeon(R) [EXL]54##", 6 }, "Xeon (Harpertown)" }, + { 6, 7, -1, -1, 23, 4, -1, -1, { "Xeon(R) [XL]33##", 6 }, "Xeon (Yorkfield)" }, /* Nehalem CPUs (45nm): */ - { 6, 10, -1, -1, 26, 4, -1, -1, GAINESTOWN, XEON_ , 0, "Gainestown (Xeon)" }, - { 6, 10, -1, -1, 26, 4, -1, 4096, GAINESTOWN, XEON_ , 0, "Gainestown 4M (Xeon)" }, - { 6, 10, -1, -1, 26, 4, -1, 8192, GAINESTOWN, XEON_ , 0, "Gainestown 8M (Xeon)" }, - { 6, 10, -1, -1, 26, 4, -1, -1, NC, XEON_|_7 , 0, "Bloomfield (Xeon)" }, - { 6, 10, -1, -1, 26, 4, -1, -1, NC, CORE_|_I_|_7 , 0, "Bloomfield (Core i7)" }, - { 6, 10, -1, -1, 30, 4, -1, -1, NC, CORE_|_I_|_7 , 0, "Lynnfield (Core i7)" }, - { 6, 5, -1, -1, 30, 4, -1, 8192, NC, CORE_|_I_|_5 , 0, "Lynnfield (Core i5)" }, + { 6, 10, -1, -1, 26, -1, -1, -1, { "Xeon(R) [WELX]5###", 6 }, "Xeon (Gainestown)" }, + { 6, 10, -1, -1, 26, -1, -1, -1, { "Xeon(R) [WELX]3###", 6 }, "Xeon (Bloomfield)" }, + { 6, 10, -1, -1, 26, -1, -1, -1, { "Core(TM) i7 9#5", 8 }, "Core i7 Extreme (Bloomfield)" }, + { 6, 10, -1, -1, 26, -1, -1, -1, { "Core(TM) i7 9#0", 8 }, "Core i7 (Bloomfield)" }, + { 6, 10, -1, -1, 30, -1, -1, -1, { "Core(TM) i7 8##", 8 }, "Core i7 (Lynnfield)" }, + { 6, 5, -1, -1, 30, -1, -1, -1, { "Core(TM) i5 7##", 8 }, "Core i5 (Lynnfield)" }, /* Westmere CPUs (32nm): */ - { 6, 5, -1, -1, 37, 2, -1, -1, NC, 0 , 0, "Unknown Core i3/i5" }, - { 6, 12, -1, -1, 44, -1, -1, -1, WESTMERE, XEON_ , 0, "Westmere (Xeon)" }, - { 6, 12, -1, -1, 44, -1, -1, 12288, WESTMERE, XEON_ , 0, "Gulftown (Xeon)" }, - { 6, 12, -1, -1, 44, 4, -1, 12288, NC, CORE_|_I_|_7 , 0, "Gulftown (Core i7)" }, - { 6, 5, -1, -1, 37, 2, -1, 4096, NC, CORE_|_I_|_5 , 0, "Clarkdale (Core i5)" }, - { 6, 5, -1, -1, 37, 2, -1, 4096, NC, CORE_|_I_|_3 , 0, "Clarkdale (Core i3)" }, - { 6, 5, -1, -1, 37, 2, -1, 4096, NC, CORE_|_I_|_7 , 0, "Arrandale (Core i7)" }, - { 6, 5, -1, -1, 37, 2, -1, 3072, NC, CORE_|_I_|_5 , 0, "Arrandale (Core i5)" }, - { 6, 5, -1, -1, 37, 2, -1, 3072, NC, CORE_|_I_|_3 , 0, "Arrandale (Core i3)" }, - { 6, 5, -1, -1, 37, 2, -1, -1, NC, PENTIUM_ , 0, "Arrandale (Pentium)" }, - { 6, 5, -1, -1, 37, 2, -1, -1, NC, CELERON_ , 0, "Arrandale (Celeron)" }, + { 6, 12, -1, -1, 44, -1, -1, -1, { "Xeon(R) [XEL]5###", 6 }, "Xeon (Westmere-EP)" }, + { 6, 12, -1, -1, 44, -1, -1, -1, { "Xeon(R) W3###", 6 }, "Xeon (Gulftown)" }, + { 6, 12, -1, -1, 44, -1, -1, -1, { "Core(TM) i7 X 9##", 10 }, "Core i7 Extreme (Gulftown)" }, + { 6, 12, -1, -1, 44, -1, -1, -1, { "Core(TM) i7 9##", 8 }, "Core i7 (Gulftown)" }, + { 6, 5, -1, -1, 37, -1, -1, -1, { "Xeon(R) L3###", 6 }, "Xeon (Clarkdale)" }, + { 6, 5, -1, -1, 37, -1, -1, -1, { "Core(TM) i5-6##", 8 }, "Core i5 (Clarkdale)" }, + { 6, 5, -1, -1, 37, -1, -1, -1, { "Core(TM) i3-5##", 8 }, "Core i3 (Clarkdale)" }, + { 6, 5, -1, -1, 37, -1, -1, -1, { "Pentium(R) G6###", 6 }, "Pentium (Clarkdale)" }, + { 6, 5, -1, -1, 37, -1, -1, -1, { "Celeron(R) G1###", 6 }, "Celeron (Clarkdale)" }, + { 6, 5, -1, -1, 37, -1, -1, -1, { "Core(TM) i7 M 6##", 8 }, "Core i7 (Arrandale)" }, + { 6, 5, -1, -1, 37, -1, -1, -1, { "Core(TM) i5 M [45]##", 8 }, "Core i5 (Arrandale)" }, + { 6, 5, -1, -1, 37, -1, -1, -1, { "Core(TM) i3 M 3##", 8 }, "Core i3 (Arrandale)" }, + { 6, 5, -1, -1, 37, -1, -1, -1, { "Pentium(R) P6###", 6 }, "Pentium (Arrandale)" }, + { 6, 5, -1, -1, 37, -1, -1, -1, { "Pentium(R) 5U###", 6 }, "Pentium (Arrandale)" }, + { 6, 5, -1, -1, 37, -1, -1, -1, { "Celeron(R) P4###", 6 }, "Celeron (Arrandale)" }, + { 6, 5, -1, -1, 37, -1, -1, -1, { "Celeron(R) U3###", 6 }, "Celeron (Arrandale)" }, /* Sandy Bridge CPUs (2nd gen, 32nm): */ - { 6, 10, -1, -1, 42, -1, -1, -1, NC, 0 , 0, "Unknown Sandy Bridge" }, - { 6, 10, -1, -1, 42, -1, -1, -1, NC, XEON_ , 0, "Sandy Bridge (Xeon)" }, - { 6, 10, -1, -1, 42, 4, -1, -1, NC, XEON_ , 0, "Sandy Bridge (Xeon)" }, - { 6, 10, -1, -1, 42, -1, -1, -1, NC, CORE_|_I_|_7 , 0, "Sandy Bridge (Core i7)" }, - { 6, 10, -1, -1, 42, 4, -1, -1, NC, CORE_|_I_|_7 , 0, "Sandy Bridge (Core i7)" }, - { 6, 10, -1, -1, 42, 4, -1, -1, NC, CORE_|_I_|_5 , 0, "Sandy Bridge (Core i5)" }, - { 6, 10, -1, -1, 42, 2, -1, -1, NC, CORE_|_I_|_3 , 0, "Sandy Bridge (Core i3)" }, - { 6, 10, -1, -1, 42, 2, -1, -1, NC, PENTIUM_ , 0, "Sandy Bridge (Pentium)" }, - { 6, 10, -1, -1, 42, 1, -1, -1, NC, CELERON_ , 0, "Sandy Bridge (Celeron)" }, - { 6, 10, -1, -1, 42, 2, -1, -1, NC, CELERON_ , 0, "Sandy Bridge (Celeron)" }, - { 6, 13, -1, -1, 45, -1, -1, -1, NC, CORE_|_I_|_7 , 0, "Sandy Bridge-E (Core i7)" }, - { 6, 13, -1, -1, 45, -1, -1, -1, NC, XEON_ , 0, "Sandy Bridge-E (Xeon)" }, + { 6, 10, -1, -1, 42, -1, -1, -1, { "Xeon(R) E5####", 6 }, "Xeon E5 (Sandy Bridge)" }, + { 6, 10, -1, -1, 42, -1, -1, -1, { "Xeon(R) E3####", 6 }, "Xeon E3 (Sandy Bridge)" }, + { 6, 10, -1, -1, 42, -1, -1, -1, { "Core(TM) i7-2###", 8 }, "Core i7 (Sandy Bridge)" }, + { 6, 10, -1, -1, 42, -1, -1, -1, { "Core(TM) i5-2###", 8 }, "Core i5 (Sandy Bridge)" }, + { 6, 10, -1, -1, 42, -1, -1, -1, { "Core(TM) i3-2###", 8 }, "Core i3 (Sandy Bridge)" }, + { 6, 10, -1, -1, 42, -1, -1, -1, { "Pentium(R) G[68]##", 6 }, "Pentium (Sandy Bridge)" }, + { 6, 10, -1, -1, 42, -1, -1, -1, { "Celeron(R) G[45]##", 6 }, "Celeron (Sandy Bridge)" }, + { 6, 13, -1, -1, 45, -1, -1, -1, { "Core(TM) i7-3###[KX]",10 }, "Core i7 Extreme (Sandy Bridge-E)" }, + { 6, 13, -1, -1, 45, -1, -1, -1, { "Xeon(R) E5-####", 4 }, "Xeon E5 (Sandy Bridge-E)" }, + { 6, 13, -1, -1, 45, -1, -1, -1, { "Xeon(R) E3-####", 4 }, "Xeon E3 (Sandy Bridge-E)" }, /* Ivy Bridge CPUs (3rd gen, 22nm): */ - { 6, 10, -1, -1, 58, -1, -1, -1, NC, XEON_ , 0, "Ivy Bridge (Xeon)" }, - { 6, 10, -1, -1, 58, 4, -1, -1, NC, CORE_|_I_|_7 , 0, "Ivy Bridge (Core i7)" }, - { 6, 10, -1, -1, 58, 4, -1, -1, NC, CORE_|_I_|_5 , 0, "Ivy Bridge (Core i5)" }, - { 6, 10, -1, -1, 58, 2, -1, -1, NC, CORE_|_I_|_3 , 0, "Ivy Bridge (Core i3)" }, - { 6, 10, -1, -1, 58, 2, -1, -1, NC, PENTIUM_ , 0, "Ivy Bridge (Pentium)" }, - { 6, 10, -1, -1, 58, 1, -1, -1, NC, CELERON_ , 0, "Ivy Bridge (Celeron)" }, - { 6, 10, -1, -1, 58, 2, -1, -1, NC, CELERON_ , 0, "Ivy Bridge (Celeron)" }, - { 6, 14, -1, -1, 62, -1, -1, -1, NC, XEON_ , 0, "Ivy Bridge-E (Xeon)" }, - { 6, 14, -1, -1, 62, -1, -1, -1, NC, 0 , 0, "Ivy Bridge-E" }, + { 6, 10, -1, -1, 58, -1, -1, -1, { "Xeon(R) E7-#### v2", 6 }, "Xeon E7 (Ivy Bridge)" }, + { 6, 10, -1, -1, 58, -1, -1, -1, { "Xeon(R) E5-#### v2", 6 }, "Xeon E5 (Ivy Bridge)" }, + { 6, 10, -1, -1, 58, -1, -1, -1, { "Xeon(R) E3-#### v2", 6 }, "Xeon E3 (Ivy Bridge)" }, + { 6, 10, -1, -1, 58, -1, -1, -1, { "Core(TM) i7-3###", 8 }, "Core i7 (Ivy Bridge)" }, + { 6, 10, -1, -1, 58, -1, -1, -1, { "Core(TM) i5-3###", 8 }, "Core i5 (Ivy Bridge)" }, + { 6, 10, -1, -1, 58, -1, -1, -1, { "Core(TM) i3-3###", 8 }, "Core i3 (Ivy Bridge)" }, + { 6, 10, -1, -1, 58, -1, -1, -1, { "Pentium(R) G2###", 6 }, "Pentium (Ivy Bridge)" }, + { 6, 10, -1, -1, 58, -1, -1, -1, { "Celeron(R) G1###", 6 }, "Celeron (Ivy Bridge)" }, + { 6, 14, -1, -1, 62, -1, -1, -1, { "Xeon(R) E7-#### v2", 6 }, "Xeon E7 (Ivy Bridge-E)" }, + { 6, 14, -1, -1, 62, -1, -1, -1, { "Xeon(R) E5-#### v2", 6 }, "Xeon E5 (Ivy Bridge-E)" }, + { 6, 14, -1, -1, 62, -1, -1, -1, { "Xeon(R) E3-#### v2", 6 }, "Xeon E3 (Ivy Bridge-E)" }, + { 6, 14, -1, -1, 62, -1, -1, -1, { "Core(TM) i7-4###X", 10 }, "Core i7 Extreme (Ivy Bridge-E)" }, + { 6, 14, -1, -1, 62, -1, -1, -1, { "Core(TM) i7-4###K", 8 }, "Core i7 (Ivy Bridge-E)" }, /* Haswell CPUs (4th gen, 22nm): */ - { 6, 12, -1, -1, 60, -1, -1, -1, NC, XEON_ , 0, "Haswell (Xeon)" }, - { 6, 12, -1, -1, 60, 4, -1, -1, NC, CORE_|_I_|_7 , 0, "Haswell (Core i7)" }, - { 6, 5, -1, -1, 69, 4, -1, -1, NC, CORE_|_I_|_7 , 0, "Haswell (Core i7)" }, - { 6, 6, -1, -1, 70, 4, -1, -1, NC, CORE_|_I_|_7 , 0, "Haswell (Core i7)" }, - { 6, 12, -1, -1, 60, 4, -1, -1, NC, CORE_|_I_|_5 , 0, "Haswell (Core i5)" }, - { 6, 5, -1, -1, 69, 4, -1, -1, NC, CORE_|_I_|_5 , 0, "Haswell (Core i5)" }, - { 6, 12, -1, -1, 60, 2, -1, -1, NC, CORE_|_I_|_5 , 0, "Haswell (Core i5)" }, - { 6, 5, -1, -1, 69, 2, -1, -1, NC, CORE_|_I_|_5 , 0, "Haswell (Core i5)" }, - { 6, 12, -1, -1, 60, 2, -1, -1, NC, CORE_|_I_|_3 , 0, "Haswell (Core i3)" }, - { 6, 5, -1, -1, 69, 2, -1, -1, NC, CORE_|_I_|_3 , 0, "Haswell (Core i3)" }, - { 6, 12, -1, -1, 60, 2, -1, -1, NC, PENTIUM_ , 0, "Haswell (Pentium)" }, - { 6, 12, -1, -1, 60, 2, -1, -1, NC, CELERON_ , 0, "Haswell (Celeron)" }, - { 6, 12, -1, -1, 60, 1, -1, -1, NC, CELERON_ , 0, "Haswell (Celeron)" }, - { 6, 15, -1, -1, 63, -1, -1, -1, NC, 0 , 0, "Haswell-E" }, + { 6, 12, -1, -1, 60, -1, -1, -1, { "Xeon(R) E7-#### v3", 6 }, "Xeon E7 (Haswell)" }, + { 6, 12, -1, -1, 60, -1, -1, -1, { "Xeon(R) E5-#### v3", 6 }, "Xeon E5 (Haswell)" }, + { 6, 12, -1, -1, 60, -1, -1, -1, { "Xeon(R) E3-#### v3", 6 }, "Xeon E3 (Haswell)" }, + { 6, 12, -1, -1, 60, -1, -1, -1, { "Core(TM) i7-4###", 8 }, "Core i7 (Haswell)" }, + { 6, 12, -1, -1, 60, -1, -1, -1, { "Core(TM) i5-4###", 8 }, "Core i5 (Haswell)" }, + { 6, 12, -1, -1, 60, -1, -1, -1, { "Core(TM) i3-4###", 8 }, "Core i3 (Haswell)" }, + { 6, 12, -1, -1, 60, -1, -1, -1, { "Pentium(R) G3###", 6 }, "Pentium (Haswell)" }, + { 6, 12, -1, -1, 60, -1, -1, -1, { "Celeron(R) G1###", 6 }, "Celeron (Haswell)" }, + { 6, 15, -1, -1, 63, -1, -1, -1, { "Core(TM) i7-5###[KX]", 8 }, "Core i7 Extreme (Haswell)" }, + { 6, 5, -1, -1, 69, -1, -1, -1, { "Core(TM) i7-4###", 8 }, "Core i7 (Haswell)" }, + { 6, 5, -1, -1, 69, -1, -1, -1, { "Core(TM) i5-4###", 8 }, "Core i5 (Haswell)" }, + { 6, 5, -1, -1, 69, -1, -1, -1, { "Core(TM) i3-4###", 8 }, "Core i3 (Haswell)" }, + { 6, 6, -1, -1, 70, -1, -1, -1, { "Core(TM) i7-4###R", 10 }, "Core i7 (Haswell)" }, // GT3e + { 6, 6, -1, -1, 70, -1, -1, -1, { "Core(TM) i7-4###R", 10 }, "Core i5 (Haswell)" }, // GT3e /* Silvermont CPUs (2013, 22nm, low-power) */ - { 6, 7, -1, -1, 55, -1, -1, -1, NC, PENTIUM_|_J_ , 0, "Bay Trail-D (Pentium)" }, - { 6, 7, -1, -1, 55, -1, -1, -1, NC, CELERON_|_J_ , 0, "Bay Trail-D (Celeron)" }, - { 6, 7, -1, -1, 55, -1, -1, -1, NC, PENTIUM_|_N_ , 0, "Bay Trail-M (Pentium)" }, - { 6, 7, -1, -1, 55, -1, -1, -1, NC, CELERON_|_N_ , 0, "Bay Trail-M (Celeron)" }, - { 6, 7, -1, -1, 55, -1, -1, -1, NC, ATOM_ , 0, "Bay Trail-T (Atom)" }, + { 6, 7, -1, -1, 55, -1, -1, -1, { "Pentium(R) J2###", 6 }, "Pentium (Bay Trail-D)" }, + { 6, 7, -1, -1, 55, -1, -1, -1, { "Celeron(R) J1###", 6 }, "Celeron (Bay Trail-D)" }, + { 6, 7, -1, -1, 55, -1, -1, -1, { "Pentium(R) N3###", 6 }, "Pentium (Bay Trail-M)" }, + { 6, 7, -1, -1, 55, -1, -1, -1, { "Celeron(R) N2###", 6 }, "Celeron (Bay Trail-M)" }, + { 6, 7, -1, -1, 55, -1, -1, -1, { "Atom(TM) Z3###", 6 }, "Atom (Bay Trail-T)" }, + { 6, 7, -1, -1, 55, -1, -1, -1, { "Atom(TM) E3###", 6 }, "Atom (Bay Trail-I)" }, /* Broadwell CPUs (5th gen, 14nm): */ - { 6, 7, -1, -1, 71, 4, -1, -1, NC, CORE_|_I_|_7 , 0, "Broadwell (Core i7)" }, - { 6, 7, -1, -1, 71, 4, -1, -1, NC, CORE_|_I_|_5 , 0, "Broadwell (Core i5)" }, - { 6, 13, -1, -1, 61, 4, -1, -1, NC, CORE_|_I_|_7 , 0, "Broadwell-U (Core i7)" }, - { 6, 13, -1, -1, 61, 2, -1, -1, NC, CORE_|_I_|_7 , 0, "Broadwell-U (Core i7)" }, - { 6, 13, -1, -1, 61, 2, -1, -1, NC, CORE_|_I_|_5 , 0, "Broadwell-U (Core i5)" }, - { 6, 13, -1, -1, 61, 2, -1, -1, NC, CORE_|_I_|_3 , 0, "Broadwell-U (Core i3)" }, - { 6, 13, -1, -1, 61, 2, -1, -1, NC, PENTIUM_ , 0, "Broadwell-U (Pentium)" }, - { 6, 13, -1, -1, 61, 2, -1, -1, NC, CELERON_ , 0, "Broadwell-U (Celeron)" }, - { 6, 13, -1, -1, 61, 2, -1, -1, NA, 0 , 0, "Broadwell-U (Core M)" }, - { 6, 15, -1, -1, 79, -1, -1, -1, NC, XEON_ , 0, "Broadwell-E (Xeon)" }, - { 6, 15, -1, -1, 79, 2, -1, -1, NC, CORE_|_I_|_3 , 0, "Broadwell-E (Core i3)" }, - { 6, 15, -1, -1, 79, 2, -1, -1, NC, CORE_|_I_|_5 , 0, "Broadwell-E (Core i5)" }, - { 6, 15, -1, -1, 79, 4, -1, -1, NC, CORE_|_I_|_5 , 0, "Broadwell-E (Core i5)" }, - { 6, 15, -1, -1, 79, 2, -1, -1, NC, CORE_|_I_|_7 , 0, "Broadwell-E (Core i7)" }, - { 6, 15, -1, -1, 79, 4, -1, -1, NC, CORE_|_I_|_7 , 0, "Broadwell-E (Core i7)" }, + { 6, 7, -1, -1, 71, 4, -1, -1, { "Core(TM) i7-5###C", 10 }, "Core i7 (Broadwell)" }, + { 6, 7, -1, -1, 71, 4, -1, -1, { "Core(TM) i5-5###C", 10 }, "Core i5 (Broadwell)" }, + { 6, 13, -1, -1, 61, 4, -1, -1, { "Core(TM) i7-5###HQ", 12 }, "Core i7 (Broadwell-U)" }, + { 6, 13, -1, -1, 61, 2, -1, -1, { "Core(TM) i7-5###U", 10 }, "Core i7 (Broadwell-U)" }, + { 6, 13, -1, -1, 61, 2, -1, -1, { "Core(TM) i5-5###[HU]", 10 }, "Core i5 (Broadwell-U)" }, + { 6, 13, -1, -1, 61, 2, -1, -1, { "Core(TM) i3-5###U", 10 }, "Core i3 (Broadwell-U)" }, + { 6, 13, -1, -1, 61, 2, -1, -1, { "Core(TM) M-5Y##", 8 }, "Core M (Broadwell-U)" }, + { 6, 13, -1, -1, 61, 2, -1, -1, { "Pentium(R) 3###U", 6 }, "Pentium (Broadwell-U)" }, + { 6, 13, -1, -1, 61, 2, -1, -1, { "Celeron(R) 3###U", 6 }, "Celeron (Broadwell-U)" }, + { 6, 15, -1, -1, 79, 4, -1, -1, { "Core(TM) i7-6###[KX]", 10 }, "Core i7 (Broadwell-E)" }, /* Skylake (client) CPUs (2015, 6th Core i gen, 14nm) => https://en.wikichip.org/wiki/intel/microarchitectures/skylake_(client) */ - { 6, 14, -1, -1, 94, -1, -1, -1, NC, XEON_ , 0, "Skylake (Xeon)" }, - { 6, 14, -1, -1, 94, 4, -1, -1, NC, CORE_|_I_|_7 , _6xxx, "Skylake (Core i7)" }, - { 6, 14, -1, -1, 94, 4, -1, -1, NC, CORE_|_I_|_5 , _6xxx, "Skylake (Core i5)" }, - { 6, 14, -1, -1, 94, 2, -1, -1, NC, CORE_|_I_|_3 , _6xxx, "Skylake (Core i3)" }, - { 6, 14, -1, -1, 94, 2, -1, -1, NC, PENTIUM_ , 0, "Skylake (Pentium)" }, - { 6, 14, -1, -1, 78, 2, -1, -1, NC, PENTIUM_ , 0, "Skylake (Pentium)" }, - { 6, 14, -1, -1, 94, 2, -1, -1, NC, CELERON_ , 0, "Skylake (Celeron)" }, - { 6, 14, -1, -1, 78, 2, -1, -1, NC, CELERON_ , 0, "Skylake (Celeron)" }, - { 6, 14, -1, -1, 78, 2, -1, -1, NC, CORE_|_M_|_7 , _6xxx, "Skylake (Core m7)" }, - { 6, 14, -1, -1, 78, 2, -1, -1, NC, CORE_|_M_|_5 , _6xxx, "Skylake (Core m5)" }, - { 6, 14, -1, -1, 78, 2, -1, -1, NC, CORE_|_M_|_3 , _6xxx, "Skylake (Core m3)" }, + { 6, 14, -1, -1, 94, 4, -1, -1, { "Core(TM) i7-6###", 8 }, "Core i7 (Skylake)" }, + { 6, 14, -1, -1, 94, 4, -1, -1, { "Core(TM) i5-6###", 8 }, "Core i5 (Skylake)" }, + { 6, 14, -1, -1, 94, 2, -1, -1, { "Core(TM) i3-6###", 8 }, "Core i3 (Skylake)" }, + { 6, 14, -1, -1, 94, 2, -1, -1, { "Pentium(R) G4###", 4 }, "Pentium (Skylake)" }, + { 6, 14, -1, -1, 94, 2, -1, -1, { "Celeron(R) G3###", 4 }, "Celeron (Skylake)" }, + { 6, 14, -1, -1, 78, 2, -1, -1, { "Core(TM) m7-6Y##", 8 }, "Core m7 (Skylake)" }, + { 6, 14, -1, -1, 78, 2, -1, -1, { "Core(TM) m5-6Y##", 8 }, "Core m5 (Skylake)" }, + { 6, 14, -1, -1, 78, 2, -1, -1, { "Core(TM) m3-6Y##", 8 }, "Core m3 (Skylake)" }, + { 6, 14, -1, -1, 78, 2, -1, -1, { "Pentium(R) 4###[UY]", 4 }, "Pentium (Skylake)" }, + { 6, 14, -1, -1, 78, 2, -1, -1, { "Celeron(R) 3###U", 4 }, "Celeron (Skylake)" }, + { 6, 14, -1, -1, 78, 2, -1, -1, { "Celeron(R) G3###E", 6 }, "Celeron (Skylake)" }, + { 6, 5, -1, -1, 85, -1, -1, -1, { "Core(TM) i9-7###X", 10 }, "Core i9 (Skylake-X)" }, /* 10 to 18 cores */ + { 6, 5, -1, -1, 85, -1, -1, -1, { "Core(TM) i7-7###X", 10 }, "Core i7 (Skylake-X)" }, /* 6 to 8 cores */ + { 6, 14, -1, -1, 94, -1, -1, -1, { "Xeon(R) W-#1##X", 8 }, "Xeon (Skylake-X)" }, /* Skylake (server) CPUs (2017, 1st Xeon Scalable gen, 14nm) => https://en.wikichip.org/wiki/intel/microarchitectures/skylake_(server) */ - { 6, 5, -1, -1, 85, -1, -1, -1, NC, CORE_|_I_|_9 , _6xxx, "Skylake-X (Core i9)" }, /* 10 to 18 cores */ - { 6, 5, -1, -1, 85, -1, -1, -1, NC, CORE_|_I_|_7 , _6xxx, "Skylake-X (Core i7)" }, /* 6 to 8 cores */ - { 6, 5, -1, -1, 85, -1, -1, -1, NC, XEON_|_W_ , _x1xx, "Skylake-W (Xeon W)" }, - { 6, 5, -1, -1, 85, -1, -1, -1, NC, XEON_|_D_ , _x1xx, "Skylake-DE (Xeon D)" }, - { 6, 5, -1, -1, 85, -1, -1, -1, NC, XEON_|_PLATINIUM_, _x1xx, "Skylake-SP (Xeon Platinum)" }, - { 6, 5, -1, -1, 85, -1, -1, -1, NC, XEON_|_GOLD_ , _x1xx, "Skylake-SP (Xeon Gold)" }, - { 6, 5, -1, -1, 85, -1, -1, -1, NC, XEON_|_SILVER_ , _x1xx, "Skylake-SP (Xeon Silver)" }, - { 6, 5, -1, -1, 85, -1, -1, -1, NC, XEON_|_BRONZE_ , _x1xx, "Skylake-SP (Xeon Bronze)" }, + { 6, 5, -1, -1, 85, -1, -1, -1, { "Xeon(R) W-#1##", 6 }, "Xeon W (Skylake-W)" }, + { 6, 5, -1, -1, 85, -1, -1, -1, { "Xeon(R) D-#1##", 6 }, "Xeon D (Skylake-DE)" }, + { 6, 5, -1, -1, 85, -1, -1, -1, { "Xeon(R) Platinum #1##", 6 }, "Xeon Platinum (Skylake-SP)" }, + { 6, 5, -1, -1, 85, -1, -1, -1, { "Xeon(R) Gold #1##", 6 }, "Xeon Gold (Skylake-SP)" }, + { 6, 5, -1, -1, 85, -1, -1, -1, { "Xeon(R) Silver #1##", 6 }, "Xeon Silver (Skylake-SP)" }, + { 6, 5, -1, -1, 85, -1, -1, -1, { "Xeon(R) Bronze #1##", 6 }, "Xeon Bronze (Skylake-SP)" }, /* Kaby Lake CPUs (7th gen, 14nm): */ - { 6, 14, -1, -1, 158, 4, -1, -1, NC, CORE_|_I_|_7 , _7xxx, "Kaby Lake (Core i7)" }, - { 6, 14, -1, -1, 158, 4, -1, -1, NC, CORE_|_I_|_5 , _7xxx, "Kaby Lake (Core i5)" }, - { 6, 14, -1, -1, 158, 2, -1, -1, NC, CORE_|_I_|_3 , _7xxx, "Kaby Lake (Core i3)" }, - { 6, 14, -1, -1, 158, 2, -1, -1, NC, PENTIUM_ , 0, "Kaby Lake (Pentium)" }, - { 6, 14, -1, -1, 158, 2, -1, -1, NC, CELERON_ , 0, "Kaby Lake (Celeron)" }, - { 6, 14, 9, -1, 142, 2, -1, -1, NC, CORE_|_I_|_7 , _7xxx, "Kaby Lake-U (Core i7)" }, - { 6, 14, 9, -1, 142, 2, -1, -1, NC, CORE_|_I_|_5 , _7xxx, "Kaby Lake-U (Core i5)" }, - { 6, 14, 9, -1, 142, 2, -1, -1, NC, CORE_|_I_|_3 , _7xxx, "Kaby Lake-U (Core i3)" }, - { 6, 14, 9, -1, 142, 2, -1, -1, NC, PENTIUM_ , 0, "Kaby Lake-U (Pentium)" }, - { 6, 14, 9, -1, 142, 2, -1, -1, NC, CELERON_ , 0, "Kaby Lake-U (Celeron)" }, - { 6, 14, 9, -1, 142, 2, -1, -1, NC, CORE_|_M_|_3 , _7xxx, "Kaby Lake-U (Core m3)" }, - { 6, 14, 9, -1, 158, 4, -1, -1, NC, CORE_|_I_|_7 , _8xxx, "Kaby Lake-G (Core i7)" }, - { 6, 14, 9, -1, 158, 4, -1, -1, NC, CORE_|_I_|_5 , _8xxx, "Kaby Lake-G (Core i5)" }, - { 6, 14, 10, -1, 142, 4, -1, -1, NC, CORE_|_I_|_7 , _8xxx, "Kaby Lake-R (Core i7)" }, /* i7-8550U + i7-8650U */ - { 6, 14, 10, -1, 142, 4, -1, -1, NC, CORE_|_I_|_5 , _8xxx, "Kaby Lake-R (Core i5)" }, /* i5-8250U + i5-8350U */ + { 6, 14, -1, -1, 158, 4, -1, -1, { "Core(TM) i7-7###", 8 }, "Core i7 (Kaby Lake)" }, + { 6, 14, -1, -1, 158, 4, -1, -1, { "Core(TM) i5-7###", 8 }, "Core i5 (Kaby Lake)" }, + { 6, 14, -1, -1, 158, 2, -1, -1, { "Core(TM) i3-7###", 8 }, "Core i3 (Kaby Lake)" }, + { 6, 14, -1, -1, 158, 2, -1, -1, { "Pentium(R) G4###", 4 }, "Pentium (Kaby Lake)" }, + { 6, 14, -1, -1, 158, 2, -1, -1, { "Celeron(R) G3###", 4 }, "Celeron (Kaby Lake)" }, + { 6, 14, 9, -1, 142, 2, -1, -1, { "Core(TM) i7-7.##", 8 }, "Core i7 (Kaby Lake-U)" }, + { 6, 14, 9, -1, 142, 2, -1, -1, { "Core(TM) i5-7.##", 8 }, "Core i5 (Kaby Lake-U)" }, + { 6, 14, 9, -1, 142, 2, -1, -1, { "Core(TM) i3-7.##", 8 }, "Core i3 (Kaby Lake-U)" }, + { 6, 14, 9, -1, 142, 2, -1, -1, { "Core(TM) m3-7.##", 8 }, "Core m3 (Kaby Lake-U)" }, + { 6, 14, 9, -1, 142, 2, -1, -1, { "Pentium(R) Gold 4###[UY]", 8 }, "Pentium Gold (Kaby Lake-U)" }, + { 6, 14, 9, -1, 142, 2, -1, -1, { "Celeron(R) 3###[UY]", 6 }, "Celeron (Kaby Lake-U)" }, + { 6, 14, 9, -1, 158, 4, -1, -1, { "Core(TM) i7-8###G", 10 }, "Core i7 (Kaby Lake-G)" }, + { 6, 14, 9, -1, 158, 4, -1, -1, { "Core(TM) i5-8###G", 10 }, "Core i5 (Kaby Lake-G)" }, + { 6, 14, 10, -1, 142, 4, -1, -1, { "Core(TM) i7-8###U", 10 }, "Core i7 (Kaby Lake-R)" }, /* i7-8550U + i7-8650U */ + { 6, 14, 10, -1, 142, 4, -1, -1, { "Core(TM) i5-8###U", 10 }, "Core i5 (Kaby Lake-R)" }, /* i5-8250U + i5-8350U */ + { 6, 14, 10, -1, 142, 2, -1, -1, { "Pentium(R) Gold 4###U", 8 }, "Pentium Gold (Kaby Lake-U)" }, + { 6, 14, 10, -1, 142, 2, -1, -1, { "Celeron(R) 3###U", 6 }, "Celeron (Kaby Lake-U)" }, /* Coffee Lake CPUs (8th gen, 14nm): */ - { 6, 14, 10, -1, 158, 8, -1, -1, NC, CORE_|_I_|_9 , _8xxx, "Coffee Lake (Core i9)" }, - { 6, 14, 10, -1, 158, 8, -1, -1, NC, CORE_|_I_|_7 , _8xxx, "Coffee Lake (Core i7)" }, - { 6, 14, 10, -1, 158, 6, -1, -1, NC, CORE_|_I_|_7 , _8xxx, "Coffee Lake (Core i7)" }, - { 6, 14, 10, -1, 158, 6, -1, -1, NC, CORE_|_I_|_5 , _8xxx, "Coffee Lake (Core i5)" }, - { 6, 14, 10, -1, 158, 4, -1, -1, NC, CORE_|_I_|_3 , _8xxx, "Coffee Lake (Core i3)" }, - { 6, 14, 10, -1, 158, 2, -1, -1, NC, PENTIUM_ , 0, "Coffee Lake (Pentium)" }, - { 6, 14, 10, -1, 158, 2, -1, -1, NC, CELERON_ , 0, "Coffee Lake (Celeron)" }, - { 6, 14, 10, -1, 142, 4, -1, -1, NC, CORE_|_I_|_7 , _8xxx, "Coffee Lake-U (Core i7)" }, - { 6, 14, 10, -1, 142, 4, -1, -1, NC, CORE_|_I_|_5 , _8xxx, "Coffee Lake-U (Core i5)" }, - { 6, 14, 10, -1, 142, 2, -1, -1, NC, CORE_|_I_|_3 , _8xxx, "Coffee Lake-U (Core i3)" }, - { 6, 6, -1, -1, 102, 2, -1, -1, NC, CORE_|_I_|_3 , _8xxx, "Cannon Lake (Core i3)" }, /* Core i3 8121U */ - { 6, 6, -1, -1, 102, 2, -1, -1, NC, CORE_|_M_|_3 , _8xxx, "Cannon Lake (Core m3)" }, /* Core m3 8114Y */ - { 6, 14, 12, -1, 142, 4, -1, -1, NC, CORE_|_I_|_7 , _8xxx, "Whiskey Lake-U (Core i7)" }, - { 6, 14, 12, -1, 142, 4, -1, -1, NC, CORE_|_I_|_5 , _8xxx, "Whiskey Lake-U (Core i5)" }, - { 6, 14, 12, -1, 142, 2, -1, -1, NC, CORE_|_I_|_3 , _8xxx, "Whiskey Lake-U (Core i3)" }, - { 6, 14, 12, -1, 142, 2, -1, -1, NC, PENTIUM_ , _8xxx, "Whiskey Lake-U (Pentium)" }, - { 6, 14, 12, -1, 142, 2, -1, -1, NC, CELERON_ , _8xxx, "Whiskey Lake-U (Celeron)" }, + { 6, 14, -1, -1, 158, 6, -1, -1, { "Core(TM) i7-8###", 8 }, "Core i7 (Coffee Lake-S)" }, + { 6, 14, -1, -1, 158, 6, -1, -1, { "Core(TM) i5-8###", 8 }, "Core i5 (Coffee Lake-S)" }, + { 6, 14, -1, -1, 158, 4, -1, -1, { "Core(TM) i3-8###", 8 }, "Core i3 (Coffee Lake-S)" }, + { 6, 14, -1, -1, 158, 2, -1, -1, { "Pentium(R) Gold G5###", 6 }, "Pentium Gold (Coffee Lake-S)" }, + { 6, 14, -1, -1, 158, 2, -1, -1, { "Celeron(R) G4###", 4 }, "Celeron (Coffee Lake-S)" }, + { 6, 14, -1, -1, 142, 4, -1, -1, { "Core(TM) i9-8###[HB]", 10 }, "Core i9 (Coffee Lake-H)" }, + { 6, 14, -1, -1, 142, 4, -1, -1, { "Core(TM) i7-8###[HB]", 10 }, "Core i7 (Coffee Lake-H)" }, + { 6, 14, -1, -1, 142, 4, -1, -1, { "Core(TM) i5-8###[HB]", 10 }, "Core i5 (Coffee Lake-H)" }, + { 6, 14, -1, -1, 142, 2, -1, -1, { "Core(TM) i3-8###[HB]", 10 }, "Core i3 (Coffee Lake-H)" }, + { 6, 14, -1, -1, 142, 4, -1, -1, { "Core(TM) i7-8###U", 10 }, "Core i7 (Coffee Lake-U)" }, + { 6, 14, -1, -1, 142, 4, -1, -1, { "Core(TM) i5-8###U", 10 }, "Core i5 (Coffee Lake-U)" }, + { 6, 14, -1, -1, 142, 2, -1, -1, { "Core(TM) i3-8###U", 10 }, "Core i3 (Coffee Lake-U)" }, + { 6, 6, -1, -1, 102, 2, -1, -1, { "Core(TM) i3-8###U", 10 }, "Core i3 (Cannon Lake-U)" }, /* Core i3 8121U */ + { 6, 6, -1, -1, 102, 2, -1, -1, { "Core(TM) m3-8###Y", 10 }, "Core m3 (Cannon Lake-Y)" }, /* Core m3 8114Y */ + { 6, 14, -1, -1, 142, 4, -1, -1, { "Core(TM) i7-8###U", 12 }, "Core i7 (Whiskey Lake-U)" }, + { 6, 14, -1, -1, 142, 4, -1, -1, { "Core(TM) i5-8###U", 12 }, "Core i5 (Whiskey Lake-U)" }, + { 6, 14, -1, -1, 142, 2, -1, -1, { "Core(TM) i3-8###U", 12 }, "Core i3 (Whiskey Lake-U)" }, + { 6, 14, -1, -1, 142, 2, -1, -1, { "Pentium(R) Gold 5###U", 8 }, "Pentium Gold (Whiskey Lake-U)" }, + { 6, 14, -1, -1, 142, 2, -1, -1, { "Celeron(R) 4###U", 6 }, "Celeron (Whiskey Lake-U)" }, /* Coffee Lake Refresh CPUs (9th gen, 14nm): */ - { 6, 14, 13, -1, 158, 8, -1, -1, NC, CORE_|_I_|_9 , _9xxx, "Coffee Lake-R (Core i9)" }, - { 6, 14, 12, -1, 158, 8, -1, -1, NC, CORE_|_I_|_9 , _9xxx, "Coffee Lake-R (Core i9)" }, - { 6, 14, 13, -1, 158, 8, -1, -1, NC, CORE_|_I_|_7 , _9xxx, "Coffee Lake-R (Core i7)" }, - { 6, 14, 12, -1, 158, 8, -1, -1, NC, CORE_|_I_|_7 , _9xxx, "Coffee Lake-R (Core i7)" }, - { 6, 14, 13, -1, 158, 6, -1, -1, NC, CORE_|_I_|_5 , _9xxx, "Coffee Lake-R (Core i5)" }, - { 6, 14, 11, -1, 158, 4, -1, -1, NC, CORE_|_I_|_3 , _9xxx, "Coffee Lake-R (Core i3)" }, + { 6, 14, -1, -1, 158, 8, -1, -1, { "Core(TM) i9-9###", 8 }, "Core i9 (Coffee Lake-S)" }, + { 6, 14, -1, -1, 158, 8, -1, -1, { "Core(TM) i7-9###", 8 }, "Core i7 (Coffee Lake-S)" }, + { 6, 14, -1, -1, 158, 6, -1, -1, { "Core(TM) i5-9###", 8 }, "Core i5 (Coffee Lake-S)" }, + { 6, 14, -1, -1, 158, 4, -1, -1, { "Core(TM) i3-9###", 8 }, "Core i3 (Coffee Lake-S)" }, + { 6, 14, -1, -1, 158, 2, -1, -1, { "Pentium(R) Gold G5###", 6 }, "Pentium Gold (Coffee Lake-S)" }, + { 6, 14, -1, -1, 158, 2, -1, -1, { "Celeron(R) G4###", 4 }, "Celeron (Coffee Lake-S)" }, /* Cascade Lake CPUs (2019, 2nd Xeon Scalable gen, 14nm) => https://en.wikichip.org/wiki/intel/microarchitectures/cascade_lake */ - { 6, 5, 7, -1, 85, -1, -1, -1, NC, CORE_|_I_|_9 , _10xxx, "Cascade Lake-X (Core i9)" }, - { 6, 5, -1, -1, 85, -1, -1, -1, NC, XEON_|_W_ , _x2xx, "Cascade Lake-W (Xeon W)" }, - { 6, 5, -1, -1, 85, -1, -1, -1, NC, XEON_|_PLATINIUM_, _x2xx, "Cascade Lake-SP (Xeon Platinum)" }, - { 6, 5, -1, -1, 85, -1, -1, -1, NC, XEON_|_GOLD_ , _x2xx, "Cascade Lake-SP (Xeon Gold)" }, - { 6, 5, -1, -1, 85, -1, -1, -1, NC, XEON_|_SILVER_ , _x2xx, "Cascade Lake-SP (Xeon Silver)" }, - { 6, 5, -1, -1, 85, -1, -1, -1, NC, XEON_|_BRONZE_ , _x2xx, "Cascade Lake-SP (Xeon Bronze)" }, + { 6, 5, 7, -1, 85, -1, -1, -1, { "Core(TM) i9-10###X", 10 }, "Core i9 (Cascade Lake-X)" }, + { 6, 5, -1, -1, 85, -1, -1, -1, { "Xeon(R) W-#[23]##", 6 }, "Xeon W (Cascade Lake-W)" }, + { 6, 5, -1, -1, 85, -1, -1, -1, { "Xeon(R) Platinum #2##", 6 }, "Xeon Platinum (Cascade Lake-SP)" }, + { 6, 5, -1, -1, 85, -1, -1, -1, { "Xeon(R) Gold #2##", 6 }, "Xeon Gold (Cascade Lake-SP)" }, + { 6, 5, -1, -1, 85, -1, -1, -1, { "Xeon(R) Silver #2##", 6 }, "Xeon Silver (Cascade Lake-SP)" }, + { 6, 5, -1, -1, 85, -1, -1, -1, { "Xeon(R) Bronze #2##", 6 }, "Xeon Bronze (Cascade Lake-SP)" }, /* Comet Lake CPUs (10th gen, 14nm): */ - { 6, 5, -1, -1, 165, 10, -1, -1, NC, CORE_|_I_|_9, _10xxx, "Comet Lake (Core i9)" }, - { 6, 5, -1, -1, 165, 8, -1, -1, NC, CORE_|_I_|_7, _10xxx, "Comet Lake (Core i7)" }, - { 6, 5, -1, -1, 165, 6, -1, -1, NC, CORE_|_I_|_5, _10xxx, "Comet Lake (Core i5)" }, - { 6, 5, -1, -1, 165, 4, -1, -1, NC, CORE_|_I_|_3, _10xxx, "Comet Lake (Core i3)" }, - { 6, 5, -1, -1, 165, 2, -1, -1, NC, PENTIUM_ , 0, "Comet Lake (Pentium)" }, - { 6, 5, -1, -1, 165, 2, -1, -1, NC, CELERON_ , 0, "Comet Lake (Celeron)" }, - { 6, 14, 12, -1, 142, 6, -1, -1, NC, CORE_|_I_|_7, _10xxx, "Comet Lake-U (Core i7)" }, - { 6, 14, 12, -1, 142, 4, -1, -1, NC, CORE_|_I_|_7, _10xxx, "Comet Lake-U (Core i7)" }, - { 6, 14, 12, -1, 142, 4, -1, -1, NC, CORE_|_I_|_5, _10xxx, "Comet Lake-U (Core i5)" }, - { 6, 14, 12, -1, 142, 2, -1, -1, NC, PENTIUM_ , 0, "Comet Lake-U (Pentium)" }, - { 6, 14, 12, -1, 142, 2, -1, -1, NC, CELERON_ , 0, "Comet Lake-U (Celeron)" }, + { 6, 5, -1, -1, 165, 10, -1, -1, { "Core(TM) i9-10###", 8 }, "Core i9 (Comet Lake-S)" }, + { 6, 5, -1, -1, 165, 8, -1, -1, { "Core(TM) i7-10###", 8 }, "Core i7 (Comet Lake-S)" }, + { 6, 5, -1, -1, 165, 6, -1, -1, { "Core(TM) i5-10###", 8 }, "Core i5 (Comet Lake-S)" }, + { 6, 5, -1, -1, 165, 4, -1, -1, { "Core(TM) i3-10###", 8 }, "Core i3 (Comet Lake-S)" }, + { 6, 5, -1, -1, 165, 2, -1, -1, { "Pentium(R) Gold G6###", 6 }, "Pentium Gold (Comet Lake-S)" }, + { 6, 5, -1, -1, 165, 2, -1, -1, { "Celeron(R) G5###", 4 }, "Celeron (Comet Lake-S)" }, + { 6, 14, 12, -1, 142, 6, -1, -1, { "Core(TM) i7-10###U", 10 }, "Core i7 (Comet Lake-U)" }, + { 6, 14, 12, -1, 142, 4, -1, -1, { "Core(TM) i7-10###U", 10 }, "Core i7 (Comet Lake-U)" }, + { 6, 14, 12, -1, 142, 4, -1, -1, { "Core(TM) i5-10###U", 10 }, "Core i5 (Comet Lake-U)" }, + { 6, 14, 12, -1, 142, 2, -1, -1, { "Pentium(R) Gold 6###U", 6 }, "Pentium Gold (Comet Lake-U)" }, + { 6, 14, 12, -1, 142, 2, -1, -1, { "Celeron(R) 5###U", 4 }, "Celeron (Comet Lake-U)" }, /* Ice Lake (client) CPUs (2019, 10th Core i gen, 10nm) => https://en.wikichip.org/wiki/intel/microarchitectures/ice_lake_(client) */ - { 6, 14, -1, -1, 126, 4, -1, -1, NC, CORE_|_I_|_7 ,_10xxx, "Ice Lake (Core i7)" }, - { 6, 14, -1, -1, 126, 4, -1, -1, NC, CORE_|_I_|_5 ,_10xxx, "Ice Lake (Core i5)" }, - { 6, 14, -1, -1, 126, 2, -1, -1, NC, CORE_|_I_|_3 ,_10xxx, "Ice Lake (Core i3)" }, + { 6, 14, -1, -1, 126, 4, -1, -1, { "Core(TM) i7-10##", 8 }, "Core i7 (Ice Lake)" }, + { 6, 14, -1, -1, 126, 4, -1, -1, { "Core(TM) i5-10##", 8 }, "Core i5 (Ice Lake)" }, + { 6, 14, -1, -1, 126, 2, -1, -1, { "Core(TM) i3-10##", 8 }, "Core i3 (Ice Lake)" }, + { 6, 14, -1, -1, 126, 2, -1, -1, { "Pentium(R) 68##", 4 }, "Pentium (Ice Lake)" }, /* Ice Lake (server) CPUs (2021, 3rd Xeon Scalable gen, 10nm) => https://en.wikichip.org/wiki/intel/microarchitectures/ice_lake_(server) */ - { 6, 12, -1, -1, 108, 4, -1, -1, NC, XEON_ , 0, "Ice Lake-D (Xeon-D)" }, - { 6, 10, -1, -1, 106, -1, -1, -1, NC, XEON_|_W_ , _x3xx, "Ice Lake-W (Xeon W)" }, - { 6, 10, -1, -1, 106, -1, -1, -1, NC, XEON_|_PLATINIUM_, _x3xx, "Ice Lake-SP (Xeon Platinum)" }, - { 6, 10, -1, -1, 106, -1, -1, -1, NC, XEON_|_GOLD_, _x3xx, "Ice Lake-SP (Xeon Gold)" }, - { 6, 10, -1, -1, 106, -1, -1, -1, NC, XEON_|_SILVER_, _x3xx, "Ice Lake-SP (Xeon Silver)" }, - { 6, 10, -1, -1, 106, -1, -1, -1, NC, XEON_|_BRONZE_, _x3xx, "Ice Lake-SP (Xeon Bronze)" }, + { 6, 12, -1, -1, 108, 4, -1, -1, { "Xeon(R) D-[12]7##", 6 }, "Xeon D (Ice Lake-D)" }, + { 6, 10, -1, -1, 106, -1, -1, -1, { "Xeon(R) W-#3##", 6 }, "Xeon W (Ice Lake-W)" }, + { 6, 10, -1, -1, 106, -1, -1, -1, { "Xeon(R) Platinum #3##", 6 }, "Xeon Platinum (Ice Lake-SP)" }, + { 6, 10, -1, -1, 106, -1, -1, -1, { "Xeon(R) Gold #3##", 6 }, "Xeon Gold (Ice Lake-SP)" }, + { 6, 10, -1, -1, 106, -1, -1, -1, { "Xeon(R) Silver #3##", 6 }, "Xeon Silver (Ice Lake-SP)" }, + { 6, 10, -1, -1, 106, -1, -1, -1, { "Xeon(R) Bronze #3##", 6 }, "Xeon Bronze (Ice Lake-SP)" }, /* Rocket Lake CPUs (11th gen, 14nm): */ - { 6, 7, -1, -1, 167, -1, -1, -1, NC, CORE_|_I_|_9 ,_11xxx, "Rocket Lake (Core i9)" }, - { 6, 7, -1, -1, 167, -1, -1, -1, NC, CORE_|_I_|_7 ,_11xxx, "Rocket Lake (Core i7)" }, - { 6, 7, -1, -1, 167, -1, -1, -1, NC, CORE_|_I_|_5 ,_11xxx, "Rocket Lake (Core i5)" }, - { 6, 7, -1, -1, 167, -1, -1, -1, NC, CORE_|_I_|_3 ,_11xxx, "Rocket Lake (Core i3)" }, - { 6, 7, -1, -1, 167, -1, -1, -1, NC, XEON_ , 0, "Rocket Lake (Xeon-E)" }, + { 6, 7, -1, -1, 167, -1, -1, -1, { "Core(TM) i9-11###", 8 }, "Core i9 (Rocket Lake-S)" }, + { 6, 7, -1, -1, 167, -1, -1, -1, { "Core(TM) i7-11###", 8 }, "Core i7 (Rocket Lake-S)" }, + { 6, 7, -1, -1, 167, -1, -1, -1, { "Core(TM) i5-11###", 8 }, "Core i5 (Rocket Lake-S)" }, + { 6, 7, -1, -1, 167, -1, -1, -1, { "Xeon(R) E-23##", 6 }, "Xeon E (Rocket Lake)" }, /* Goldmont Plus CPUs (2017, 14nm, low-power) */ - { 6, 10, -1, -1, 122, 4, -1, -1, NC, PENTIUM_ , 0, "Gemini Lake (Pentium)" }, - { 6, 10, -1, -1, 122, 4, -1, -1, NC, CELERON_ , 0, "Gemini Lake (Celeron)" }, - { 6, 10, -1, -1, 122, 2, -1, -1, NC, CELERON_ , 0, "Gemini Lake (Celeron)" }, - { 6, 12, -1, -1, 92, -1, -1, -1, NC, ATOM_ , 0, "Apollo Lake (Atom)" }, + { 6, 10, -1, -1, 122, -1, -1, -1, { "Pentium(R) Silver [JN]5###", 8 }, "Pentium (Gemini Lake)" }, + { 6, 10, -1, -1, 122, -1, -1, -1, { "Celeron(R) [JN]4###", 6 }, "Celeron (Gemini Lake)" }, + { 6, 12, -1, -1, 92, -1, -1, -1, { "Atom(TM)", 2 }, "Atom (Apollo Lake)" }, /* Tremont CPUs (2020, 10nm, low-power) */ - { 6, 6, -1, -1, 150, -1, -1, -1, NC, PENTIUM_ , 0, "Elkhart Lake (Pentium)" }, - { 6, 6, -1, -1, 150, -1, -1, -1, NC, CELERON_ , 0, "Elkhart Lake (Celeron)" }, - { 6, 6, -1, -1, 150, -1, -1, -1, NC, ATOM_ , 0, "Elkhart Lake (Atom)" }, - { 6, 10, -1, -1, 138, -1, -1, -1, NC, CORE_|_I_|_5 , 0, "Lakefield (Core i5)" }, - { 6, 10, -1, -1, 138, -1, -1, -1, NC, CORE_|_I_|_3 , 0, "Lakefield (Core i3)" }, - { 6, 12, -1, -1, 156, -1, -1, -1, NC, PENTIUM_ , 0, "Jasper Lake (Pentium)" }, - { 6, 12, -1, -1, 156, -1, -1, -1, NC, CELERON_ , 0, "Jasper Lake (Celeron)" }, + { 6, 6, -1, -1, 150, -1, -1, -1, { "Pentium(R) [JN]6###", 6 }, "Pentium (Elkhart Lake)" }, + { 6, 6, -1, -1, 150, -1, -1, -1, { "Celeron(R) [JN]6###", 6 }, "Celeron (Elkhart Lake)" }, + { 6, 6, -1, -1, 150, -1, -1, -1, { "Atom(TM) x6###", 6 }, "Atom (Elkhart Lake)" }, + { 6, 10, -1, -1, 138, -1, -1, -1, { "Core(TM) i5-L##G7", 12 }, "Core i5 (Lakefield)" }, + { 6, 10, -1, -1, 138, -1, -1, -1, { "Core(TM) i3-L##G4", 12 }, "Core i3 (Lakefield)" }, + { 6, 12, -1, -1, 156, -1, -1, -1, { "Pentium(R) Silver N6###", 8 }, "Pentium Silver (Jasper Lake)" }, + { 6, 12, -1, -1, 156, -1, -1, -1, { "Celeron(R) N[45]###", 6 }, "Celeron (Jasper Lake)" }, /* Tiger Lake CPUs (2020, 11th gen, 10nm, mobile processors): */ - { 6, 12, -1, -1, 140, -1, -1, -1, NC, CORE_|_I_|_9 ,_11xxx, "Tiger Lake (Core i9)" }, - { 6, 12, -1, -1, 140, -1, -1, -1, NC, CORE_|_I_|_7 ,_11xxx, "Tiger Lake (Core i7)" }, - { 6, 12, -1, -1, 140, -1, -1, -1, NC, CORE_|_I_|_5 ,_11xxx, "Tiger Lake (Core i5)" }, - { 6, 12, -1, -1, 140, -1, -1, -1, NC, CORE_|_I_|_3 ,_11xxx, "Tiger Lake (Core i3)" }, - { 6, 12, -1, -1, 140, 2, -1, -1, NC, PENTIUM_ , 0, "Tiger Lake (Pentium)" }, - { 6, 12, -1, -1, 140, 2, -1, -1, NC, CELERON_ , 0, "Tiger Lake (Celeron)" }, + { 6, 12, -1, -1, 140, -1, -1, -1, { "Core(TM) i7-11##G7", 12 }, "Core i7 (Tiger Lake-UP3)" }, + { 6, 12, -1, -1, 140, -1, -1, -1, { "Core(TM) i5-11##G7", 12 }, "Core i5 (Tiger Lake-UP3)" }, + { 6, 12, -1, -1, 140, -1, -1, -1, { "Core(TM) i3-11##G7", 12 }, "Core i3 (Tiger Lake-UP3)" }, + { 6, 12, -1, -1, 140, 2, -1, -1, { "Pentium(R) Gold 7###", 6 }, "Pentium Gold (Tiger Lake-UP3)" }, + { 6, 12, -1, -1, 140, 2, -1, -1, { "Celeron(R) 6###", 4 }, "Celeron (Tiger Lake-UP3)" }, /* Alder Lake CPUs (2021, 12th gen, 10nm) => https://en.wikichip.org/wiki/intel/microarchitectures/alder_lake */ - { 6, 7, -1, -1, 151, -1, -1, -1, NC, CORE_|_I_|_9 , _12xxx, "Alder Lake-S (Core i9)" }, - { 6, 7, -1, -1, 151, -1, -1, -1, NC, CORE_|_I_|_7 , _12xxx, "Alder Lake-S (Core i7)" }, - { 6, 7, -1, -1, 151, -1, -1, -1, NC, CORE_|_I_|_5 , _12xxx, "Alder Lake-S (Core i5)" }, - { 6, 7, -1, -1, 151, -1, -1, -1, NC, CORE_|_I_|_3 , _12xxx, "Alder Lake-S (Core i3)" }, - { 6, 7, -1, -1, 151, -1, -1, -1, NC, PENTIUM_ , 0, "Alder Lake-S (Pentium)" }, - { 6, 7, -1, -1, 151, -1, -1, -1, NC, CELERON_ , 0, "Alder Lake-S (Celeron)" }, - { 6, 7, -1, -1, 151, -1, -1, -1, NC, CORE_|_I_|_9|_H|_X, _12xxx, "Alder Lake-HX (Core i9)" }, - { 6, 7, -1, -1, 151, -1, -1, -1, NC, CORE_|_I_|_7|_H|_X, _12xxx, "Alder Lake-HX (Core i7)" }, - { 6, 7, -1, -1, 151, -1, -1, -1, NC, CORE_|_I_|_5|_H|_X, _12xxx, "Alder Lake-HX (Core i5)" }, - { 6, 10, -1, -1, 154, -1, -1, -1, NC, CORE_|_I_|_7|_P , 0, "Alder Lake-P (Core i7)" }, - { 6, 10, -1, -1, 154, -1, -1, -1, NC, CORE_|_I_|_5|_P , 0, "Alder Lake-P (Core i5)" }, - { 6, 10, -1, -1, 154, -1, -1, -1, NC, CORE_|_I_|_3|_P , 0, "Alder Lake-P (Core i3)" }, - { 6, 10, -1, -1, 154, -1, -1, -1, NC, CORE_|_I_|_7|_U , 0, "Alder Lake-U (Core i7)" }, - { 6, 10, -1, -1, 154, -1, -1, -1, NC, CORE_|_I_|_5|_U , 0, "Alder Lake-U (Core i5)" }, - { 6, 10, -1, -1, 154, -1, -1, -1, NC, CORE_|_I_|_3|_U , 0, "Alder Lake-U (Core i3)" }, - { 6, 10, -1, -1, 154, -1, -1, -1, NC, PENTIUM_ , 0, "Alder Lake-U (Pentium)" }, - { 6, 10, -1, -1, 154, -1, -1, -1, NC, CELERON_ , 0, "Alder Lake-U (Celeron)" }, - { 6, 10, -1, -1, 154, -1, -1, -1, NC, CORE_|_I_|_9|_H , _12xxx, "Alder Lake-H (Core i9)" }, - { 6, 10, -1, -1, 154, -1, -1, -1, NC, CORE_|_I_|_7|_H , _12xxx, "Alder Lake-H (Core i7)" }, - { 6, 10, -1, -1, 154, -1, -1, -1, NC, CORE_|_I_|_5|_H , _12xxx, "Alder Lake-H (Core i5)" }, - { 6, 10, -1, -1, 154, -1, -1, -1, NC, CORE_|_I_|_7|_U|_L, 0, "Alder Lake-PS (Core i7)" }, - { 6, 10, -1, -1, 154, -1, -1, -1, NC, CORE_|_I_|_5|_U|_L, 0, "Alder Lake-PS (Core i5)" }, - { 6, 10, -1, -1, 154, -1, -1, -1, NC, CORE_|_I_|_3|_U|_L, 0, "Alder Lake-PS (Core i3)" }, - { 6, 10, -1, -1, 154, -1, -1, -1, NC, CELERON_|_L , 0, "Alder Lake-PS (Celeron)" }, - { 6, 10, -1, -1, 154, -1, -1, -1, NC, CORE_|_I_|_7|_H|_L, _12xxx, "Alder Lake-PS (Core i7)" }, - { 6, 10, -1, -1, 154, -1, -1, -1, NC, CORE_|_I_|_5|_H|_L, _12xxx, "Alder Lake-PS (Core i5)" }, - { 6, 10, -1, -1, 154, -1, -1, -1, NC, CORE_|_I_|_3|_H|_L, _12xxx, "Alder Lake-PS (Core i3)" }, - { 6, 14, -1, -1, 190, -1, -1, -1, NC, CORE_|_I_|_3|_N_ , 0, "Alder Lake-N (Core i3)" }, /* Core i3 N300 + Core i3 N305 */ - { 6, 14, -1, -1, 190, 4, -1, -1, NC, _N_ , 0, "Alder Lake-N (Intel Processor)" }, - { 6, 14, -1, -1, 190, 2, -1, -1, NC, _N_ , 0, "Alder Lake-N (Intel Processor)" }, /* Intel Processor N50 */ - { 6, 14, -1, -1, 190, -1, -1, -1, NC, ATOM_ , 0, "Alder Lake-N (Atom)" }, + { 6, 7, -1, -1, 151, -1, -1, -1, { "Core(TM) i9-12###", 8 }, "Core i9 (Alder Lake-S)" }, + { 6, 7, -1, -1, 151, -1, -1, -1, { "Core(TM) i7-12###", 8 }, "Core i7 (Alder Lake-S)" }, + { 6, 7, -1, -1, 151, -1, -1, -1, { "Core(TM) i5-12###", 8 }, "Core i5 (Alder Lake-S)" }, + { 6, 7, -1, -1, 151, -1, -1, -1, { "Core(TM) i3-12###", 8 }, "Core i3 (Alder Lake-S)" }, + { 6, 7, -1, -1, 151, -1, -1, -1, { "Pentium(R) Gold G7###", 8 }, "Pentium Gold (Alder Lake-S)" }, + { 6, 7, -1, -1, 151, -1, -1, -1, { "Celeron(R) G6###", 6 }, "Celeron (Alder Lake-S)" }, + { 6, 7, -1, -1, 151, -1, -1, -1, { "Core(TM) i9-12###HX", 12 }, "Core i9 (Alder Lake-HX)" }, + { 6, 7, -1, -1, 151, -1, -1, -1, { "Core(TM) i7-12###HX", 12 }, "Core i7 (Alder Lake-HX)" }, + { 6, 7, -1, -1, 151, -1, -1, -1, { "Core(TM) i5-12###HX", 12 }, "Core i5 (Alder Lake-HX)" }, + { 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i7-12##P", 10 }, "Core i7 (Alder Lake-P)" }, + { 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i5-12##P", 10 }, "Core i5 (Alder Lake-P)" }, + { 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i3-12##P", 10 }, "Core i3 (Alder Lake-P)" }, + { 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i7-12##U", 10 }, "Core i7 (Alder Lake-U)" }, + { 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i5-12##U", 10 }, "Core i5 (Alder Lake-U)" }, + { 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i3-12##U", 10 }, "Core i3 (Alder Lake-U)" }, + { 6, 10, -1, -1, 154, -1, -1, -1, { "Pentium(R) Gold 8###", 6 }, "Pentium Gold (Alder Lake-U)" }, + { 6, 10, -1, -1, 154, -1, -1, -1, { "Celeron(R) 7###", 4 }, "Celeron (Alder Lake-U)" }, + { 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i9-12###H", 10 }, "Core i9 (Alder Lake-H)" }, + { 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i7-12###H", 10 }, "Core i7 (Alder Lake-H)" }, + { 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i5-12###H", 10 }, "Core i5 (Alder Lake-H)" }, + { 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i7-12##UL", 12 }, "Core i7 (Alder Lake-PS)" }, + { 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i5-12##UL", 12 }, "Core i5 (Alder Lake-PS)" }, + { 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i3-12##UL", 12 }, "Core i3 (Alder Lake-PS)" }, + { 6, 10, -1, -1, 154, -1, -1, -1, { "Celeron(R) 7###L", 6 }, "Celeron (Alder Lake-PS)" }, + { 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i7-12###HL", 12 }, "Core i7 (Alder Lake-PS)" }, + { 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i5-12###HL", 12 }, "Core i5 (Alder Lake-PS)" }, + { 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i3-12###HL", 12 }, "Core i3 (Alder Lake-PS)" }, + { 6, 14, -1, -1, 190, -1, -1, -1, { "Core(TM) i3-N3##", 10 }, "Core i3 (Alder Lake-N)" }, /* Core i3 N300 + Core i3 N305 */ + { 6, 14, -1, -1, 190, 4, -1, -1, { "Processor N##", 4 }, "Intel Processor (Alder Lake-N)" }, + { 6, 14, -1, -1, 190, 2, -1, -1, { "Processor N##", 4 }, "Intel Processor (Alder Lake-N)" }, /* Intel Processor N50 */ + { 6, 14, -1, -1, 190, -1, -1, -1, { "Atom(TM) x7###E", 8 }, "Atom (Alder Lake-N)" }, /* Twin Lake CPUs (2025, Intel 7) => https://en.wikichip.org/wiki/intel/microarchitectures/twin_lake */ - { 6, 14, -1, -1, 190, 8, -1, -1, NC, CORE_|_3|_N_ , _x5x, "Twin Lake-N (Core 3)" }, /* Core 3 N350 + Core 3 N355 */ - { 6, 14, -1, -1, 190, 4, -1, -1, NC, _N_ , _x5x, "Twin Lake-N (Intel Processor)" }, /* Intel Processor N150 + Intel Processor N150 */ + { 6, 14, -1, -1, 190, 8, -1, -1, { "Core(TM) 3 N#5#", 8 }, "Core 3 (Twin Lake-N)" }, /* Core 3 N350 + Core 3 N355 */ + { 6, 14, -1, -1, 190, 4, -1, -1, { "Processor N#5#", 6 }, "Intel Processor (Twin Lake-N)" }, /* Intel Processor N150 + Intel Processor N150 */ /* Raptor Lake CPUs (2022, 13th Core i gen, Intel 7) => https://en.wikichip.org/wiki/intel/microarchitectures/raptor_lake */ - { 6, 15, -1, -1, 191, -1, -1, -1, NC, CORE_|_I_|_5 , _13xxx, "Raptor Lake-S (Core i5)" }, // "Golden Cove" cores - { 6, 15, -1, -1, 191, -1, -1, -1, NC, CORE_|_I_|_3 , _13xxx, "Raptor Lake-S (Core i3)" }, // "Golden Cove" cores - { 6, 7, -1, -1, 183, -1, -1, -1, NC, CORE_|_I_|_9 , _13xxx, "Raptor Lake-S (Core i9)" }, - { 6, 7, -1, -1, 183, -1, -1, -1, NC, CORE_|_I_|_7 , _13xxx, "Raptor Lake-S (Core i7)" }, - { 6, 7, -1, -1, 183, -1, -1, -1, NC, CORE_|_I_|_5 , _13xxx, "Raptor Lake-S (Core i5)" }, - { 6, 7, -1, -1, 183, -1, -1, -1, NC, CORE_|_I_|_3 , _13xxx, "Raptor Lake-S (Core i3)" }, - { 6, 7, -1, -1, 183, -1, -1, -1, NC, CORE_|_I_|_9|_H|_X, _13xxx, "Raptor Lake-HX (Core i9)" }, - { 6, 7, -1, -1, 183, -1, -1, -1, NC, CORE_|_I_|_7|_H|_X, _13xxx, "Raptor Lake-HX (Core i7)" }, - { 6, 7, -1, -1, 183, -1, -1, -1, NC, CORE_|_I_|_5|_H|_X, _13xxx, "Raptor Lake-HX (Core i5)" }, - { 6, 10, 2, -1, 186, -1, -1, -1, NC, CORE_|_I_|_7|_P , 0, "Raptor Lake-P (Core i7)" }, - { 6, 10, 2, -1, 186, -1, -1, -1, NC, CORE_|_I_|_5|_P , 0, "Raptor Lake-P (Core i5)" }, - { 6, 10, 3, -1, 186, -1, -1, -1, NC, CORE_|_I_|_7|_U , 0, "Raptor Lake-U (Core i7)" }, - { 6, 10, 3, -1, 186, -1, -1, -1, NC, CORE_|_I_|_5|_U , 0, "Raptor Lake-U (Core i5)" }, - { 6, 10, 3, -1, 186, -1, -1, -1, NC, CORE_|_I_|_3|_U , 0, "Raptor Lake-U (Core i3)" }, - { 6, 10, 3, -1, 186, -1, -1, -1, NC, _U_ , 0, "Raptor Lake-U (Intel Processor)" }, /* Intel Processor U300 */ - { 6, 10, -1, -1, 186, -1, -1, -1, NC, CORE_|_I_|_9|_H , _13xxx, "Raptor Lake-H (Core i9)" }, - { 6, 10, -1, -1, 186, -1, -1, -1, NC, CORE_|_I_|_7|_H , _13xxx, "Raptor Lake-H (Core i7)" }, - { 6, 10, -1, -1, 186, -1, -1, -1, NC, CORE_|_I_|_5|_H , _13xxx, "Raptor Lake-H (Core i5)" }, + { 6, 15, -1, -1, 191, -1, -1, -1, { "Core(TM) i5-13###", 8 }, "Core i5 (Raptor Lake-S)" }, // "Golden Cove" cores + { 6, 15, -1, -1, 191, -1, -1, -1, { "Core(TM) i3-13###", 8 }, "Core i3 (Raptor Lake-S)" }, // "Golden Cove" cores + { 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i9-13###", 8 }, "Core i9 (Raptor Lake-S)" }, + { 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i7-13###", 8 }, "Core i7 (Raptor Lake-S)" }, + { 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i5-13###", 8 }, "Core i5 (Raptor Lake-S)" }, + { 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i3-13###", 8 }, "Core i3 (Raptor Lake-S)" }, + { 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i9-13###HX", 12 }, "Core i9 (Raptor Lake-HX)" }, + { 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i7-13###HX", 12 }, "Core i7 (Raptor Lake-HX)" }, + { 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i5-13###HX", 12 }, "Core i5 (Raptor Lake-HX)" }, + { 6, 10, 2, -1, 186, -1, -1, -1, { "Core(TM) i7-13###P", 10 }, "Core i7 (Raptor Lake-P)" }, + { 6, 10, 2, -1, 186, -1, -1, -1, { "Core(TM) i5-13###P", 10 }, "Core i5 (Raptor Lake-P)" }, + { 6, 10, 3, -1, 186, -1, -1, -1, { "Core(TM) i7-13###U", 10 }, "Core i7 (Raptor Lake-U)" }, + { 6, 10, 3, -1, 186, -1, -1, -1, { "Core(TM) i5-13###U", 10 }, "Core i5 (Raptor Lake-U)" }, + { 6, 10, 3, -1, 186, -1, -1, -1, { "Core(TM) i3-13###U", 10 }, "Core i3 (Raptor Lake-U)" }, + { 6, 10, 3, -1, 186, -1, -1, -1, { "Processor U300", 6 }, "Intel Processor (Raptor Lake-U)" }, /* Intel Processor U300 */ + { 6, 10, -1, -1, 186, -1, -1, -1, { "Core(TM) i9-13###H", 10 }, "Core i9 (Raptor Lake-H)" }, + { 6, 10, -1, -1, 186, -1, -1, -1, { "Core(TM) i7-13###H", 10 }, "Core i7 (Raptor Lake-H)" }, + { 6, 10, -1, -1, 186, -1, -1, -1, { "Core(TM) i5-13###H", 10 }, "Core i5 (Raptor Lake-H)" }, /* Raptor Lake Refresh CPUs (2023, 14th Core i gen, Intel 7) => https://en.wikipedia.org/wiki/Raptor_Lake#List_of_14th_generation_Raptor_Lake_processors */ - { 6, 7, -1, -1, 183, -1, -1, -1, NC, CORE_|_I_|_9 , _14xxx, "Raptor Lake-S (Core i9)" }, - { 6, 7, -1, -1, 183, -1, -1, -1, NC, CORE_|_I_|_7 , _14xxx, "Raptor Lake-S (Core i7)" }, - { 6, 7, -1, -1, 183, -1, -1, -1, NC, CORE_|_I_|_5 , _14xxx, "Raptor Lake-S (Core i5)" }, - { 6, 7, -1, -1, 183, -1, -1, -1, NC, CORE_|_I_|_3 , _14xxx, "Raptor Lake-S (Core i3)" }, - { 6, 7, -1, -1, 183, 2, -1, -1, NC, 0 , 0, "Raptor Lake-S (Intel Processor )"}, /* Intel Processor 300 + Intel Processor 300T */ - { 6, 7, -1, -1, 183, -1, -1, -1, NC, CORE_|_I_|_9|_H|_X, _14xxx, "Raptor Lake-HX (Core i9)" }, - { 6, 7, -1, -1, 183, -1, -1, -1, NC, CORE_|_I_|_7|_H|_X, _14xxx, "Raptor Lake-HX (Core i7)" }, - { 6, 7, -1, -1, 183, -1, -1, -1, NC, CORE_|_I_|_5|_H|_X, _14xxx, "Raptor Lake-HX (Core i5)" }, - { 6, 7, -1, -1, 183, -1, -1, -1, NC, XEON_ , 0, "Raptor Lake (Xeon-E)" }, - { 6, 7, -1, -1, 183, -1, -1, -1, NC, CORE_|_7|_U , _1xx, "Raptor Lake-U (Core 7)" }, /* Core 7 150U */ - { 6, 7, -1, -1, 183, -1, -1, -1, NC, CORE_|_5|_U , _1xx, "Raptor Lake-U (Core 5)" }, /* Core 5 120U */ - { 6, 7, -1, -1, 183, -1, -1, -1, NC, CORE_|_3|_U , _1xx, "Raptor Lake-U (Core 3)" }, /* Core 3 100U */ + { 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i9-14###", 8 }, "Core i9 (Raptor Lake-S)" }, + { 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i7-14###", 8 }, "Core i7 (Raptor Lake-S)" }, + { 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i5-14###", 8 }, "Core i5 (Raptor Lake-S)" }, + { 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i3-14###", 8 }, "Core i3 (Raptor Lake-S)" }, + { 6, 7, -1, -1, 183, 2, -1, -1, { "Processor 300", 4 }, "Intel Processor (Raptor Lake-S)"}, /* Intel Processor 300 + Intel Processor 300T */ + { 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i9-14###HX", 12 }, "Core i9 (Raptor Lake-HX)" }, + { 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i7-14###HX", 12 }, "Core i7 (Raptor Lake-HX)" }, + { 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i5-14###HX", 12 }, "Core i5 (Raptor Lake-HX)" }, + { 6, 7, -1, -1, 183, -1, -1, -1, { "Xeon(R) E-24##", 6 }, "Xeon E (Raptor Lake)" }, + { 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) 7 1##U", 8 }, "Core 7 (Raptor Lake-U)" }, /* Core 7 150U */ + { 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) 5 1##U", 8 }, "Core 5 (Raptor Lake-U)" }, /* Core 5 120U */ + { 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) 3 1##U", 8 }, "Core 3 (Raptor Lake-U)" }, /* Core 3 100U */ /* Raptor Lake Re-refresh CPUs (2025, Core Series 2 processors Intel 7) => https://en.wikipedia.org/wiki/Raptor_Lake#List_of_Core_Series_2_processors */ - { 6, 7, -1, -1, 183, -1, -1, -1, NC, CORE_|_7|_U , _2xx, "Raptor Lake-U (Core 7)" }, /* Core 7 250U */ - { 6, 7, -1, -1, 183, -1, -1, -1, NC, CORE_|_5|_U , _2xx, "Raptor Lake-U (Core 5)" }, /* Core 5 220U */ - { 6, 7, -1, -1, 183, -1, -1, -1, NC, CORE_|_9|_H , _2xx, "Raptor Lake-H (Core 9)" }, /* Core 9 270H */ - { 6, 7, -1, -1, 183, -1, -1, -1, NC, CORE_|_7|_H , _2xx, "Raptor Lake-H (Core 7)" }, /* Core 7 240H + Core 7 250H */ - { 6, 7, -1, -1, 183, -1, -1, -1, NC, CORE_|_5|_H , _2xx, "Raptor Lake-H (Core 5)" }, /* Core 5 210H + Core 5 220H */ + { 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) 7 2##U", 8 }, "Core 7 (Raptor Lake-U)" }, /* Core 7 250U */ + { 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) 5 2##U", 8 }, "Core 5 (Raptor Lake-U)" }, /* Core 5 220U */ + { 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) 9 2##H", 8 }, "Core 9 (Raptor Lake-H)" }, /* Core 9 270H */ + { 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) 7 2##H", 8 }, "Core 7 (Raptor Lake-H)" }, /* Core 7 240H + Core 7 250H */ + { 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) 5 2##H", 8 }, "Core 5 (Raptor Lake-H)" }, /* Core 5 210H + Core 5 220H */ /* Sapphire Rapids CPUs (2023, 4th Xeon Scalable gen, Intel 7) => https://en.wikichip.org/wiki/intel/microarchitectures/sapphire_rapids */ - { 6, 15, -1, -1, 143, -1, -1, -1, NC, XEON_|_W_|_9 , _x4xx, "Sapphire Rapids-WS (Xeon w9)" }, - { 6, 15, -1, -1, 143, -1, -1, -1, NC, XEON_|_W_|_7 , _x4xx, "Sapphire Rapids-WS (Xeon w7)" }, - { 6, 15, -1, -1, 143, -1, -1, -1, NC, XEON_|_W_|_5 , _x4xx, "Sapphire Rapids-WS (Xeon w5)" }, - { 6, 15, -1, -1, 143, -1, -1, -1, NC, XEON_|_W_|_3 , _x4xx, "Sapphire Rapids-WS (Xeon w3)" }, - { 6, 15, -1, -1, 143, -1, -1, -1, NC, XEON_|_MAX_ , _x4xx, "Sapphire Rapids-HBM (Xeon Max)" }, - { 6, 15, -1, -1, 143, -1, -1, -1, NC, XEON_|_PLATINIUM_, _x4xx, "Sapphire Rapids-SP (Xeon Platinum)" }, - { 6, 15, -1, -1, 143, -1, -1, -1, NC, XEON_|_GOLD_ , _x4xx, "Sapphire Rapids-SP (Xeon Gold)" }, - { 6, 15, -1, -1, 143, -1, -1, -1, NC, XEON_|_SILVER_ , _x4xx, "Sapphire Rapids-SP (Xeon Silver)" }, - { 6, 15, -1, -1, 143, -1, -1, -1, NC, XEON_|_BRONZE_ , _x4xx, "Sapphire Rapids-SP (Xeon Bronze)" }, + { 6, 15, -1, -1, 143, -1, -1, -1, { "Xeon(R) w9-#4##", 6 }, "Xeon w9 (Sapphire Rapids-WS)" }, + { 6, 15, -1, -1, 143, -1, -1, -1, { "Xeon(R) w7-#4##", 6 }, "Xeon w7 (Sapphire Rapids-WS)" }, + { 6, 15, -1, -1, 143, -1, -1, -1, { "Xeon(R) w5-#4##", 6 }, "Xeon w5 (Sapphire Rapids-WS)" }, + { 6, 15, -1, -1, 143, -1, -1, -1, { "Xeon(R) w3-#4##", 6 }, "Xeon w3 (Sapphire Rapids-WS)" }, + { 6, 15, -1, -1, 143, -1, -1, -1, { "Xeon(R) Max #4##", 6 }, "Xeon Max (Sapphire Rapids-HBM)" }, + { 6, 15, -1, -1, 143, -1, -1, -1, { "Xeon(R) Platinum #4##", 6 }, "Xeon Platinum (Sapphire Rapids-SP)" }, + { 6, 15, -1, -1, 143, -1, -1, -1, { "Xeon(R) Gold #4##", 6 }, "Xeon Gold (Sapphire Rapids-SP)" }, + { 6, 15, -1, -1, 143, -1, -1, -1, { "Xeon(R) Silver #4##", 6 }, "Xeon Silver (Sapphire Rapids-SP)" }, + { 6, 15, -1, -1, 143, -1, -1, -1, { "Xeon(R) Bronze #4##", 6 }, "Xeon Bronze (Sapphire Rapids-SP)" }, /* Emerald Rapids CPUs (2023, 5th Xeon Scalable gen, Intel 7) => https://en.wikichip.org/wiki/intel/microarchitectures/emerald_rapids */ - { 6, 15, -1, -1, 207, -1, -1, -1, NC, XEON_|_PLATINIUM_, _x5xx, "Emerald Rapids-SP (Xeon Platinum)" }, // Xeon Platinum (8500) - { 6, 15, -1, -1, 207, -1, -1, -1, NC, XEON_|_GOLD_ , _x5xx, "Emerald Rapids-SP (Xeon Gold)" }, // Xeon Gold (5500 and 6500) - { 6, 15, -1, -1, 207, -1, -1, -1, NC, XEON_|_SILVER_ , _x5xx, "Emerald Rapids-SP (Xeon Silver)" }, // Xeon Silver (4500) - { 6, 15, -1, -1, 207, -1, -1, -1, NC, XEON_|_BRONZE_ , _x5xx, "Emerald Rapids-SP (Xeon Bronze)" }, // Xeon Bronze (3500) + { 6, 15, -1, -1, 207, -1, -1, -1, { "Xeon(R) Platinum #5##", 6 }, "Xeon Platinum (Emerald Rapids-SP)" }, // Xeon Platinum (8500) + { 6, 15, -1, -1, 207, -1, -1, -1, { "Xeon(R) Gold #5##", 6 }, "Xeon Gold (Emerald Rapids-SP)" }, // Xeon Gold (5500 and 6500) + { 6, 15, -1, -1, 207, -1, -1, -1, { "Xeon(R) Silver #5##", 6 }, "Xeon Silver (Emerald Rapids-SP)" }, // Xeon Silver (4500) + { 6, 15, -1, -1, 207, -1, -1, -1, { "Xeon(R) Bronze #5##", 6 }, "Xeon Bronze (Emerald Rapids-SP)" }, // Xeon Bronze (3500) /* Meteor Lake CPUs (2023, Core Ultra Series 1 processors, Intel 4) => https://en.wikichip.org/wiki/intel/microarchitectures/meteor_lake */ - { 6, 10, -1, -1, 170, -1, -1, -1, NC, CORE_|_ULTRA_|_9|_H, _1xx, "Meteor Lake-H (Core Ultra 9)" }, - { 6, 10, -1, -1, 170, -1, -1, -1, NC, CORE_|_ULTRA_|_7|_H, _1xx, "Meteor Lake-H (Core Ultra 7)" }, - { 6, 10, -1, -1, 170, -1, -1, -1, NC, CORE_|_ULTRA_|_5|_H, _1xx, "Meteor Lake-H (Core Ultra 5)" }, - { 6, 10, -1, -1, 170, -1, -1, -1, NC, CORE_|_ULTRA_|_7|_U, _1xx, "Meteor Lake-U (Core Ultra 7)" }, - { 6, 10, -1, -1, 170, -1, -1, -1, NC, CORE_|_ULTRA_|_5|_U, _1xx, "Meteor Lake-U (Core Ultra 5)" }, + { 6, 10, -1, -1, 170, -1, -1, -1, { "Core(TM) Ultra 9 1##H", 10 }, "Core Ultra 9 (Meteor Lake-H)" }, + { 6, 10, -1, -1, 170, -1, -1, -1, { "Core(TM) Ultra 7 1##H", 10 }, "Core Ultra 7 (Meteor Lake-H)" }, + { 6, 10, -1, -1, 170, -1, -1, -1, { "Core(TM) Ultra 5 1##H", 10 }, "Core Ultra 5 (Meteor Lake-H)" }, + { 6, 10, -1, -1, 170, -1, -1, -1, { "Core(TM) Ultra 7 1##U", 10 }, "Core Ultra 7 (Meteor Lake-U)" }, + { 6, 10, -1, -1, 170, -1, -1, -1, { "Core(TM) Ultra 5 1##U", 10 }, "Core Ultra 5 (Meteor Lake-U)" }, /* Arrow Lake CPUs (2024, Core Ultra Series 2 processors, TSMC N3B) => https://en.wikichip.org/wiki/intel/microarchitectures/arrow_lake */ - { 6, 6, -1, -1, 198, -1, -1, -1, NC, CORE_|_ULTRA_|_9, _2xx, "Arrow Lake-S (Core Ultra 9)" }, - { 6, 6, -1, -1, 198, -1, -1, -1, NC, CORE_|_ULTRA_|_7, _2xx, "Arrow Lake-S (Core Ultra 7)" }, - { 6, 6, -1, -1, 198, -1, -1, -1, NC, CORE_|_ULTRA_|_5, _2xx, "Arrow Lake-S (Core Ultra 5)" }, - { 6, 6, -1, -1, 181, -1, -1, -1, NC, CORE_|_ULTRA_|_7|_U, _2xx, "Arrow Lake-U (Core Ultra 7)" }, /* Core Ultra 7 255U + Core Ultra 7 265U */ - { 6, 6, -1, -1, 181, -1, -1, -1, NC, CORE_|_ULTRA_|_5|_U, _2xx, "Arrow Lake-U (Core Ultra 5)" }, /* Core Ultra 5 225U + Core Ultra 7 235U */ - { 6, 6, -1, -1, 197, -1, -1, -1, NC, CORE_|_ULTRA_|_9|_H, _2xx, "Arrow Lake-H (Core Ultra 9)" }, /* Core Ultra 9 285H */ - { 6, 6, -1, -1, 197, -1, -1, -1, NC, CORE_|_ULTRA_|_7|_H, _2xx, "Arrow Lake-H (Core Ultra 7)" }, /* Core Ultra 7 255H + Core Ultra 7 265H */ - { 6, 6, -1, -1, 197, -1, -1, -1, NC, CORE_|_ULTRA_|_5|_H, _2xx, "Arrow Lake-H (Core Ultra 5)" }, /* Core Ultra 5 225H + Core Ultra 7 235H */ + { 6, 6, -1, -1, 198, -1, -1, -1, { "Core(TM) Ultra 9 2##", 8 }, "Core Ultra 9 (Arrow Lake-S)" }, + { 6, 6, -1, -1, 198, -1, -1, -1, { "Core(TM) Ultra 7 2##", 8 }, "Core Ultra 7 (Arrow Lake-S)" }, + { 6, 6, -1, -1, 198, -1, -1, -1, { "Core(TM) Ultra 5 2##", 8 }, "Core Ultra 5 (Arrow Lake-S)" }, + { 6, 6, -1, -1, 181, -1, -1, -1, { "Core(TM) Ultra 7 2##U", 10 }, "Core Ultra 7 (Arrow Lake-U)" }, /* Core Ultra 7 255U + Core Ultra 7 265U */ + { 6, 6, -1, -1, 181, -1, -1, -1, { "Core(TM) Ultra 5 2##U", 10 }, "Core Ultra 5 (Arrow Lake-U)" }, /* Core Ultra 5 225U + Core Ultra 7 235U */ + { 6, 6, -1, -1, 197, -1, -1, -1, { "Core(TM) Ultra 9 2##H", 10 }, "Core Ultra 9 (Arrow Lake-H)" }, /* Core Ultra 9 285H */ + { 6, 6, -1, -1, 197, -1, -1, -1, { "Core(TM) Ultra 7 2##H", 10 }, "Core Ultra 7 (Arrow Lake-H)" }, /* Core Ultra 7 255H + Core Ultra 7 265H */ + { 6, 6, -1, -1, 197, -1, -1, -1, { "Core(TM) Ultra 5 2##H", 10 }, "Core Ultra 5 (Arrow Lake-H)" }, /* Core Ultra 5 225H + Core Ultra 7 235H */ + /* Lunar Lake CPUs (2024, Core Ultra Series 2 processors, TSMC N3B) => https://en.wikichip.org/wiki/intel/microarchitectures/lunar_lake */ - { 6, 13, -1, -1, 189, -1, -1, -1, NC, CORE_|_ULTRA_|_9|_V, _1xx, "Lunar Lake-V (Core Ultra 9)" }, - { 6, 13, -1, -1, 189, -1, -1, -1, NC, CORE_|_ULTRA_|_7|_V, _1xx, "Lunar Lake-V (Core Ultra 7)" }, - { 6, 13, -1, -1, 189, -1, -1, -1, NC, CORE_|_ULTRA_|_5|_V, _1xx, "Lunar Lake-V (Core Ultra 5)" }, - /* F M S EF EM #cores L2$ L3$ BC ModelBits ModelCode Name */ + { 6, 13, -1, -1, 189, -1, -1, -1, { "Core(TM) Ultra 9 2##V", 10 }, "Core Ultra 9 (Lunar Lake-V)" }, + { 6, 13, -1, -1, 189, -1, -1, -1, { "Core(TM) Ultra 7 2##V", 10 }, "Core Ultra 7 (Lunar Lake-V)" }, + { 6, 13, -1, -1, 189, -1, -1, -1, { "Core(TM) Ultra 5 2##V", 10 }, "Core Ultra 5 (Lunar Lake-V)" }, +// F M S EF EM #cores L2$ L3$ Pattern Name /* Itaniums */ - { 7, -1, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Itanium" }, - { 15, -1, -1, 16, -1, 1, -1, -1, NC, 0 , 0, "Itanium 2" }, + { 7, -1, -1, -1, -1, 1, -1, -1, { "", 0 }, "Itanium" }, + { 15, -1, -1, 16, -1, 1, -1, -1, { "", 0 }, "Itanium 2" }, + }; @@ -772,324 +702,6 @@ static int decode_intel_extended_topology(struct cpu_raw_data_t* raw, struct cpu return 1; } -static intel_code_and_bits_t get_brand_code_and_bits(struct cpu_id_t* data) -{ - intel_code_t code = (intel_code_t) NC; - intel_code_and_bits_t result; - uint64_t bits = 0; - int i = 0; - const char* bs = data->brand_str; - const char* s; - const size_t n = strlen(bs); - const struct { intel_code_t c; const char *search; } matchtable[] = { - { PENTIUM_M, "Pentium(R) M" }, - { CORE_SOLO, "Pentium(R) Dual" }, - { PENTIUM_D, "Pentium(R) D" }, - { CORE_SOLO, "Genuine Intel(R) CPU" }, - { CORE_SOLO, "Intel(R) Core(TM)" }, - { DIAMONDVILLE, "CPU [N ][23]## " }, - { SILVERTHORNE, "CPU Z" }, - { PINEVIEW, "CPU [ND][45]## " }, - { CEDARVIEW, "CPU [ND]#### " }, - }; - - const struct { uint64_t bit; const char* search; } bit_matchtable[] = { - { XEON_, "Xeon" }, - { _MP_, " MP" }, - { ATOM_, "Atom" }, - { MOBILE_, "Mobile" }, - { CELERON_, "Celeron" }, - { PENTIUM_, "Pentium" }, - { _BRONZE_, "Bronze" }, - { _SILVER_, "Silver" }, - { _GOLD_, "Gold" }, - { _PLATINIUM_, "Platinum" }, - { _MAX_, "Max" }, - }; - - for (i = 0; i < COUNT_OF(bit_matchtable); i++) { - if (match_pattern(bs, bit_matchtable[i].search)) - bits |= bit_matchtable[i].bit; - } - - if ((i = match_pattern(bs, "Core(TM) [im][3579]")) != 0) { - bits |= CORE_; - i--; - switch (bs[i + 9]) { - case 'i': bits |= _I_; break; - case 'm': bits |= _M_; break; - } - switch (bs[i + 10]) { - case '3': bits |= _3; break; - case '5': bits |= _5; break; - case '7': bits |= _7; break; - case '9': bits |= _9; break; - } - for(i = i + 11; i < n; i++) { - switch (bs[i]) { - case 'H': bits |= _H; break; - case 'K': bits |= _K; break; - case 'N': bits |= _N; break; - case 'P': bits |= _P; break; - case 'S': bits |= _S; break; - case 'U': bits |= _U; break; - case 'X': bits |= _X; break; - } - } - } - /* https://www.intel.com/content/www/us/en/ark/products/series/236798/intel-core-processors-series-1.html - https://www.intel.com/content/www/us/en/ark/products/series/238783/intel-core-processors-series-2.html */ - else if ((i = match_pattern(bs, "Core(TM) [3579]")) != 0) { - bits |= CORE_; - i--; - switch (bs[i + 9]) { - case '3': bits |= _3; break; - case '5': bits |= _5; break; - case '7': bits |= _7; break; - case '9': bits |= _9; break; - } - for(i = i + 10; i < n; i++) { - switch (bs[i]) { - case 'E': bits |= _E; break; - case 'F': bits |= _F; break; - case 'H': bits |= _H; break; - case 'L': bits |= _L; break; - case 'T': bits |= _T; break; - case 'U': bits |= _U; break; - } - } - } - /* https://www.intel.com/content/www/us/en/ark/products/series/236803/intel-core-ultra-processors-series-1.html - https://www.intel.com/content/www/us/en/ark/products/series/241071/intel-core-ultra-processors-series-2.html */ - else if ((i = match_pattern(bs, "Core(TM) Ultra [3579]")) != 0) { - bits |= CORE_ | _ULTRA_; - i--; - switch (bs[i + 15]) { - case '3': bits |= _3; break; - case '5': bits |= _5; break; - case '7': bits |= _7; break; - case '9': bits |= _9; break; - } - for(i = i + 16; i < n; i++) { - switch (bs[i]) { - case 'F': bits |= _F; break; - case 'H': bits |= _H; break; - case 'K': bits |= _K; break; - case 'L': bits |= _L; break; - case 'T': bits |= _T; break; - case 'U': bits |= _U; break; - case 'V': bits |= _V; break; - case 'X': bits |= _X; break; - } - } - } - else if ((i = match_pattern(bs, "Xeon(R) w[3579]")) != 0) { - bits |= XEON_; - i--; - switch (bs[i + 8]) { - case 'w': bits |= _W_; break; - } - switch (bs[i + 9]) { - case '3': bits |= _3; break; - case '5': bits |= _5; break; - case '7': bits |= _7; break; - case '9': bits |= _9; break; - } - } - else if ((i = match_pattern(bs, "Xeon(R) [DW]")) != 0) { - bits |= XEON_; - i--; - switch (bs[i + 8]) { - case 'D': bits |= _D_; break; - case 'W': bits |= _W_; break; - } - } - else if ((i = match_pattern(bs, "[NU]##")) != 0) { - i--; - switch (bs[i]) { - case 'N': bits |= _N_; break; - case 'U': bits |= _U_; break; - } - } - - if (((bits & PENTIUM_) || (bits & CELERON_)) && ((i = match_pattern(bs, "[JN]")) != 0)) { - i--; - switch (bs[i]) { - case 'J': bits |= _J_; break; - case 'N': bits |= _N_; break; - } - } - - for (i = 0; i < COUNT_OF(matchtable); i++) - if (match_pattern(bs, matchtable[i].search)) { - code = matchtable[i].c; - break; - } - debugf(2, "intel matchtable result is %d\n", code); - if (bits & XEON_) { - if (match_pattern(bs, "W35##") || match_pattern(bs, "[ELXW]75##")) - bits |= _7; - else if (match_pattern(bs, "[ELXW]55##")) - code = GAINESTOWN; - else if (match_pattern(bs, "[ELXW]56##")) - code = WESTMERE; - else if (data->l3_cache > 0 && data->x86.family == 16) - /* restrict by family, since later Xeons also have L3 ... */ - code = IRWIN; - } - if (match_all(bits, XEON_ + _MP_) && data->l3_cache > 0) - code = POTOMAC; - if (code == CORE_SOLO) { - s = strstr(bs, "CPU"); - if (s) { - s += 3; - while (*s == ' ') s++; - if (*s == 'T') - bits |= MOBILE_; - } - } - if (code == CORE_SOLO) { - switch (data->num_cores) { - case 1: break; - case 2: - { - code = CORE_DUO; - if (data->num_logical_cpus > 2) - code = DUAL_CORE_HT; - break; - } - case 4: - { - code = QUAD_CORE; - if (data->num_logical_cpus > 4) - code = QUAD_CORE_HT; - break; - } - default: - code = MORE_THAN_QUADCORE; break; - } - } - - if (code == CORE_DUO && (bits & MOBILE_) && data->x86.model != 14) { - if (data->x86.ext_model < 23) { - code = MEROM; - } else { - code = PENRYN; - } - } - if (data->x86.ext_model == 23 && - (code == CORE_DUO || code == PENTIUM_D || (bits & CELERON_))) { - code = WOLFDALE; - } - - result.code = code; - result.bits = bits; - return result; -} - -static intel_model_t get_model_code(struct cpu_id_t* data) -{ - int i = 0; - int l = (int) strlen(data->brand_str); - const char *bs = data->brand_str; - int mod_flags = 0, model_no = 0, ndigs = 0; - /* If the CPU is a Core ix, then just return the model number generation: */ - if ((i = match_pattern(bs, "Core(TM) i[3579]")) != 0) { - i += 11; - if (i + 3 >= l) return UNKNOWN; - if (bs[i] == '2') return _2xxx; - if (bs[i] == '3') return _3xxx; - if (bs[i] == '4') return _4xxx; - if (bs[i] == '5') return _5xxx; - if (bs[i] == '6') return _6xxx; - if (bs[i] == '7') return _7xxx; - if (bs[i] == '8') return _8xxx; - if (bs[i] == '9') return _9xxx; - if (i + 4 >= l) return UNKNOWN; - if ((bs[i] == '1') && (bs[i+1] == '0')) return _10xxx; - if ((bs[i] == '1') && (bs[i+1] == '1')) return _11xxx; - if ((bs[i] == '1') && (bs[i+1] == '2')) return _12xxx; - if ((bs[i] == '1') && (bs[i+1] == '3')) return _13xxx; - if ((bs[i] == '1') && (bs[i+1] == '4')) return _14xxx; - return UNKNOWN; - } - else if ((i = match_pattern(bs, "Core(TM) [3579]")) != 0) { - i += 11; - if (i + 2 >= l) return UNKNOWN; - if ((bs[i] == '1') && (bs[i+1] == '5')) return _x5x; - if ((bs[i] == '2') && (bs[i+1] == '5')) return _x5x; - if ((bs[i] == '3') && (bs[i+1] == '5')) return _x5x; - return UNKNOWN; - } - else if ((i = match_pattern(bs, "Core(TM) Ultra [3579]")) != 0) { - i += 16; - if (i + 2 >= l) return UNKNOWN; - if (bs[i] == '1') return _1xx; - if (bs[i] == '2') return _2xx; - return UNKNOWN; - } - else if ((i = match_pattern(bs, "Xeon(R) [WBSGP]")) != 0) { - i = 0; - if ((i = match_pattern(bs, "Xeon(R) W-")) != 0) i += 10; - else if ((i == 0) && ((i = match_pattern(bs, "Xeon(R) Bronze")) != 0)) i += 15; - else if ((i == 0) && ((i = match_pattern(bs, "Xeon(R) Silver")) != 0)) i += 15; - else if ((i == 0) && ((i = match_pattern(bs, "Xeon(R) Gold")) != 0)) i += 13; - else if ((i == 0) && ((i = match_pattern(bs, "Xeon(R) Platinum")) != 0)) i += 17; - else if ((i == 0) && ((i = match_pattern(bs, "Xeon(R) Max")) != 0)) i += 12; - - if (i == 0) return UNKNOWN; - if (bs[i] == '1') return _x1xx; - if (bs[i] == '2') return _x2xx; - if (bs[i] == '3') return _x3xx; - if (bs[i] == '4') return _x4xx; - if (bs[i] == '5') return _x5xx; - return UNKNOWN; - } - - /* For Core2-based Xeons: */ - while (i < l - 3) { - if (bs[i] == 'C' && bs[i+1] == 'P' && bs[i+2] == 'U') - break; - i++; - } - if (i >= l - 3) return UNKNOWN; - i += 3; - while (i < l - 4 && bs[i] == ' ') i++; - if (i >= l - 4) return UNKNOWN; - while (i < l - 4 && !isdigit(bs[i])) { - if (bs[i] >= 'A' && bs[i] <= 'Z') - mod_flags |= (1 << (bs[i] - 'A')); - i++; - } - if (i >= l - 4) return UNKNOWN; - while (isdigit(bs[i])) { - ndigs++; - model_no = model_no * 10 + (int) (bs[i] - '0'); - i++; - } - if (ndigs != 4) return UNKNOWN; -#define HAVE(ch, flags) ((flags & (1 << ((int)(ch-'A')))) != 0) - switch (model_no / 100) { - case 30: return _3000; - case 31: return _3100; - case 32: - { - return (HAVE('X', mod_flags)) ? X3200 : _3200; - } - case 33: - { - return (HAVE('X', mod_flags)) ? X3300 : _3300; - } - case 51: return _5100; - case 52: return _5200; - case 53: return _5300; - case 54: return _5400; - default: - return UNKNOWN; - } -#undef HAVE -} - static void decode_intel_sgx_features(const struct cpu_raw_data_t* raw, struct cpu_id_t* data) { struct cpu_epc_t epc; @@ -1154,11 +766,6 @@ struct cpu_epc_t cpuid_get_epc(int index, const struct cpu_raw_data_t* raw) int cpuid_identify_intel(struct cpu_raw_data_t* raw, struct cpu_id_t* data, struct internal_id_info_t* internal) { - intel_code_and_bits_t brand; - intel_model_t model_code; - int i; - char* brand_code_str = NULL; - load_intel_features(raw, data); if (raw->basic_cpuid[0][EAX] >= 4) { /* Deterministic way is preferred, being more generic */ @@ -1168,29 +775,9 @@ int cpuid_identify_intel(struct cpu_raw_data_t* raw, struct cpu_id_t* data, stru } if ((raw->basic_cpuid[0][EAX] < 11) || (decode_intel_extended_topology(raw, data) == 0)) decode_number_of_cores_x86(raw, data); - data->purpose = cpuid_identify_purpose_intel(raw); decode_architecture_version_x86(data); - - brand = get_brand_code_and_bits(data); - model_code = get_model_code(data); - for (i = 0; i < COUNT_OF(intel_bcode_str); i++) { - if (brand.code == intel_bcode_str[i].code) { - brand_code_str = intel_bcode_str[i].str; - break; - } - } - if (brand_code_str) - debugf(2, "Detected Intel brand code: %d (%s)\n", brand.code, brand_code_str); - else - debugf(2, "Detected Intel brand code: %d\n", brand.code); - if (brand.bits) { - debugf(2, "Detected Intel bits: "); - debug_print_lbits(2, brand.bits); - } - debugf(2, "Detected Intel model code: %d\n", model_code); - - internal->code.intel = brand.code; - internal->bits = brand.bits; + data->purpose = cpuid_identify_purpose_intel(raw); + internal->score = match_cpu_codename(cpudb_intel, COUNT_OF(cpudb_intel), data); if (data->flags[CPU_FEATURE_SGX]) { debugf(2, "SGX seems to be present, decoding...\n"); @@ -1198,8 +785,6 @@ int cpuid_identify_intel(struct cpu_raw_data_t* raw, struct cpu_id_t* data, stru decode_intel_sgx_features(raw, data); } - internal->score = match_cpu_codename(cpudb_intel, COUNT_OF(cpudb_intel), data, - brand.code, brand.bits, model_code); return 0; } diff --git a/tests/amd/bobcat/brazos-zacate.test b/tests/amd/bobcat/brazos-zacate.test index ba21aed..833b5ec 100644 --- a/tests/amd/bobcat/brazos-zacate.test +++ b/tests/amd/bobcat/brazos-zacate.test @@ -102,5 +102,5 @@ general -1 -1 64 (authoritative) -Brazos Zacate (Dual-core) +E-Series (Zacate) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni monitor ssse3 cx16 syscall popcnt mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch ibs skinit wdt ts ttp tm_amd stc 100mhzsteps hwpstate constant_tsc diff --git a/tests/amd/bulldozer/bald-eagle-x4.test b/tests/amd/bulldozer/bald-eagle-x4.test index a14cda5..ee07430 100644 --- a/tests/amd/bulldozer/bald-eagle-x4.test +++ b/tests/amd/bulldozer/bald-eagle-x4.test @@ -218,5 +218,5 @@ general -1 -1 128 (authoritative) -Bald Eagle X4 +R-Series (Bald Eagle) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd 100mhzsteps hwpstate constant_tsc xop fma3 fma4 tbm f16c cpb aperfmperf bmi1 diff --git a/tests/amd/bulldozer/godavari-x4.test b/tests/amd/bulldozer/godavari-x4.test index 7269a4f..f997c4e 100644 --- a/tests/amd/bulldozer/godavari-x4.test +++ b/tests/amd/bulldozer/godavari-x4.test @@ -110,5 +110,5 @@ general -1 -1 128 (authoritative) -Godavari X4 +Athlon X4 (Godavari) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd 100mhzsteps hwpstate constant_tsc xop fma3 fma4 tbm f16c cpb aperfmperf bmi1 diff --git a/tests/amd/bulldozer/kaveri-x4.test b/tests/amd/bulldozer/kaveri-x4.test index ac21571..f9367d3 100644 --- a/tests/amd/bulldozer/kaveri-x4.test +++ b/tests/amd/bulldozer/kaveri-x4.test @@ -222,5 +222,5 @@ general -1 -1 128 (authoritative) -Kaveri X4 +Athlon X4 (Kaveri) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd 100mhzsteps hwpstate constant_tsc xop fma3 fma4 tbm f16c cpb aperfmperf bmi1 diff --git a/tests/amd/bulldozer/opteron-abu-dhabi.test b/tests/amd/bulldozer/opteron-abu-dhabi.test index 74b762b..d134dc5 100644 --- a/tests/amd/bulldozer/opteron-abu-dhabi.test +++ b/tests/amd/bulldozer/opteron-abu-dhabi.test @@ -846,5 +846,5 @@ general -1 -1 128 (authoritative) -Abu Dhabi +Opteron (Abu Dhabi) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd 100mhzsteps hwpstate constant_tsc xop fma3 fma4 tbm f16c cpb aperfmperf bmi1 diff --git a/tests/amd/bulldozer/opteron-interlagos.test b/tests/amd/bulldozer/opteron-interlagos.test index a941977..26894f6 100644 --- a/tests/amd/bulldozer/opteron-interlagos.test +++ b/tests/amd/bulldozer/opteron-interlagos.test @@ -642,5 +642,5 @@ general -1 -1 128 (authoritative) -Interlagos +Opteron (Interlagos) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd 100mhzsteps hwpstate constant_tsc xop fma4 cpb diff --git a/tests/amd/bulldozer/vishera-x4.test b/tests/amd/bulldozer/vishera-x4.test index 712c558..d239dc3 100644 --- a/tests/amd/bulldozer/vishera-x4.test +++ b/tests/amd/bulldozer/vishera-x4.test @@ -102,5 +102,5 @@ general -1 -1 128 (authoritative) -Vishera X4 +FX (Vishera) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd 100mhzsteps hwpstate constant_tsc xop fma3 fma4 tbm f16c cpb aperfmperf bmi1 diff --git a/tests/amd/bulldozer/zambezi-x3.test b/tests/amd/bulldozer/zambezi-x3.test index e797e79..c99cdd9 100644 --- a/tests/amd/bulldozer/zambezi-x3.test +++ b/tests/amd/bulldozer/zambezi-x3.test @@ -324,5 +324,5 @@ general -1 -1 128 (authoritative) -Zambezi X3 +FX (Zambezi) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd 100mhzsteps hwpstate constant_tsc xop fma4 cpb diff --git a/tests/amd/bulldozer/zambezi-x4.test b/tests/amd/bulldozer/zambezi-x4.test index 47b627a..472d46e 100644 --- a/tests/amd/bulldozer/zambezi-x4.test +++ b/tests/amd/bulldozer/zambezi-x4.test @@ -102,5 +102,5 @@ general -1 -1 128 (authoritative) -Zambezi X4 +FX (Zambezi) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd 100mhzsteps hwpstate constant_tsc xop fma4 cpb diff --git a/tests/amd/jaguar/athlon-kabini.test b/tests/amd/jaguar/athlon-kabini.test index bd4cce8..1cf1ec4 100644 --- a/tests/amd/jaguar/athlon-kabini.test +++ b/tests/amd/jaguar/athlon-kabini.test @@ -226,5 +226,5 @@ general -1 -1 128 (authoritative) -Kabini X4 +Athlon X4 (Kabini) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd 100mhzsteps hwpstate constant_tsc f16c pfi bmi1 diff --git a/tests/amd/jaguar/beema-x4.test b/tests/amd/jaguar/beema-x4.test index 7a2683d..0c2e792 100644 --- a/tests/amd/jaguar/beema-x4.test +++ b/tests/amd/jaguar/beema-x4.test @@ -222,5 +222,5 @@ general -1 -1 128 (authoritative) -Beema X4 +A-Series (Beema) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd 100mhzsteps hwpstate constant_tsc f16c rdrand cpb pa bmi1 diff --git a/tests/amd/jaguar/kabini-x4.test b/tests/amd/jaguar/kabini-x4.test index 2acd8e1..c538c09 100644 --- a/tests/amd/jaguar/kabini-x4.test +++ b/tests/amd/jaguar/kabini-x4.test @@ -222,5 +222,5 @@ general -1 -1 128 (authoritative) -Kabini X4 +A-Series (Kabini) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd 100mhzsteps hwpstate constant_tsc f16c pfi bmi1 diff --git a/tests/amd/jaguar/steppe-eagle-x2.test b/tests/amd/jaguar/steppe-eagle-x2.test index 1abd6dc..36d3850 100644 --- a/tests/amd/jaguar/steppe-eagle-x2.test +++ b/tests/amd/jaguar/steppe-eagle-x2.test @@ -128,5 +128,5 @@ general -1 -1 128 (authoritative) -Steppe Eagle X2 +G-Series (Steppe Eagle) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd 100mhzsteps hwpstate constant_tsc f16c rdrand pa bmi1 diff --git a/tests/amd/k10/magny-cours.test b/tests/amd/k10/magny-cours.test index 48ebc8f..01dc88f 100644 --- a/tests/amd/k10/magny-cours.test +++ b/tests/amd/k10/magny-cours.test @@ -102,5 +102,5 @@ general -1 -1 128 (authoritative) -Magny-Cours Opteron +Opteron (Magny-Cours) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni monitor cx16 syscall popcnt mmxext 3dnow 3dnowext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd stc 100mhzsteps hwpstate constant_tsc diff --git a/tests/amd/zen3/ryzen7-rembrandt-r.test b/tests/amd/zen3/ryzen7-rembrandt-r.test index 4055352..7280da0 100644 --- a/tests/amd/zen3/ryzen7-rembrandt-r.test +++ b/tests/amd/zen3/ryzen7-rembrandt-r.test @@ -1054,5 +1054,5 @@ general 1 0 256 (authoritative) -Ryzen 7 (Rembrandt) +Ryzen 7 (Rembrandt-R) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd hwpstate constant_tsc fma3 f16c rdrand x2apic cpb aperfmperf avx2 bmi1 bmi2 sha_ni rdseed adx diff --git a/tests/hygon/dhyana/dhyana_7.test b/tests/hygon/dhyana/dhyana.test similarity index 99% rename from tests/hygon/dhyana/dhyana_7.test rename to tests/hygon/dhyana/dhyana.test index aa70a7e..967272d 100644 --- a/tests/hygon/dhyana/dhyana_7.test +++ b/tests/hygon/dhyana/dhyana.test @@ -106,5 +106,5 @@ general -1 -1 128 (authoritative) -C86 7 (Dhyana) +C86 (Dhyana) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw skinit wdt ts ttp tm_amd hwpstate constant_tsc fma3 f16c rdrand aperfmperf avx2 bmi1 bmi2 rdseed adx diff --git a/tests/intel/ia-32/p6/yonah-core-duo-t2400.test b/tests/intel/ia-32/p6/yonah-core-duo-t2400.test index a724f6d..d7a7d47 100644 --- a/tests/intel/ia-32/p6/yonah-core-duo-t2400.test +++ b/tests/intel/ia-32/p6/yonah-core-duo-t2400.test @@ -98,5 +98,5 @@ general -1 -1 64 (non-authoritative) -Yonah (Core Duo) +Core Duo (Yonah) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni monitor vmx est tm2 xtpr pdcm xd diff --git a/tests/intel/ia-32/p6/yonah-core-duo-t2600.test b/tests/intel/ia-32/p6/yonah-core-duo-t2600.test index 82df25a..9a07559 100644 --- a/tests/intel/ia-32/p6/yonah-core-duo-t2600.test +++ b/tests/intel/ia-32/p6/yonah-core-duo-t2600.test @@ -102,5 +102,5 @@ general -1 -1 64 (non-authoritative) -Yonah (Core Duo) +Core Duo (Yonah) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni monitor vmx est tm2 xtpr pdcm xd diff --git a/tests/intel/ia-32/p6/yonah-core-solo.test b/tests/intel/ia-32/p6/yonah-core-solo.test index 4837111..70fad8c 100644 --- a/tests/intel/ia-32/p6/yonah-core-solo.test +++ b/tests/intel/ia-32/p6/yonah-core-solo.test @@ -98,5 +98,5 @@ general -1 -1 64 (non-authoritative) -Yonah (Core Duo) +Core Duo (Yonah) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni monitor vmx est tm2 xtpr pdcm xd diff --git a/tests/intel/x86-64/core/allendale-celeron.test b/tests/intel/x86-64/core/allendale-celeron.test index e71bde0..9a36955 100644 --- a/tests/intel/x86-64/core/allendale-celeron.test +++ b/tests/intel/x86-64/core/allendale-celeron.test @@ -98,5 +98,5 @@ general -1 -1 128 (non-authoritative) -Allendale (Celeron) +Celeron (Allendale) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni dts64 monitor ds_cpl est tm2 ssse3 cx16 xtpr pdcm lm lahf_lm diff --git a/tests/intel/x86-64/core/allendale-core-2-duo.test b/tests/intel/x86-64/core/allendale-core-2-duo.test index 2d1ed4e..492dd7f 100644 --- a/tests/intel/x86-64/core/allendale-core-2-duo.test +++ b/tests/intel/x86-64/core/allendale-core-2-duo.test @@ -98,5 +98,5 @@ general -1 -1 128 (non-authoritative) -Allendale (Core 2 Duo) +Core 2 Duo (Allendale) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni dts64 monitor ds_cpl est tm2 ssse3 cx16 xtpr pdcm xd lm lahf_lm diff --git a/tests/intel/x86-64/core/allendale-pentium.test b/tests/intel/x86-64/core/allendale-pentium.test index 2776d00..18e8f1b 100644 --- a/tests/intel/x86-64/core/allendale-pentium.test +++ b/tests/intel/x86-64/core/allendale-pentium.test @@ -98,5 +98,5 @@ general -1 -1 128 (non-authoritative) -Allendale (Pentium) +Pentium Dual-Core (Allendale) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni dts64 monitor ds_cpl est tm2 ssse3 cx16 xtpr pdcm xd lm lahf_lm diff --git a/tests/intel/x86-64/core/conroe-core-2-duo.test b/tests/intel/x86-64/core/conroe-core-2-duo.test index f6dc49b..b73bccb 100644 --- a/tests/intel/x86-64/core/conroe-core-2-duo.test +++ b/tests/intel/x86-64/core/conroe-core-2-duo.test @@ -98,5 +98,5 @@ general -1 -1 128 (non-authoritative) -Conroe (Core 2 Duo) +Core 2 Duo (Conroe) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm xd lm lahf_lm diff --git a/tests/intel/x86-64/core/conroe-l-celeron.test b/tests/intel/x86-64/core/conroe-l-celeron.test index 78e89ce..d8e1454 100644 --- a/tests/intel/x86-64/core/conroe-l-celeron.test +++ b/tests/intel/x86-64/core/conroe-l-celeron.test @@ -102,5 +102,5 @@ general -1 -1 128 (non-authoritative) -Conroe-L (Celeron) +Celeron (Conroe-L) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss tm pbe pni dts64 monitor ds_cpl tm2 ssse3 cx16 xtpr pdcm xd lm lahf_lm diff --git a/tests/intel/x86-64/core/kentsfield-core-2-quad.test b/tests/intel/x86-64/core/kentsfield-core-2-quad.test index 2d26e23..3878417 100644 --- a/tests/intel/x86-64/core/kentsfield-core-2-quad.test +++ b/tests/intel/x86-64/core/kentsfield-core-2-quad.test @@ -102,5 +102,5 @@ general -1 -1 128 (non-authoritative) -Kentsfield (Core 2 Quad) +Core 2 Quad (Kentsfield) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm lm lahf_lm diff --git a/tests/intel/x86-64/core/merom-core-2-duo-2m.test b/tests/intel/x86-64/core/merom-core-2-duo-2m.test index 682110e..37e3e50 100644 --- a/tests/intel/x86-64/core/merom-core-2-duo-2m.test +++ b/tests/intel/x86-64/core/merom-core-2-duo-2m.test @@ -98,5 +98,5 @@ general -1 -1 128 (non-authoritative) -Merom (Core 2 Duo) 2048K +Core 2 Duo (Merom-2M) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm xd lm lahf_lm diff --git a/tests/intel/x86-64/core/merom-core-2-duo-4m.test b/tests/intel/x86-64/core/merom-core-2-duo-4m.test index 730afb9..9a42576 100644 --- a/tests/intel/x86-64/core/merom-core-2-duo-4m.test +++ b/tests/intel/x86-64/core/merom-core-2-duo-4m.test @@ -98,5 +98,5 @@ general -1 -1 128 (non-authoritative) -Merom (Core 2 Duo) 4096K +Core 2 Duo (Merom) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm xd lm lahf_lm diff --git a/tests/intel/x86-64/core/penryn-core-2-duo-3m.test b/tests/intel/x86-64/core/penryn-core-2-duo-3m.test index 0634b31..34c1a12 100644 --- a/tests/intel/x86-64/core/penryn-core-2-duo-3m.test +++ b/tests/intel/x86-64/core/penryn-core-2-duo-3m.test @@ -98,5 +98,5 @@ general -1 -1 128 (non-authoritative) -Penryn (Core 2 Duo) 3M +Core 2 Duo (Penryn-3M) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 xd lm lahf_lm diff --git a/tests/intel/x86-64/core/penryn-l-celeron.test b/tests/intel/x86-64/core/penryn-l-celeron.test index 056bda7..8b5bcab 100644 --- a/tests/intel/x86-64/core/penryn-l-celeron.test +++ b/tests/intel/x86-64/core/penryn-l-celeron.test @@ -111,5 +111,5 @@ general -1 -1 128 (non-authoritative) -Celeron Penryn L +Celeron (Penryn-L) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss tm pbe pni dts64 monitor ds_cpl tm2 ssse3 cx16 xtpr pdcm syscall xd xsave osxsave lm lahf_lm diff --git a/tests/intel/x86-64/core/penryn-pentium-m.test b/tests/intel/x86-64/core/penryn-pentium-m.test index 3a2f4ef..18fb86e 100644 --- a/tests/intel/x86-64/core/penryn-pentium-m.test +++ b/tests/intel/x86-64/core/penryn-pentium-m.test @@ -102,5 +102,5 @@ general -1 -1 128 (non-authoritative) -Penryn (Core 2 Duo) +Pentium Dual-Core (Penryn-L) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni dts64 monitor ds_cpl est tm2 ssse3 cx16 xtpr pdcm syscall xd xsave osxsave lm lahf_lm diff --git a/tests/intel/x86-64/core/wolfdale-celeron.test b/tests/intel/x86-64/core/wolfdale-celeron.test index 62ca00a..01703c9 100644 --- a/tests/intel/x86-64/core/wolfdale-celeron.test +++ b/tests/intel/x86-64/core/wolfdale-celeron.test @@ -102,5 +102,5 @@ general -1 -1 128 (non-authoritative) -Celeron Wolfdale 1M +Celeron (Wolfdale-3M) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm xd xsave osxsave lm lahf_lm diff --git a/tests/intel/x86-64/core/wolfdale-pentium.test b/tests/intel/x86-64/core/wolfdale-pentium.test index a8d4296..0d5f29b 100644 --- a/tests/intel/x86-64/core/wolfdale-pentium.test +++ b/tests/intel/x86-64/core/wolfdale-pentium.test @@ -98,5 +98,5 @@ general -1 -1 128 (non-authoritative) -Wolfdale (Core 2 Duo) 2M +Pentium (Wolfdale-3M) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni dts64 monitor ds_cpl est tm2 ssse3 cx16 xtpr pdcm xd lm lahf_lm diff --git a/tests/intel/x86-64/core/yorkfield-core-2-quad-2m.test b/tests/intel/x86-64/core/yorkfield-core-2-quad-2m.test index dd8e3f8..53e1448 100644 --- a/tests/intel/x86-64/core/yorkfield-core-2-quad-2m.test +++ b/tests/intel/x86-64/core/yorkfield-core-2-quad-2m.test @@ -102,5 +102,5 @@ general -1 -1 128 (non-authoritative) -Yorkfield (Core 2 Quad) 2M +Core 2 Quad (Yorkfield-6M) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 xd xsave osxsave lm lahf_lm diff --git a/tests/intel/x86-64/core/yorkfield-core-2-quad-6m.test b/tests/intel/x86-64/core/yorkfield-core-2-quad-6m.test index f1af9b6..8e22317 100644 --- a/tests/intel/x86-64/core/yorkfield-core-2-quad-6m.test +++ b/tests/intel/x86-64/core/yorkfield-core-2-quad-6m.test @@ -98,5 +98,5 @@ general -1 -1 128 (non-authoritative) -Yorkfield (Core 2 Quad) 6M +Core 2 Quad (Yorkfield) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 xd lm lahf_lm diff --git a/tests/intel/x86-64/cypress-cove/rocket-lake-core-i7.test b/tests/intel/x86-64/cypress-cove/rocket-lake-core-i7.test index 0fd5f8e..edc5fb1 100644 --- a/tests/intel/x86-64/cypress-cove/rocket-lake-core-i7.test +++ b/tests/intel/x86-64/cypress-cove/rocket-lake-core-i7.test @@ -1038,5 +1038,5 @@ general 1 0 128 (non-authoritative) -Rocket Lake (Core i7) +Core i7 (Rocket Lake-S) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 avx512f avx512dq avx512cd sha_ni avx512bw avx512vl rdseed adx avx512vnni avx512vbmi avx512vbmi2 diff --git a/tests/intel/x86-64/cypress-cove/rocket-lake-xeon-e.test b/tests/intel/x86-64/cypress-cove/rocket-lake-xeon-e.test index e8b9d24..0471cef 100644 --- a/tests/intel/x86-64/cypress-cove/rocket-lake-xeon-e.test +++ b/tests/intel/x86-64/cypress-cove/rocket-lake-xeon-e.test @@ -810,5 +810,5 @@ general 1 0 128 (non-authoritative) -Rocket Lake (Xeon-E) +Xeon E (Rocket Lake) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 avx512f avx512dq avx512cd sha_ni avx512bw avx512vl sgx rdseed adx avx512vnni avx512vbmi avx512vbmi2 diff --git a/tests/intel/x86-64/golden-cove/alder-lake-h-core-i7.test b/tests/intel/x86-64/golden-cove/alder-lake-h-core-i7.test index 36b624b..50e3f21 100644 --- a/tests/intel/x86-64/golden-cove/alder-lake-h-core-i7.test +++ b/tests/intel/x86-64/golden-cove/alder-lake-h-core-i7.test @@ -1378,7 +1378,7 @@ performance 1 0 128 (non-authoritative) -Alder Lake-H (Core i7) +Core i7 (Alder Lake-H) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx -------------------------------------------------------------------------------- x86 @@ -1412,5 +1412,5 @@ efficiency 1 0 128 (non-authoritative) -Alder Lake-H (Core i7) +Core i7 (Alder Lake-H) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx diff --git a/tests/intel/x86-64/golden-cove/alder-lake-h-core-i9.test b/tests/intel/x86-64/golden-cove/alder-lake-h-core-i9.test index cf27fb5..805abe8 100644 --- a/tests/intel/x86-64/golden-cove/alder-lake-h-core-i9.test +++ b/tests/intel/x86-64/golden-cove/alder-lake-h-core-i9.test @@ -1378,7 +1378,7 @@ performance 1 0 128 (non-authoritative) -Alder Lake-H (Core i9) +Core i9 (Alder Lake-H) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx -------------------------------------------------------------------------------- x86 @@ -1412,5 +1412,5 @@ efficiency 1 0 128 (non-authoritative) -Alder Lake-H (Core i9) +Core i9 (Alder Lake-H) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx diff --git a/tests/intel/x86-64/golden-cove/alder-lake-hx-core-i7.test b/tests/intel/x86-64/golden-cove/alder-lake-hx-core-i7.test index 06e7b49..5c0cd7b 100644 --- a/tests/intel/x86-64/golden-cove/alder-lake-hx-core-i7.test +++ b/tests/intel/x86-64/golden-cove/alder-lake-hx-core-i7.test @@ -1678,7 +1678,7 @@ performance 1 0 128 (non-authoritative) -Alder Lake-HX (Core i7) +Core i7 (Alder Lake-HX) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx -------------------------------------------------------------------------------- x86 @@ -1712,5 +1712,5 @@ efficiency 1 0 128 (non-authoritative) -Alder Lake-HX (Core i7) +Core i7 (Alder Lake-HX) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx diff --git a/tests/intel/x86-64/golden-cove/alder-lake-p-core-i3.test b/tests/intel/x86-64/golden-cove/alder-lake-p-core-i3.test index 1a61ecb..1b707ce 100644 --- a/tests/intel/x86-64/golden-cove/alder-lake-p-core-i3.test +++ b/tests/intel/x86-64/golden-cove/alder-lake-p-core-i3.test @@ -826,7 +826,7 @@ performance 1 0 128 (non-authoritative) -Alder Lake-P (Core i3) +Core i3 (Alder Lake-P) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx -------------------------------------------------------------------------------- x86 @@ -860,5 +860,5 @@ efficiency 1 0 128 (non-authoritative) -Alder Lake-P (Core i3) +Core i3 (Alder Lake-P) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx diff --git a/tests/intel/x86-64/golden-cove/alder-lake-s-core-i5.test b/tests/intel/x86-64/golden-cove/alder-lake-s-core-i5.test index 190f50f..14c4e28 100644 --- a/tests/intel/x86-64/golden-cove/alder-lake-s-core-i5.test +++ b/tests/intel/x86-64/golden-cove/alder-lake-s-core-i5.test @@ -894,5 +894,5 @@ general 1 0 128 (non-authoritative) -Alder Lake-S (Core i5) +Core i5 (Alder Lake-S) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 avx512f avx512dq avx512cd sha_ni avx512bw avx512vl rdseed adx avx512vnni avx512vbmi avx512vbmi2 diff --git a/tests/intel/x86-64/golden-cove/alder-lake-s-core-i9.test b/tests/intel/x86-64/golden-cove/alder-lake-s-core-i9.test index e6b8e8d..2420c7e 100644 --- a/tests/intel/x86-64/golden-cove/alder-lake-s-core-i9.test +++ b/tests/intel/x86-64/golden-cove/alder-lake-s-core-i9.test @@ -1654,7 +1654,7 @@ performance 1 0 128 (non-authoritative) -Alder Lake-S (Core i9) +Core i9 (Alder Lake-S) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx -------------------------------------------------------------------------------- x86 @@ -1688,5 +1688,5 @@ efficiency 1 0 128 (non-authoritative) -Alder Lake-S (Core i9) +Core i9 (Alder Lake-S) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx diff --git a/tests/intel/x86-64/golden-cove/alder-lake-s-pentium.test b/tests/intel/x86-64/golden-cove/alder-lake-s-pentium.test index 605436d..3daf1d4 100644 --- a/tests/intel/x86-64/golden-cove/alder-lake-s-pentium.test +++ b/tests/intel/x86-64/golden-cove/alder-lake-s-pentium.test @@ -310,5 +310,5 @@ general 1 0 128 (non-authoritative) -Alder Lake-S (Pentium) +Pentium Gold (Alder Lake-S) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx diff --git a/tests/intel/x86-64/golden-cove/alder-lake-u-pentium.test b/tests/intel/x86-64/golden-cove/alder-lake-u-pentium.test index f01261c..8b6cf2f 100644 --- a/tests/intel/x86-64/golden-cove/alder-lake-u-pentium.test +++ b/tests/intel/x86-64/golden-cove/alder-lake-u-pentium.test @@ -434,7 +434,7 @@ performance 1 0 128 (non-authoritative) -Alder Lake-U (Pentium) +Pentium Gold (Alder Lake-U) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx -------------------------------------------------------------------------------- x86 @@ -468,5 +468,5 @@ efficiency 1 0 128 (non-authoritative) -Alder Lake-U (Pentium) +Pentium Gold (Alder Lake-U) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx diff --git a/tests/intel/x86-64/golden-cove/raptor-lake-s-core-i5.test b/tests/intel/x86-64/golden-cove/raptor-lake-s-core-i5.test index bf27bd5..9dd9f79 100644 --- a/tests/intel/x86-64/golden-cove/raptor-lake-s-core-i5.test +++ b/tests/intel/x86-64/golden-cove/raptor-lake-s-core-i5.test @@ -1398,7 +1398,7 @@ performance 1 0 128 (non-authoritative) -Raptor Lake-S (Core i5) +Core i5 (Raptor Lake-S) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx -------------------------------------------------------------------------------- x86 @@ -1432,5 +1432,5 @@ efficiency 1 0 128 (non-authoritative) -Raptor Lake-S (Core i5) +Core i5 (Raptor Lake-S) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx diff --git a/tests/intel/x86-64/golden-cove/sapphire-rapids-ws-xeon-w7.test b/tests/intel/x86-64/golden-cove/sapphire-rapids-ws-xeon-w7.test index 7b298b7..4b6a826 100644 --- a/tests/intel/x86-64/golden-cove/sapphire-rapids-ws-xeon-w7.test +++ b/tests/intel/x86-64/golden-cove/sapphire-rapids-ws-xeon-w7.test @@ -3110,5 +3110,5 @@ general 1 0 128 (non-authoritative) -Sapphire Rapids-WS (Xeon w7) +Xeon w7 (Sapphire Rapids-WS) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm dca sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 hle rtm avx512f avx512dq avx512cd sha_ni avx512bw avx512vl rdseed adx avx512vnni avx512vbmi avx512vbmi2 diff --git a/tests/intel/x86-64/golden-cove/sapphire-rapids-ws-xeon-w9.test b/tests/intel/x86-64/golden-cove/sapphire-rapids-ws-xeon-w9.test index 75b0b82..be750b2 100644 --- a/tests/intel/x86-64/golden-cove/sapphire-rapids-ws-xeon-w9.test +++ b/tests/intel/x86-64/golden-cove/sapphire-rapids-ws-xeon-w9.test @@ -5574,5 +5574,5 @@ general 1 0 128 (non-authoritative) -Sapphire Rapids-WS (Xeon w9) +Xeon w9 (Sapphire Rapids-WS) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm dca sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 hle rtm avx512f avx512dq avx512cd sha_ni avx512bw avx512vl rdseed adx avx512vnni avx512vbmi avx512vbmi2 diff --git a/tests/intel/x86-64/haswell/broadwell-e-core-i7.test b/tests/intel/x86-64/haswell/broadwell-e-core-i7.test index 62bdd63..1fa3a66 100644 --- a/tests/intel/x86-64/haswell/broadwell-e-core-i7.test +++ b/tests/intel/x86-64/haswell/broadwell-e-core-i7.test @@ -106,5 +106,5 @@ general -1 -1 128 (non-authoritative) -Broadwell-E (Core i7) +Core i7 (Broadwell-E) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm dca sse4_1 sse4_2 syscall xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 hle rtm rdseed adx diff --git a/tests/intel/x86-64/haswell/crystal-well-core-i7.test b/tests/intel/x86-64/haswell/crystal-well-core-i7.test index 1f543eb..ad45e44 100644 --- a/tests/intel/x86-64/haswell/crystal-well-core-i7.test +++ b/tests/intel/x86-64/haswell/crystal-well-core-i7.test @@ -106,5 +106,5 @@ general -1 -1 128 (non-authoritative) -Haswell (Core i7) +Core i7 (Haswell) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 syscall xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 diff --git a/tests/intel/x86-64/haswell/haswell-core-i3.test b/tests/intel/x86-64/haswell/haswell-core-i3.test index f4db715..4f05266 100644 --- a/tests/intel/x86-64/haswell/haswell-core-i3.test +++ b/tests/intel/x86-64/haswell/haswell-core-i3.test @@ -102,5 +102,5 @@ general -1 -1 128 (non-authoritative) -Haswell (Core i3) +Core i3 (Haswell) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 syscall xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand avx2 bmi1 bmi2 diff --git a/tests/intel/x86-64/haswell/haswell-core-i5.test b/tests/intel/x86-64/haswell/haswell-core-i5.test index b11465d..3cf2d3d 100644 --- a/tests/intel/x86-64/haswell/haswell-core-i5.test +++ b/tests/intel/x86-64/haswell/haswell-core-i5.test @@ -102,5 +102,5 @@ general -1 -1 128 (non-authoritative) -Haswell (Core i5) +Core i5 (Haswell) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 syscall xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 diff --git a/tests/intel/x86-64/haswell/haswell-core-i7.test b/tests/intel/x86-64/haswell/haswell-core-i7.test index e140ba1..4dc506e 100644 --- a/tests/intel/x86-64/haswell/haswell-core-i7.test +++ b/tests/intel/x86-64/haswell/haswell-core-i7.test @@ -102,5 +102,5 @@ general -1 -1 128 (non-authoritative) -Haswell (Core i7) +Core i7 (Haswell) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand avx2 bmi1 bmi2 diff --git a/tests/intel/x86-64/lion-cove/arrow-lake-s-core-ultra-5.test b/tests/intel/x86-64/lion-cove/arrow-lake-s-core-ultra-5.test index 8a8a783..d625229 100644 --- a/tests/intel/x86-64/lion-cove/arrow-lake-s-core-ultra-5.test +++ b/tests/intel/x86-64/lion-cove/arrow-lake-s-core-ultra-5.test @@ -1206,7 +1206,7 @@ performance 1 0 128 (non-authoritative) -Arrow Lake-S (Core Ultra 5) +Core Ultra 5 (Arrow Lake-S) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx -------------------------------------------------------------------------------- x86 @@ -1240,5 +1240,5 @@ efficiency 1 0 128 (non-authoritative) -Arrow Lake-S (Core Ultra 5) +Core Ultra 5 (Arrow Lake-S) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx diff --git a/tests/intel/x86-64/lion-cove/arrow-lake-s-core-ultra-7.test b/tests/intel/x86-64/lion-cove/arrow-lake-s-core-ultra-7.test index f365bf4..c6cdbdb 100644 --- a/tests/intel/x86-64/lion-cove/arrow-lake-s-core-ultra-7.test +++ b/tests/intel/x86-64/lion-cove/arrow-lake-s-core-ultra-7.test @@ -1730,7 +1730,7 @@ performance 1 0 128 (non-authoritative) -Arrow Lake-S (Core Ultra 7) +Core Ultra 7 (Arrow Lake-S) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx -------------------------------------------------------------------------------- x86 @@ -1764,5 +1764,5 @@ efficiency 1 0 128 (non-authoritative) -Arrow Lake-S (Core Ultra 7) +Core Ultra 7 (Arrow Lake-S) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx diff --git a/tests/intel/x86-64/lion-cove/lunar-lake-v-core-ultra-9.test b/tests/intel/x86-64/lion-cove/lunar-lake-v-core-ultra-9.test index 1d4b2dd..a7a9088 100644 --- a/tests/intel/x86-64/lion-cove/lunar-lake-v-core-ultra-9.test +++ b/tests/intel/x86-64/lion-cove/lunar-lake-v-core-ultra-9.test @@ -714,7 +714,7 @@ performance 1 0 128 (non-authoritative) -Lunar Lake-V (Core Ultra 9) +Core Ultra 9 (Lunar Lake-V) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx -------------------------------------------------------------------------------- x86 @@ -748,5 +748,5 @@ low-power efficiency 0 0 128 (non-authoritative) -Lunar Lake-V (Core Ultra 9) +Core Ultra 9 (Lunar Lake-V) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx diff --git a/tests/intel/x86-64/nehalem/arrandale-core-i5.test b/tests/intel/x86-64/nehalem/arrandale-core-i5.test index 28222b6..e115cf6 100644 --- a/tests/intel/x86-64/nehalem/arrandale-core-i5.test +++ b/tests/intel/x86-64/nehalem/arrandale-core-i5.test @@ -106,5 +106,5 @@ general -1 -1 128 (non-authoritative) -Arrandale (Core i5) +Core i5 (Arrandale) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 syscall xd popcnt aes rdtscp lm lahf_lm constant_tsc diff --git a/tests/intel/x86-64/nehalem/arrandale-core-i7.test b/tests/intel/x86-64/nehalem/arrandale-core-i7.test index ef502c6..f1768a0 100644 --- a/tests/intel/x86-64/nehalem/arrandale-core-i7.test +++ b/tests/intel/x86-64/nehalem/arrandale-core-i7.test @@ -102,5 +102,5 @@ general -1 -1 128 (non-authoritative) -Arrandale (Core i7) +Core i7 (Arrandale) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd popcnt aes rdtscp lm lahf_lm constant_tsc diff --git a/tests/intel/x86-64/nehalem/arrandale-pentium.test b/tests/intel/x86-64/nehalem/arrandale-pentium.test index 0f97a73..c7c1792 100644 --- a/tests/intel/x86-64/nehalem/arrandale-pentium.test +++ b/tests/intel/x86-64/nehalem/arrandale-pentium.test @@ -102,5 +102,5 @@ general -1 -1 128 (non-authoritative) -Arrandale (Pentium) +Pentium (Arrandale) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni dts64 monitor ds_cpl est tm2 ssse3 cx16 xtpr pdcm xd popcnt rdtscp lm lahf_lm constant_tsc diff --git a/tests/intel/x86-64/nehalem/bloomfield-core-i7.test b/tests/intel/x86-64/nehalem/bloomfield-core-i7.test index b4f9287..e3cdb73 100644 --- a/tests/intel/x86-64/nehalem/bloomfield-core-i7.test +++ b/tests/intel/x86-64/nehalem/bloomfield-core-i7.test @@ -102,5 +102,5 @@ general -1 -1 128 (non-authoritative) -Bloomfield (Core i7) +Core i7 (Bloomfield) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd popcnt rdtscp lm lahf_lm constant_tsc diff --git a/tests/intel/x86-64/nehalem/bloomfield-xeon.test b/tests/intel/x86-64/nehalem/bloomfield-xeon.test index 87f0313..d102286 100644 --- a/tests/intel/x86-64/nehalem/bloomfield-xeon.test +++ b/tests/intel/x86-64/nehalem/bloomfield-xeon.test @@ -102,5 +102,5 @@ general -1 -1 128 (non-authoritative) -Bloomfield (Xeon) +Xeon (Bloomfield) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm dca sse4_1 sse4_2 xd popcnt rdtscp lm lahf_lm constant_tsc diff --git a/tests/intel/x86-64/nehalem/gainestown-xeon.test b/tests/intel/x86-64/nehalem/gainestown-xeon.test index 431fc51..5957fb3 100644 --- a/tests/intel/x86-64/nehalem/gainestown-xeon.test +++ b/tests/intel/x86-64/nehalem/gainestown-xeon.test @@ -102,5 +102,5 @@ general -1 -1 128 (non-authoritative) -Gainestown 8M (Xeon) +Xeon (Gainestown) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm dca sse4_1 sse4_2 xd popcnt rdtscp lm lahf_lm constant_tsc diff --git a/tests/intel/x86-64/nehalem/gulftown-core-i7.test b/tests/intel/x86-64/nehalem/gulftown-core-i7.test index 3acfb79..62a1984 100644 --- a/tests/intel/x86-64/nehalem/gulftown-core-i7.test +++ b/tests/intel/x86-64/nehalem/gulftown-core-i7.test @@ -102,5 +102,5 @@ general -1 -1 128 (non-authoritative) -Gulftown (Core i7) +Core i7 Extreme (Gulftown) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd popcnt aes rdtscp lm lahf_lm constant_tsc diff --git a/tests/intel/x86-64/nehalem/lynnfield-core-i5.test b/tests/intel/x86-64/nehalem/lynnfield-core-i5.test index 0386df3..ab765b9 100644 --- a/tests/intel/x86-64/nehalem/lynnfield-core-i5.test +++ b/tests/intel/x86-64/nehalem/lynnfield-core-i5.test @@ -354,5 +354,5 @@ general 1 0 128 (non-authoritative) -Lynnfield (Core i5) +Core i5 (Lynnfield) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 syscall xd popcnt rdtscp lm lahf_lm constant_tsc diff --git a/tests/intel/x86-64/nehalem/lynnfield-core-i7.test b/tests/intel/x86-64/nehalem/lynnfield-core-i7.test index 2460cce..8a0658e 100644 --- a/tests/intel/x86-64/nehalem/lynnfield-core-i7.test +++ b/tests/intel/x86-64/nehalem/lynnfield-core-i7.test @@ -102,5 +102,5 @@ general -1 -1 128 (non-authoritative) -Lynnfield (Core i7) +Core i7 (Lynnfield) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd popcnt rdtscp lm lahf_lm constant_tsc diff --git a/tests/intel/x86-64/nehalem/gulftown-xeon.test b/tests/intel/x86-64/nehalem/westmere-ep-xeon.test similarity index 99% rename from tests/intel/x86-64/nehalem/gulftown-xeon.test rename to tests/intel/x86-64/nehalem/westmere-ep-xeon.test index 4709412..4d6ca98 100644 --- a/tests/intel/x86-64/nehalem/gulftown-xeon.test +++ b/tests/intel/x86-64/nehalem/westmere-ep-xeon.test @@ -102,5 +102,5 @@ general -1 -1 128 (non-authoritative) -Gulftown (Xeon) +Xeon (Westmere-EP) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm dca sse4_1 sse4_2 xd popcnt aes rdtscp lm lahf_lm constant_tsc diff --git a/tests/intel/x86-64/raptor-cove/emerald-rapids-sp-xeon-platinum.test b/tests/intel/x86-64/raptor-cove/emerald-rapids-sp-xeon-platinum.test index 5a54f92..4d849fd 100644 --- a/tests/intel/x86-64/raptor-cove/emerald-rapids-sp-xeon-platinum.test +++ b/tests/intel/x86-64/raptor-cove/emerald-rapids-sp-xeon-platinum.test @@ -4342,5 +4342,5 @@ general 1 0 128 (non-authoritative) -Emerald Rapids-SP (Xeon Platinum) +Xeon Platinum (Emerald Rapids-SP) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm dca sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 hle rtm avx512f avx512dq avx512cd sha_ni avx512bw avx512vl sgx rdseed adx avx512vnni avx512vbmi avx512vbmi2 diff --git a/tests/intel/x86-64/raptor-cove/raptor-lake-h-core-i9.test b/tests/intel/x86-64/raptor-cove/raptor-lake-h-core-i9.test index 6c20740..14b57f7 100644 --- a/tests/intel/x86-64/raptor-cove/raptor-lake-h-core-i9.test +++ b/tests/intel/x86-64/raptor-cove/raptor-lake-h-core-i9.test @@ -1398,7 +1398,7 @@ performance 1 0 128 (non-authoritative) -Raptor Lake-H (Core i9) +Core i9 (Raptor Lake-H) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx -------------------------------------------------------------------------------- x86 @@ -1432,5 +1432,5 @@ efficiency 1 0 128 (non-authoritative) -Raptor Lake-H (Core i9) +Core i9 (Raptor Lake-H) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx diff --git a/tests/intel/x86-64/raptor-cove/raptor-lake-p-core-i7.test b/tests/intel/x86-64/raptor-cove/raptor-lake-p-core-i7.test index fe8f42b..b9eae41 100644 --- a/tests/intel/x86-64/raptor-cove/raptor-lake-p-core-i7.test +++ b/tests/intel/x86-64/raptor-cove/raptor-lake-p-core-i7.test @@ -1398,7 +1398,7 @@ performance 1 0 128 (non-authoritative) -Raptor Lake-P (Core i7) +Core i7 (Raptor Lake-P) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx -------------------------------------------------------------------------------- x86 @@ -1432,5 +1432,5 @@ efficiency 1 0 128 (non-authoritative) -Raptor Lake-P (Core i7) +Core i7 (Raptor Lake-P) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx diff --git a/tests/intel/x86-64/raptor-cove/raptor-lake-s-core-i5.test b/tests/intel/x86-64/raptor-cove/raptor-lake-s-core-i5.test index 5f5d8c6..67ae56b 100644 --- a/tests/intel/x86-64/raptor-cove/raptor-lake-s-core-i5.test +++ b/tests/intel/x86-64/raptor-cove/raptor-lake-s-core-i5.test @@ -1398,7 +1398,7 @@ performance 1 0 128 (non-authoritative) -Raptor Lake-S (Core i5) +Core i5 (Raptor Lake-S) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx -------------------------------------------------------------------------------- x86 @@ -1432,5 +1432,5 @@ efficiency 1 0 128 (non-authoritative) -Raptor Lake-S (Core i5) +Core i5 (Raptor Lake-S) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx diff --git a/tests/intel/x86-64/raptor-cove/raptor-lake-s-core-i7.test b/tests/intel/x86-64/raptor-cove/raptor-lake-s-core-i7.test index ed55e00..e2ccf6b 100644 --- a/tests/intel/x86-64/raptor-cove/raptor-lake-s-core-i7.test +++ b/tests/intel/x86-64/raptor-cove/raptor-lake-s-core-i7.test @@ -1678,7 +1678,7 @@ performance 1 0 128 (non-authoritative) -Raptor Lake-S (Core i7) +Core i7 (Raptor Lake-S) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx -------------------------------------------------------------------------------- x86 @@ -1712,5 +1712,5 @@ efficiency 1 0 128 (non-authoritative) -Raptor Lake-S (Core i7) +Core i7 (Raptor Lake-S) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx diff --git a/tests/intel/x86-64/raptor-cove/raptor-lake-s-core-i9.test b/tests/intel/x86-64/raptor-cove/raptor-lake-s-core-i9.test index 0fe8ddb..35af430 100644 --- a/tests/intel/x86-64/raptor-cove/raptor-lake-s-core-i9.test +++ b/tests/intel/x86-64/raptor-cove/raptor-lake-s-core-i9.test @@ -2206,7 +2206,7 @@ performance 1 0 128 (non-authoritative) -Raptor Lake-S (Core i9) +Core i9 (Raptor Lake-S) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx -------------------------------------------------------------------------------- x86 @@ -2240,5 +2240,5 @@ efficiency 1 0 128 (non-authoritative) -Raptor Lake-S (Core i9) +Core i9 (Raptor Lake-S) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx diff --git a/tests/intel/x86-64/raptor-cove/raptor-lake-s-refresh-core-i5.test b/tests/intel/x86-64/raptor-cove/raptor-lake-s-refresh-core-i5.test index 5e79ae1..1653bd0 100644 --- a/tests/intel/x86-64/raptor-cove/raptor-lake-s-refresh-core-i5.test +++ b/tests/intel/x86-64/raptor-cove/raptor-lake-s-refresh-core-i5.test @@ -1398,7 +1398,7 @@ performance 1 0 128 (non-authoritative) -Raptor Lake-S (Core i5) +Core i5 (Raptor Lake-S) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx -------------------------------------------------------------------------------- x86 @@ -1432,5 +1432,5 @@ efficiency 1 0 128 (non-authoritative) -Raptor Lake-S (Core i5) +Core i5 (Raptor Lake-S) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx diff --git a/tests/intel/x86-64/raptor-cove/raptor-lake-s-refresh-core-i7.test b/tests/intel/x86-64/raptor-cove/raptor-lake-s-refresh-core-i7.test index 07a48ec..ef03de4 100644 --- a/tests/intel/x86-64/raptor-cove/raptor-lake-s-refresh-core-i7.test +++ b/tests/intel/x86-64/raptor-cove/raptor-lake-s-refresh-core-i7.test @@ -1942,7 +1942,7 @@ performance 1 0 128 (non-authoritative) -Raptor Lake-S (Core i7) +Core i7 (Raptor Lake-S) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx -------------------------------------------------------------------------------- x86 @@ -1976,5 +1976,5 @@ efficiency 1 0 128 (non-authoritative) -Raptor Lake-S (Core i7) +Core i7 (Raptor Lake-S) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx diff --git a/tests/intel/x86-64/raptor-cove/raptor-lake-s-refresh-core-i9.test b/tests/intel/x86-64/raptor-cove/raptor-lake-s-refresh-core-i9.test index 1a03e93..d2a7015 100644 --- a/tests/intel/x86-64/raptor-cove/raptor-lake-s-refresh-core-i9.test +++ b/tests/intel/x86-64/raptor-cove/raptor-lake-s-refresh-core-i9.test @@ -2206,7 +2206,7 @@ performance 1 0 128 (non-authoritative) -Raptor Lake-S (Core i9) +Core i9 (Raptor Lake-S) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx -------------------------------------------------------------------------------- x86 @@ -2240,5 +2240,5 @@ efficiency 1 0 128 (non-authoritative) -Raptor Lake-S (Core i9) +Core i9 (Raptor Lake-S) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx diff --git a/tests/intel/x86-64/raptor-cove/raptor-lake-u-core-i7.test b/tests/intel/x86-64/raptor-cove/raptor-lake-u-core-i7.test index 15e40e3..333e5c4 100644 --- a/tests/intel/x86-64/raptor-cove/raptor-lake-u-core-i7.test +++ b/tests/intel/x86-64/raptor-cove/raptor-lake-u-core-i7.test @@ -310,5 +310,5 @@ performance 1 0 128 (non-authoritative) -Raptor Lake-U (Core i7) +Core i7 (Raptor Lake-U) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx diff --git a/tests/intel/x86-64/redwood-cove/meteor-lake-h-core-ultra-5.test b/tests/intel/x86-64/redwood-cove/meteor-lake-h-core-ultra-5.test index 7004bcb..cb1ab2f 100644 --- a/tests/intel/x86-64/redwood-cove/meteor-lake-h-core-ultra-5.test +++ b/tests/intel/x86-64/redwood-cove/meteor-lake-h-core-ultra-5.test @@ -1500,7 +1500,7 @@ performance 1 0 128 (non-authoritative) -Meteor Lake-H (Core Ultra 5) +Core Ultra 5 (Meteor Lake-H) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx -------------------------------------------------------------------------------- x86 @@ -1534,7 +1534,7 @@ efficiency 1 0 128 (non-authoritative) -Meteor Lake-H (Core Ultra 5) +Core Ultra 5 (Meteor Lake-H) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx -------------------------------------------------------------------------------- x86 @@ -1568,5 +1568,5 @@ low-power efficiency 0 0 128 (non-authoritative) -Meteor Lake-H (Core Ultra 5) +Core Ultra 5 (Meteor Lake-H) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx diff --git a/tests/intel/x86-64/redwood-cove/meteor-lake-h-core-ultra-7.test b/tests/intel/x86-64/redwood-cove/meteor-lake-h-core-ultra-7.test index 964247b..947c9cf 100644 --- a/tests/intel/x86-64/redwood-cove/meteor-lake-h-core-ultra-7.test +++ b/tests/intel/x86-64/redwood-cove/meteor-lake-h-core-ultra-7.test @@ -1836,7 +1836,7 @@ performance 1 0 128 (non-authoritative) -Meteor Lake-H (Core Ultra 7) +Core Ultra 7 (Meteor Lake-H) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx -------------------------------------------------------------------------------- x86 @@ -1870,7 +1870,7 @@ efficiency 1 0 128 (non-authoritative) -Meteor Lake-H (Core Ultra 7) +Core Ultra 7 (Meteor Lake-H) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx -------------------------------------------------------------------------------- x86 @@ -1904,5 +1904,5 @@ low-power efficiency 0 0 128 (non-authoritative) -Meteor Lake-H (Core Ultra 7) +Core Ultra 7 (Meteor Lake-H) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx diff --git a/tests/intel/x86-64/sandy-bridge/ivy-bridge-core-i3.test b/tests/intel/x86-64/sandy-bridge/ivy-bridge-core-i3.test index 3e0a362..5661430 100644 --- a/tests/intel/x86-64/sandy-bridge/ivy-bridge-core-i3.test +++ b/tests/intel/x86-64/sandy-bridge/ivy-bridge-core-i3.test @@ -106,5 +106,5 @@ general -1 -1 128 (non-authoritative) -Ivy Bridge (Core i3) +Core i3 (Ivy Bridge) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 syscall xd popcnt xsave osxsave avx rdtscp lm lahf_lm constant_tsc f16c diff --git a/tests/intel/x86-64/sandy-bridge/ivy-bridge-core-i5.test b/tests/intel/x86-64/sandy-bridge/ivy-bridge-core-i5.test index 19b0e0c..58ba55f 100644 --- a/tests/intel/x86-64/sandy-bridge/ivy-bridge-core-i5.test +++ b/tests/intel/x86-64/sandy-bridge/ivy-bridge-core-i5.test @@ -102,5 +102,5 @@ general -1 -1 128 (non-authoritative) -Ivy Bridge (Core i5) +Core i5 (Ivy Bridge) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd popcnt aes xsave osxsave avx rdtscp lm lahf_lm constant_tsc f16c rdrand diff --git a/tests/intel/x86-64/sandy-bridge/ivy-bridge-xeon-e5.test b/tests/intel/x86-64/sandy-bridge/ivy-bridge-xeon-e5.test index c70c123..11fad4e 100644 --- a/tests/intel/x86-64/sandy-bridge/ivy-bridge-xeon-e5.test +++ b/tests/intel/x86-64/sandy-bridge/ivy-bridge-xeon-e5.test @@ -102,5 +102,5 @@ general -1 -1 128 (non-authoritative) -Ivy Bridge-E (Xeon) +Xeon E5 (Ivy Bridge-E) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm dca sse4_1 sse4_2 xd popcnt aes xsave osxsave avx rdtscp lm lahf_lm constant_tsc f16c rdrand x2apic diff --git a/tests/intel/x86-64/sandy-bridge/sandy-bridge-celeron.test b/tests/intel/x86-64/sandy-bridge/sandy-bridge-celeron.test index 1c949e2..9431d9a 100644 --- a/tests/intel/x86-64/sandy-bridge/sandy-bridge-celeron.test +++ b/tests/intel/x86-64/sandy-bridge/sandy-bridge-celeron.test @@ -102,5 +102,5 @@ general -1 -1 128 (non-authoritative) -Sandy Bridge (Celeron) +Celeron (Sandy Bridge) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd popcnt xsave rdtscp lm lahf_lm constant_tsc diff --git a/tests/intel/x86-64/sandy-bridge/sandy-bridge-core-i7.test b/tests/intel/x86-64/sandy-bridge/sandy-bridge-core-i7.test index 401626b..d57a842 100644 --- a/tests/intel/x86-64/sandy-bridge/sandy-bridge-core-i7.test +++ b/tests/intel/x86-64/sandy-bridge/sandy-bridge-core-i7.test @@ -102,5 +102,5 @@ general -1 -1 128 (non-authoritative) -Sandy Bridge (Core i7) +Core i7 (Sandy Bridge) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd popcnt aes xsave osxsave avx rdtscp lm lahf_lm constant_tsc diff --git a/tests/intel/x86-64/sandy-bridge/sandy-bridge-e-core-i7.test b/tests/intel/x86-64/sandy-bridge/sandy-bridge-e-core-i7.test index 91a5729..e233a38 100644 --- a/tests/intel/x86-64/sandy-bridge/sandy-bridge-e-core-i7.test +++ b/tests/intel/x86-64/sandy-bridge/sandy-bridge-e-core-i7.test @@ -102,5 +102,5 @@ general -1 -1 128 (non-authoritative) -Sandy Bridge-E (Core i7) +Core i7 Extreme (Sandy Bridge-E) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm dca sse4_1 sse4_2 popcnt aes xsave osxsave avx rdtscp lm lahf_lm constant_tsc x2apic diff --git a/tests/intel/x86-64/sandy-bridge/sandy-bridge-e-xeon-e5.test b/tests/intel/x86-64/sandy-bridge/sandy-bridge-e-xeon-e5.test index 58a34e9..f993f16 100644 --- a/tests/intel/x86-64/sandy-bridge/sandy-bridge-e-xeon-e5.test +++ b/tests/intel/x86-64/sandy-bridge/sandy-bridge-e-xeon-e5.test @@ -102,5 +102,5 @@ general -1 -1 128 (non-authoritative) -Sandy Bridge-E (Xeon) +Xeon E5 (Sandy Bridge-E) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm dca sse4_1 sse4_2 xd popcnt aes xsave osxsave avx rdtscp lm lahf_lm constant_tsc x2apic diff --git a/tests/intel/x86-64/sandy-bridge/sandy-bridge-xeon-e3.test b/tests/intel/x86-64/sandy-bridge/sandy-bridge-xeon-e3.test index c41f247..11c4bec 100644 --- a/tests/intel/x86-64/sandy-bridge/sandy-bridge-xeon-e3.test +++ b/tests/intel/x86-64/sandy-bridge/sandy-bridge-xeon-e3.test @@ -110,5 +110,5 @@ general -1 -1 128 (non-authoritative) -Sandy Bridge (Xeon) +Xeon E3 (Sandy Bridge) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 syscall xd popcnt aes xsave osxsave avx rdtscp lm lahf_lm constant_tsc x2apic diff --git a/tests/intel/x86-64/skylake/cannon-lake-core-i3-u.test b/tests/intel/x86-64/skylake/cannon-lake-core-i3-u.test index b696e85..f8cafba 100644 --- a/tests/intel/x86-64/skylake/cannon-lake-core-i3-u.test +++ b/tests/intel/x86-64/skylake/cannon-lake-core-i3-u.test @@ -230,5 +230,5 @@ general 1 0 128 (non-authoritative) -Cannon Lake (Core i3) +Core i3 (Cannon Lake-U) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 avx512f avx512dq avx512cd sha_ni avx512bw avx512vl rdseed adx avx512vbmi diff --git a/tests/intel/x86-64/skylake/cascade-lake-sp-xeon-gold.test b/tests/intel/x86-64/skylake/cascade-lake-sp-xeon-gold.test index 084febc..d460c4a 100644 --- a/tests/intel/x86-64/skylake/cascade-lake-sp-xeon-gold.test +++ b/tests/intel/x86-64/skylake/cascade-lake-sp-xeon-gold.test @@ -1030,5 +1030,5 @@ general 1 0 128 (non-authoritative) -Cascade Lake-SP (Xeon Gold) +Xeon Gold (Cascade Lake-SP) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm dca sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 hle rtm avx512f avx512dq avx512cd avx512bw avx512vl rdseed adx avx512vnni diff --git a/tests/intel/x86-64/skylake/cascade-lake-sp-xeon-platinum.test b/tests/intel/x86-64/skylake/cascade-lake-sp-xeon-platinum.test index 499d49d..449d9d9 100644 --- a/tests/intel/x86-64/skylake/cascade-lake-sp-xeon-platinum.test +++ b/tests/intel/x86-64/skylake/cascade-lake-sp-xeon-platinum.test @@ -2774,5 +2774,5 @@ general 1 0 128 (non-authoritative) -Cascade Lake-SP (Xeon Platinum) +Xeon Platinum (Cascade Lake-SP) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm dca sse4_1 sse4_2 syscall xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 hle rtm avx512f avx512dq avx512cd avx512bw avx512vl rdseed adx avx512vnni diff --git a/tests/intel/x86-64/skylake/cascade-lake-sp-xeon-silver.test b/tests/intel/x86-64/skylake/cascade-lake-sp-xeon-silver.test index 488eed0..08e7a20 100644 --- a/tests/intel/x86-64/skylake/cascade-lake-sp-xeon-silver.test +++ b/tests/intel/x86-64/skylake/cascade-lake-sp-xeon-silver.test @@ -1230,5 +1230,5 @@ general 1 0 128 (non-authoritative) -Cascade Lake-SP (Xeon Silver) +Xeon Silver (Cascade Lake-SP) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm dca sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 hle rtm avx512f avx512dq avx512cd avx512bw avx512vl rdseed adx avx512vnni diff --git a/tests/intel/x86-64/skylake/cascade-lake-w-xeon-w.test b/tests/intel/x86-64/skylake/cascade-lake-w-xeon-w.test index eb48b4f..417627b 100644 --- a/tests/intel/x86-64/skylake/cascade-lake-w-xeon-w.test +++ b/tests/intel/x86-64/skylake/cascade-lake-w-xeon-w.test @@ -2830,5 +2830,5 @@ general 1 0 128 (non-authoritative) -Cascade Lake-W (Xeon W) +Xeon W (Cascade Lake-W) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm dca sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 hle rtm avx512f avx512dq avx512cd avx512bw avx512vl rdseed adx avx512vnni diff --git a/tests/intel/x86-64/skylake/cascade-lake-x-core-i9.test b/tests/intel/x86-64/skylake/cascade-lake-x-core-i9.test index 2b65ec3..cfc9f51 100644 --- a/tests/intel/x86-64/skylake/cascade-lake-x-core-i9.test +++ b/tests/intel/x86-64/skylake/cascade-lake-x-core-i9.test @@ -1794,5 +1794,5 @@ general 1 0 128 (non-authoritative) -Cascade Lake-X (Core i9) +Core i9 (Cascade Lake-X) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm dca sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 hle rtm avx512f avx512dq avx512cd avx512bw avx512vl rdseed adx avx512vnni diff --git a/tests/intel/x86-64/skylake/coffee-lake-core-i7.test b/tests/intel/x86-64/skylake/coffee-lake-core-i7.test index ba4de0d..1bf7124 100644 --- a/tests/intel/x86-64/skylake/coffee-lake-core-i7.test +++ b/tests/intel/x86-64/skylake/coffee-lake-core-i7.test @@ -106,5 +106,5 @@ general -1 -1 128 (non-authoritative) -Coffee Lake (Core i7) +Core i7 (Coffee Lake-S) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 syscall xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 hle rtm sgx rdseed adx diff --git a/tests/intel/x86-64/skylake/comet-lake-core-i7-u.test b/tests/intel/x86-64/skylake/comet-lake-core-i7-u.test index d1ecb35..f3108d5 100644 --- a/tests/intel/x86-64/skylake/comet-lake-core-i7-u.test +++ b/tests/intel/x86-64/skylake/comet-lake-core-i7-u.test @@ -110,5 +110,5 @@ general -1 -1 128 (non-authoritative) -Comet Lake-U (Core i7) +Core i7 (Comet Lake-U) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 syscall xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sgx rdseed adx diff --git a/tests/intel/x86-64/skylake/kaby-lake-core-i7-g.test b/tests/intel/x86-64/skylake/kaby-lake-core-i7-g.test index 5956716..6360c16 100644 --- a/tests/intel/x86-64/skylake/kaby-lake-core-i7-g.test +++ b/tests/intel/x86-64/skylake/kaby-lake-core-i7-g.test @@ -382,5 +382,5 @@ general 1 0 128 (non-authoritative) -Kaby Lake-G (Core i7) +Core i7 (Kaby Lake-G) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 syscall xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sgx rdseed adx diff --git a/tests/intel/x86-64/skylake/kaby-lake-core-i7-u.test b/tests/intel/x86-64/skylake/kaby-lake-core-i7-u.test index a0bb835..e5c789f 100644 --- a/tests/intel/x86-64/skylake/kaby-lake-core-i7-u.test +++ b/tests/intel/x86-64/skylake/kaby-lake-core-i7-u.test @@ -106,5 +106,5 @@ general -1 -1 128 (non-authoritative) -Kaby Lake-U (Core i7) +Core i7 (Kaby Lake-U) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 syscall xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sgx rdseed adx diff --git a/tests/intel/x86-64/skylake/kaby-lake-r-core-i5.test b/tests/intel/x86-64/skylake/kaby-lake-r-core-i5.test index 8f650d0..fd4a243 100644 --- a/tests/intel/x86-64/skylake/kaby-lake-r-core-i5.test +++ b/tests/intel/x86-64/skylake/kaby-lake-r-core-i5.test @@ -110,5 +110,5 @@ general -1 -1 128 (non-authoritative) -Kaby Lake-R (Core i5) +Core i5 (Kaby Lake-R) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 syscall xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 hle rtm sgx rdseed adx diff --git a/tests/intel/x86-64/skylake/skylake-core-i5.test b/tests/intel/x86-64/skylake/skylake-core-i5.test index 3b18d66..44af8a8 100644 --- a/tests/intel/x86-64/skylake/skylake-core-i5.test +++ b/tests/intel/x86-64/skylake/skylake-core-i5.test @@ -102,5 +102,5 @@ general -1 -1 128 (non-authoritative) -Skylake (Core i5) +Core i5 (Skylake) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 hle rtm rdseed adx diff --git a/tests/intel/x86-64/skylake/skylake-de-xeon-d.test b/tests/intel/x86-64/skylake/skylake-de-xeon-d.test index c61f796..dd15e1f 100644 --- a/tests/intel/x86-64/skylake/skylake-de-xeon-d.test +++ b/tests/intel/x86-64/skylake/skylake-de-xeon-d.test @@ -1630,5 +1630,5 @@ general 1 0 128 (non-authoritative) -Skylake-DE (Xeon D) +Xeon D (Skylake-DE) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm dca sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 hle rtm avx512f avx512dq avx512cd avx512bw avx512vl rdseed adx diff --git a/tests/intel/x86-64/skylake/skylake-pentium.test b/tests/intel/x86-64/skylake/skylake-pentium.test index 69de251..5a4663f 100644 --- a/tests/intel/x86-64/skylake/skylake-pentium.test +++ b/tests/intel/x86-64/skylake/skylake-pentium.test @@ -106,5 +106,5 @@ general -1 -1 128 (non-authoritative) -Skylake (Pentium) +Pentium (Skylake) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 syscall xd movbe popcnt aes xsave osxsave rdtscp lm lahf_lm abm constant_tsc rdrand x2apic sgx rdseed diff --git a/tests/intel/x86-64/skylake/skylake-sp-xeon-bronze.test b/tests/intel/x86-64/skylake/skylake-sp-xeon-bronze.test index bfb9c1c..c89eace 100644 --- a/tests/intel/x86-64/skylake/skylake-sp-xeon-bronze.test +++ b/tests/intel/x86-64/skylake/skylake-sp-xeon-bronze.test @@ -630,7 +630,7 @@ general 1 0 128 (non-authoritative) -Skylake-SP (Xeon Bronze) +Xeon Bronze (Skylake-SP) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm dca sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 hle rtm avx512f avx512dq avx512cd avx512bw avx512vl rdseed adx -------------------------------------------------------------------------------- x86 @@ -664,5 +664,5 @@ general 1 0 128 (non-authoritative) -Skylake-SP (Xeon Bronze) +Xeon Bronze (Skylake-SP) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm dca sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 hle rtm avx512f avx512dq avx512cd avx512bw avx512vl rdseed adx diff --git a/tests/intel/x86-64/skylake/skylake-sp-xeon-gold.test b/tests/intel/x86-64/skylake/skylake-sp-xeon-gold.test index 9bbda4d..9cac481 100644 --- a/tests/intel/x86-64/skylake/skylake-sp-xeon-gold.test +++ b/tests/intel/x86-64/skylake/skylake-sp-xeon-gold.test @@ -3630,7 +3630,7 @@ general 1 0 128 (non-authoritative) -Skylake-SP (Xeon Gold) +Xeon Gold (Skylake-SP) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm dca sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 hle rtm avx512f avx512dq avx512cd avx512bw avx512vl rdseed adx -------------------------------------------------------------------------------- x86 @@ -3664,5 +3664,5 @@ general 1 0 128 (non-authoritative) -Skylake-SP (Xeon Gold) +Xeon Gold (Skylake-SP) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm dca sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 hle rtm avx512f avx512dq avx512cd avx512bw avx512vl rdseed adx diff --git a/tests/intel/x86-64/skylake/skylake-sp-xeon-platinum.test b/tests/intel/x86-64/skylake/skylake-sp-xeon-platinum.test index 82877c9..e4185a1 100644 --- a/tests/intel/x86-64/skylake/skylake-sp-xeon-platinum.test +++ b/tests/intel/x86-64/skylake/skylake-sp-xeon-platinum.test @@ -5630,7 +5630,7 @@ general 1 0 128 (non-authoritative) -Skylake-SP (Xeon Platinum) +Xeon Platinum (Skylake-SP) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm dca sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 hle rtm avx512f avx512dq avx512cd avx512bw avx512vl rdseed adx -------------------------------------------------------------------------------- x86 @@ -5664,5 +5664,5 @@ general 1 0 128 (non-authoritative) -Skylake-SP (Xeon Platinum) +Xeon Platinum (Skylake-SP) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm dca sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 hle rtm avx512f avx512dq avx512cd avx512bw avx512vl rdseed adx diff --git a/tests/intel/x86-64/skylake/skylake-sp-xeon-silver.test b/tests/intel/x86-64/skylake/skylake-sp-xeon-silver.test index 1c240eb..79cd691 100644 --- a/tests/intel/x86-64/skylake/skylake-sp-xeon-silver.test +++ b/tests/intel/x86-64/skylake/skylake-sp-xeon-silver.test @@ -1630,7 +1630,7 @@ general 1 0 128 (non-authoritative) -Skylake-SP (Xeon Silver) +Xeon Silver (Skylake-SP) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm dca sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 hle rtm avx512f avx512dq avx512cd avx512bw avx512vl rdseed adx -------------------------------------------------------------------------------- x86 @@ -1664,5 +1664,5 @@ general 1 0 128 (non-authoritative) -Skylake-SP (Xeon Silver) +Xeon Silver (Skylake-SP) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm dca sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 hle rtm avx512f avx512dq avx512cd avx512bw avx512vl rdseed adx diff --git a/tests/intel/x86-64/skylake/skylake-w-xeon-w.test b/tests/intel/x86-64/skylake/skylake-w-xeon-d.test similarity index 99% rename from tests/intel/x86-64/skylake/skylake-w-xeon-w.test rename to tests/intel/x86-64/skylake/skylake-w-xeon-d.test index c61f796..dd15e1f 100644 --- a/tests/intel/x86-64/skylake/skylake-w-xeon-w.test +++ b/tests/intel/x86-64/skylake/skylake-w-xeon-d.test @@ -1630,5 +1630,5 @@ general 1 0 128 (non-authoritative) -Skylake-DE (Xeon D) +Xeon D (Skylake-DE) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm dca sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 hle rtm avx512f avx512dq avx512cd avx512bw avx512vl rdseed adx diff --git a/tests/intel/x86-64/skylake/skylake-x-core-i7.test b/tests/intel/x86-64/skylake/skylake-x-core-i7.test index 934c08d..0b995dd 100644 --- a/tests/intel/x86-64/skylake/skylake-x-core-i7.test +++ b/tests/intel/x86-64/skylake/skylake-x-core-i7.test @@ -106,5 +106,5 @@ general -1 -1 128 (non-authoritative) -Skylake-X (Core i7) +Core i7 (Skylake-X) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm dca sse4_1 sse4_2 syscall xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 hle rtm avx512f avx512dq avx512cd avx512bw avx512vl rdseed adx diff --git a/tests/intel/x86-64/skylake/whiskey-lake-core-i5-u.test b/tests/intel/x86-64/skylake/whiskey-lake-core-i5-u.test index 8b18bac..51a8281 100644 --- a/tests/intel/x86-64/skylake/whiskey-lake-core-i5-u.test +++ b/tests/intel/x86-64/skylake/whiskey-lake-core-i5-u.test @@ -110,5 +110,5 @@ general -1 -1 128 (non-authoritative) -Whiskey Lake-U (Core i5) +Core i5 (Whiskey Lake-U) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 syscall xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sgx rdseed adx diff --git a/tests/intel/x86-64/sunny-cove/ice-lake-d-xeon-d.test b/tests/intel/x86-64/sunny-cove/ice-lake-d-xeon-d.test index ac8c5b6..d6f1685 100644 --- a/tests/intel/x86-64/sunny-cove/ice-lake-d-xeon-d.test +++ b/tests/intel/x86-64/sunny-cove/ice-lake-d-xeon-d.test @@ -542,5 +542,5 @@ general 1 0 128 (non-authoritative) -Ice Lake-D (Xeon-D) +Xeon D (Ice Lake-D) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 syscall xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 hle rtm avx512f avx512dq avx512cd sha_ni avx512bw avx512vl rdseed adx avx512vnni avx512vbmi avx512vbmi2 hypervisor diff --git a/tests/intel/x86-64/sunny-cove/ice-lake-i5.test b/tests/intel/x86-64/sunny-cove/ice-lake-i5.test index e68097c..4f502e1 100644 --- a/tests/intel/x86-64/sunny-cove/ice-lake-i5.test +++ b/tests/intel/x86-64/sunny-cove/ice-lake-i5.test @@ -526,5 +526,5 @@ general 1 0 128 (non-authoritative) -Ice Lake (Core i5) +Core i5 (Ice Lake) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 avx512f avx512dq avx512cd sha_ni avx512bw avx512vl sgx rdseed adx avx512vnni avx512vbmi avx512vbmi2 diff --git a/tests/intel/x86-64/sunny-cove/ice-lake-i7.test b/tests/intel/x86-64/sunny-cove/ice-lake-i7.test index b9b746b..70980d2 100644 --- a/tests/intel/x86-64/sunny-cove/ice-lake-i7.test +++ b/tests/intel/x86-64/sunny-cove/ice-lake-i7.test @@ -526,5 +526,5 @@ general 1 0 128 (non-authoritative) -Ice Lake (Core i7) +Core i7 (Ice Lake) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 avx512f avx512dq avx512cd sha_ni avx512bw avx512vl sgx rdseed adx avx512vnni avx512vbmi avx512vbmi2 diff --git a/tests/intel/x86-64/willow-cove/tiger-lake-core-i5.test b/tests/intel/x86-64/willow-cove/tiger-lake-core-i5.test index e16b356..cf69773 100644 --- a/tests/intel/x86-64/willow-cove/tiger-lake-core-i5.test +++ b/tests/intel/x86-64/willow-cove/tiger-lake-core-i5.test @@ -110,5 +110,5 @@ general -1 -1 128 (non-authoritative) -Tiger Lake (Core i5) +Core i5 (Tiger Lake-UP3) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 syscall xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 avx512f avx512dq avx512cd sha_ni avx512bw avx512vl rdseed adx avx512vnni avx512vbmi avx512vbmi2 diff --git a/tests/intel/x86-atom/goldmont-plus/apollo-lake-atom-x5.test b/tests/intel/x86-atom/goldmont-plus/apollo-lake-atom-x5.test index f6505da..2890a35 100644 --- a/tests/intel/x86-atom/goldmont-plus/apollo-lake-atom-x5.test +++ b/tests/intel/x86-atom/goldmont-plus/apollo-lake-atom-x5.test @@ -116,5 +116,5 @@ general 0 0 128 (non-authoritative) -Apollo Lake (Atom) +Atom (Apollo Lake) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave rdtscp lm lahf_lm constant_tsc rdrand x2apic sha_ni rdseed diff --git a/tests/intel/x86-atom/goldmont-plus/gemini-lake-celeron.test b/tests/intel/x86-atom/goldmont-plus/gemini-lake-celeron.test index c6055a8..0b17947 100644 --- a/tests/intel/x86-atom/goldmont-plus/gemini-lake-celeron.test +++ b/tests/intel/x86-atom/goldmont-plus/gemini-lake-celeron.test @@ -110,5 +110,5 @@ general -1 -1 128 (non-authoritative) -Gemini Lake (Celeron) +Celeron (Gemini Lake) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 syscall xd movbe popcnt aes xsave osxsave rdtscp lm lahf_lm constant_tsc rdrand x2apic sha_ni sgx rdseed diff --git a/tests/intel/x86-atom/gracemont/alder-lake-n-core-i3.test b/tests/intel/x86-atom/gracemont/alder-lake-n-core-i3.test index 736152f..7cac808 100644 --- a/tests/intel/x86-atom/gracemont/alder-lake-n-core-i3.test +++ b/tests/intel/x86-atom/gracemont/alder-lake-n-core-i3.test @@ -566,5 +566,5 @@ general 1 0 128 (non-authoritative) -Alder Lake-N (Core i3) +Core i3 (Alder Lake-N) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx diff --git a/tests/intel/x86-atom/gracemont/alder-lake-n95.test b/tests/intel/x86-atom/gracemont/alder-lake-n95.test index d13d896..84cbf18 100644 --- a/tests/intel/x86-atom/gracemont/alder-lake-n95.test +++ b/tests/intel/x86-atom/gracemont/alder-lake-n95.test @@ -298,5 +298,5 @@ general 1 0 128 (non-authoritative) -Alder Lake-N (Intel Processor) +Intel Processor (Alder Lake-N) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx diff --git a/tests/intel/x86-atom/gracemont/twin-lake-n-core-3.test b/tests/intel/x86-atom/gracemont/twin-lake-n-core-3.test index cde2bf3..abafc67 100644 --- a/tests/intel/x86-atom/gracemont/twin-lake-n-core-3.test +++ b/tests/intel/x86-atom/gracemont/twin-lake-n-core-3.test @@ -558,5 +558,5 @@ general 1 0 128 (non-authoritative) -Twin Lake-N (Core 3) +Core 3 (Twin Lake-N) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx diff --git a/tests/intel/x86-atom/silvermont/bay-trail-d-celeron.test b/tests/intel/x86-atom/silvermont/bay-trail-d-celeron.test index fb5826c..691231d 100644 --- a/tests/intel/x86-atom/silvermont/bay-trail-d-celeron.test +++ b/tests/intel/x86-atom/silvermont/bay-trail-d-celeron.test @@ -130,5 +130,5 @@ general -1 -1 128 (non-authoritative) -Bay Trail-D (Celeron) +Celeron (Bay Trail-D) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt rdtscp lm lahf_lm constant_tsc rdrand diff --git a/tests/intel/x86-atom/silvermont/bay-trail-t-atom-e3827.test b/tests/intel/x86-atom/silvermont/bay-trail-i-atom-e3827.test similarity index 99% rename from tests/intel/x86-atom/silvermont/bay-trail-t-atom-e3827.test rename to tests/intel/x86-atom/silvermont/bay-trail-i-atom-e3827.test index 7d70882..8690eaf 100644 --- a/tests/intel/x86-atom/silvermont/bay-trail-t-atom-e3827.test +++ b/tests/intel/x86-atom/silvermont/bay-trail-i-atom-e3827.test @@ -80,5 +80,5 @@ general 0 0 128 (non-authoritative) -Bay Trail-T (Atom) +Atom (Bay Trail-I) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes rdtscp lm lahf_lm constant_tsc rdrand diff --git a/tests/intel/x86-atom/silvermont/bay-trail-m-celeron.test b/tests/intel/x86-atom/silvermont/bay-trail-m-celeron.test index 8eeeaac..9b5d4b4 100644 --- a/tests/intel/x86-atom/silvermont/bay-trail-m-celeron.test +++ b/tests/intel/x86-atom/silvermont/bay-trail-m-celeron.test @@ -354,5 +354,5 @@ general 0 0 128 (non-authoritative) -Bay Trail-M (Celeron) +Celeron (Bay Trail-M) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 syscall xd movbe popcnt rdtscp lm lahf_lm constant_tsc rdrand diff --git a/tests/intel/x86-atom/silvermont/bay-trail-t-atom-z3740.test b/tests/intel/x86-atom/silvermont/bay-trail-t-atom-z3740.test index 7b631b9..8f4109c 100644 --- a/tests/intel/x86-atom/silvermont/bay-trail-t-atom-z3740.test +++ b/tests/intel/x86-atom/silvermont/bay-trail-t-atom-z3740.test @@ -130,5 +130,5 @@ general -1 -1 128 (non-authoritative) -Bay Trail-T (Atom) +Atom (Bay Trail-T) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes rdtscp lm lahf_lm constant_tsc rdrand diff --git a/tests/intel/x86-atom/tremont/elkhart-lake-celeron.test b/tests/intel/x86-atom/tremont/elkhart-lake-celeron.test index 0c533a8..fb2a757 100644 --- a/tests/intel/x86-atom/tremont/elkhart-lake-celeron.test +++ b/tests/intel/x86-atom/tremont/elkhart-lake-celeron.test @@ -242,5 +242,5 @@ general 1 0 128 (non-authoritative) -Elkhart Lake (Celeron) +Celeron (Elkhart Lake) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave rdtscp lm lahf_lm constant_tsc rdrand x2apic sha_ni rdseed diff --git a/tests/intel/x86-atom/tremont/jasper-lake-celeron.test b/tests/intel/x86-atom/tremont/jasper-lake-celeron.test index 342e300..25eea49 100644 --- a/tests/intel/x86-atom/tremont/jasper-lake-celeron.test +++ b/tests/intel/x86-atom/tremont/jasper-lake-celeron.test @@ -242,5 +242,5 @@ general 1 0 128 (non-authoritative) -Jasper Lake (Celeron) +Celeron (Jasper Lake) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave rdtscp lm lahf_lm constant_tsc rdrand x2apic sha_ni rdseed diff --git a/tests/intel/x86-atom/tremont/jasper-lake-pentium.test b/tests/intel/x86-atom/tremont/jasper-lake-pentium.test index 672784c..3cc8de5 100644 --- a/tests/intel/x86-atom/tremont/jasper-lake-pentium.test +++ b/tests/intel/x86-atom/tremont/jasper-lake-pentium.test @@ -242,5 +242,5 @@ general 1 0 128 (non-authoritative) -Jasper Lake (Pentium) +Pentium Silver (Jasper Lake) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave rdtscp lm lahf_lm constant_tsc rdrand x2apic sha_ni rdseed diff --git a/tests/intel/x86-atom/tremont/lakefield-core-i5.test b/tests/intel/x86-atom/tremont/lakefield-core-i5.test index cf1d791..918bced 100644 --- a/tests/intel/x86-atom/tremont/lakefield-core-i5.test +++ b/tests/intel/x86-atom/tremont/lakefield-core-i5.test @@ -297,7 +297,7 @@ efficiency 1 0 128 (non-authoritative) -Lakefield (Core i5) +Core i5 (Lakefield) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave rdtscp lm lahf_lm constant_tsc rdrand sha_ni rdseed -------------------------------------------------------------------------------- x86 @@ -331,5 +331,5 @@ performance 1 0 128 (non-authoritative) -Lakefield (Core i5) +Core i5 (Lakefield) fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave rdtscp lm lahf_lm constant_tsc rdrand sha_ni rdseed