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https://github.com/anrieff/libcpuid
synced 2025-10-03 11:01:30 +00:00
Xorg
parent
671174f567
commit
e0dce2b0ef
6 changed files with 1130 additions and 32 deletions
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@ -1142,38 +1142,59 @@ int cpu_identify_all(struct cpu_raw_data_array_t* raw_array, struct system_id_t*
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}
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}
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/* Update logical and physical CPU counters in system->cpu_types on the last iteration or when purpose is different than previous core */
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/* Update logical CPU counters, physical CPU counters and cache instance in system->cpu_types
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Note: we need to differenciate two events:
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- is_new_cpu_type (e.g. purpose was 'efficiency' during previous loop, and now purpose is 'performance')
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- is_last_item (i.e. this is the last iteration in raw_array->num_raw)
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In some cases, both events can occur during the same iteration, thus we have to update counters twice for the same logical_cpu.
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This occurs with single-core CPU type. For instance, Pentacore Lakefield CPU consists of:
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- 1 "big" Sunny Cove core
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- 4 "little" Tremont cores
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On the last iteration, there is no need to reset values for the next purpose.
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*/
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if (raw_array->with_affinity && (is_last_item || (is_new_cpu_type && (system->num_cpu_types > 1)))) {
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cpu_type_index = is_new_cpu_type && !is_last_item ? system->num_cpu_types - 2 : system->num_cpu_types - 1;
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copy_affinity_mask(&system->cpu_types[cpu_type_index].affinity_mask, &affinity_mask);
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if (!is_last_item) {
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init_affinity_mask(&affinity_mask);
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set_affinity_mask_bit(logical_cpu, &affinity_mask);
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}
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if (is_apic_supported) {
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system->cpu_types[cpu_type_index].num_cores = cores_type.instances;
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system->cpu_types[cpu_type_index].l1_instruction_instances = caches_type.instances[L1I];
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system->cpu_types[cpu_type_index].l1_data_instances = caches_type.instances[L1D];
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system->cpu_types[cpu_type_index].l2_instances = caches_type.instances[L2];
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system->cpu_types[cpu_type_index].l3_instances = caches_type.instances[L3];
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system->cpu_types[cpu_type_index].l4_instances = caches_type.instances[L4];
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if (!is_last_item) {
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core_instances_t_constructor(&cores_type);
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cache_instances_t_constructor(&caches_type);
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update_core_instances(&cores_type, &apic_info);
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update_cache_instances(&caches_type, &apic_info, &id_info, true);
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update_cache_instances(&caches_all, &apic_info, &id_info, false);
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enum event_t {
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EVENT_NEW_CPU_TYPE = 0,
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EVENT_LAST_ITEM = 1
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};
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const enum event_t first_event = is_new_cpu_type && (system->num_cpu_types > 1) ? EVENT_NEW_CPU_TYPE : EVENT_LAST_ITEM;
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const enum event_t last_event = is_last_item ? EVENT_LAST_ITEM : EVENT_NEW_CPU_TYPE;
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for (enum event_t event = first_event; event <= last_event; event++) {
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switch (event) {
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case EVENT_NEW_CPU_TYPE: cpu_type_index = system->num_cpu_types - 2; break;
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case EVENT_LAST_ITEM: cpu_type_index = system->num_cpu_types - 1; break;
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default: warnf("Warning: event %i in cpu_identify_all() not handled.\n", event); return set_error(ERR_NOT_IMP);
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}
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copy_affinity_mask(&system->cpu_types[cpu_type_index].affinity_mask, &affinity_mask);
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if (event != EVENT_LAST_ITEM) {
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init_affinity_mask(&affinity_mask);
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set_affinity_mask_bit(logical_cpu, &affinity_mask);
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}
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if (is_apic_supported) {
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system->cpu_types[cpu_type_index].num_cores = cores_type.instances;
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system->cpu_types[cpu_type_index].l1_instruction_instances = caches_type.instances[L1I];
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system->cpu_types[cpu_type_index].l1_data_instances = caches_type.instances[L1D];
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system->cpu_types[cpu_type_index].l2_instances = caches_type.instances[L2];
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system->cpu_types[cpu_type_index].l3_instances = caches_type.instances[L3];
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system->cpu_types[cpu_type_index].l4_instances = caches_type.instances[L4];
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if (event != EVENT_LAST_ITEM) {
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core_instances_t_constructor(&cores_type);
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cache_instances_t_constructor(&caches_type);
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update_core_instances(&cores_type, &apic_info);
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update_cache_instances(&caches_type, &apic_info, &id_info, true);
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update_cache_instances(&caches_all, &apic_info, &id_info, false);
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}
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}
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else {
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/* Note: if SMT is disabled by BIOS, smt_divisor will no reflect the current state properly */
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is_smt_supported = (system->cpu_types[cpu_type_index].num_logical_cpus % system->cpu_types[cpu_type_index].num_cores) == 0;
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smt_divisor = is_smt_supported ? system->cpu_types[cpu_type_index].num_logical_cpus / system->cpu_types[cpu_type_index].num_cores : 1.0;
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system->cpu_types[cpu_type_index].num_cores = num_logical_cpus / smt_divisor;
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}
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/* Save current values in system->cpu_types[cpu_type_index] and reset values for the next purpose */
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system->cpu_types[cpu_type_index].num_logical_cpus = num_logical_cpus;
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num_logical_cpus = 1;
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}
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else {
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/* Note: if SMT is disabled by BIOS, smt_divisor will no reflect the current state properly */
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is_smt_supported = (system->cpu_types[cpu_type_index].num_logical_cpus % system->cpu_types[cpu_type_index].num_cores) == 0;
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smt_divisor = is_smt_supported ? system->cpu_types[cpu_type_index].num_logical_cpus / system->cpu_types[cpu_type_index].num_cores : 1.0;
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system->cpu_types[cpu_type_index].num_cores = num_logical_cpus / smt_divisor;
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}
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/* Save current values in system->cpu_types[cpu_type_index] and reset values for the next purpose */
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system->cpu_types[cpu_type_index].num_logical_cpus = num_logical_cpus;
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num_logical_cpus = 1;
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}
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prev_package_id = cur_package_id;
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}
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@ -414,12 +414,21 @@ const struct match_entry_t cpudb_intel[] = {
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{ 6, 7, -1, -1, 167, -1, -1, -1, NC, CORE_|_I_|_5 ,_11xxx, "Rocket Lake (Core i5)" },
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{ 6, 7, -1, -1, 167, -1, -1, -1, NC, CORE_|_I_|_3 ,_11xxx, "Rocket Lake (Core i3)" },
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/* Goldmont Plus CPUs (14nm) */
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/* Goldmont Plus CPUs (2017, 14nm, low-power) */
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{ 6, 10, -1, -1, 122, 4, -1, -1, NC, PENTIUM_ , 0, "Gemini Lake (Pentium)" },
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{ 6, 10, -1, -1, 122, 4, -1, -1, NC, CELERON_ , 0, "Gemini Lake (Celeron)" },
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{ 6, 10, -1, -1, 122, 2, -1, -1, NC, CELERON_ , 0, "Gemini Lake (Celeron)" },
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/* Tiger Lake CPUs (11th gen, 10nm, mobile processors): */
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/* Tremont CPUs (2020, 10nm, low-power) */
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{ 6, 6, -1, -1, 150, -1, -1, -1, NC, PENTIUM_ , 0, "Elkhart Lake (Pentium)" },
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{ 6, 6, -1, -1, 150, -1, -1, -1, NC, CELERON_ , 0, "Elkhart Lake (Celeron)" },
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{ 6, 6, -1, -1, 150, -1, -1, -1, NC, ATOM_ , 0, "Elkhart Lake (Atom)" },
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{ 6, 10, -1, -1, 138, -1, -1, -1, NC, CORE_|_I_|_5 , 0, "Lakefield (Core i5)" },
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{ 6, 10, -1, -1, 138, -1, -1, -1, NC, CORE_|_I_|_3 , 0, "Lakefield (Core i3)" },
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{ 6, 12, -1, -1, 156, -1, -1, -1, NC, PENTIUM_ , 0, "Jasper Lake (Pentium)" },
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{ 6, 12, -1, -1, 156, -1, -1, -1, NC, CELERON_ , 0, "Jasper Lake (Celeron)" },
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/* Tiger Lake CPUs (2020, 11th gen, 10nm, mobile processors): */
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{ 6, 12, -1, -1, 140, -1, -1, -1, NC, CORE_|_I_|_9 ,_11xxx, "Tiger Lake (Core i9)" },
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{ 6, 12, -1, -1, 140, -1, -1, -1, NC, CORE_|_I_|_7 ,_11xxx, "Tiger Lake (Core i7)" },
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{ 6, 12, -1, -1, 140, -1, -1, -1, NC, CORE_|_I_|_5 ,_11xxx, "Tiger Lake (Core i5)" },
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@ -696,7 +705,7 @@ static intel_code_and_bits_t get_brand_code_and_bits(struct cpu_id_t* data)
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const struct { uint64_t bit; const char* search; } bit_matchtable[] = {
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{ XEON_, "Xeon" },
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{ _MP_, " MP" },
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{ ATOM_, "Atom(TM) CPU" },
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{ ATOM_, "Atom" },
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{ MOBILE_, "Mobile" },
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{ CELERON_, "Celeron" },
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{ PENTIUM_, "Pentium" },
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