From f3f92402dcf36c1cc79d8a73b318fd6abeb1f96f Mon Sep 17 00:00:00 2001 From: Veselin Georgiev Date: Tue, 17 May 2016 13:21:43 +0300 Subject: [PATCH] Remove duplication of data in lists intel_code_t / intel_bcode_str, etc. --- libcpuid/amd_code_t.h | 67 +++++++++++++++++++++++ libcpuid/intel_code_t.h | 85 +++++++++++++++++++++++++++++ libcpuid/recog_amd.c | 81 +++------------------------ libcpuid/recog_intel.c | 118 +++------------------------------------- 4 files changed, 167 insertions(+), 184 deletions(-) create mode 100644 libcpuid/amd_code_t.h create mode 100644 libcpuid/intel_code_t.h diff --git a/libcpuid/amd_code_t.h b/libcpuid/amd_code_t.h new file mode 100644 index 0000000..a742767 --- /dev/null +++ b/libcpuid/amd_code_t.h @@ -0,0 +1,67 @@ +/* + * Copyright 2016 Veselin Georgiev, + * anrieffNOSPAM @ mgail_DOT.com (convert to gmail) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file contains a list of internal codes we use in detection. It is + * of no external use and isn't a complete list of AMD products. + */ + CODE(NA), + CODE(NO_CODE), + CODE(OPTERON_GENERIC), + CODE(OPTERON_800), + CODE(ATHLON_XP), + CODE(ATHLON_XP_M), + CODE(ATHLON_XP_M_LV), + CODE(ATHLON), + CODE(ATHLON_MP), + CODE(MOBILE_ATHLON64), + CODE(ATHLON_FX), + CODE(DURON), + CODE(DURON_MP), + CODE(MOBILE_DURON), + CODE(MOBILE_SEMPRON), + CODE(OPTERON_SINGLE), + CODE(OPTERON_DUALCORE), + CODE(OPTERON_800_DUALCORE), + CODE(MOBILE_TURION), + CODE(ATHLON_64), + CODE(ATHLON_64_FX), + CODE(TURION_64), + CODE(TURION_X2), + CODE(SEMPRON), + CODE(M_SEMPRON), + CODE(SEMPRON_DUALCORE), + CODE(PHENOM), + CODE(PHENOM2), + CODE(ATHLON_64_X2), + CODE(ATHLON_64_X3), + CODE(ATHLON_64_X4), + CODE(FUSION_C), + CODE(FUSION_E), + CODE(FUSION_EA), + CODE(FUSION_Z), + CODE(FUSION_A), + diff --git a/libcpuid/intel_code_t.h b/libcpuid/intel_code_t.h new file mode 100644 index 0000000..a1e0241 --- /dev/null +++ b/libcpuid/intel_code_t.h @@ -0,0 +1,85 @@ +/* + * Copyright 2016 Veselin Georgiev, + * anrieffNOSPAM @ mgail_DOT.com (convert to gmail) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file contains a list of internal codes we use in detection. It is + * of no external use and isn't a complete list of intel products. + */ + CODE(NA), + CODE(NO_CODE), + CODE(PENTIUM), + CODE(MOBILE_PENTIUM), + + CODE(XEON), + CODE(XEON_IRWIN), + CODE(XEONMP), + CODE(XEON_POTOMAC), + CODE(XEON_I7), + CODE(XEON_GAINESTOWN), + CODE(XEON_WESTMERE), + + CODE(MOBILE_PENTIUM_M), + CODE(CELERON), + CODE(MOBILE_CELERON), + CODE(NOT_CELERON), + + + CODE(CORE_SOLO), + CODE(MOBILE_CORE_SOLO), + CODE(CORE_DUO), + CODE(MOBILE_CORE_DUO), + + CODE(WOLFDALE), + CODE(MEROM), + CODE(PENRYN), + CODE(QUAD_CORE), + CODE(DUAL_CORE_HT), + CODE(QUAD_CORE_HT), + CODE(MORE_THAN_QUADCORE), + CODE(PENTIUM_D), + + CODE(ATOM), + CODE(ATOM_SILVERTHORNE), + CODE(ATOM_DIAMONDVILLE), + CODE(ATOM_PINEVIEW), + CODE(ATOM_CEDARVIEW), + + CODE(CORE_I3), + CODE(CORE_I5), + CODE(CORE_I7), + CODE(CORE_IVY3), /* 22nm Core-iX */ + CODE(CORE_IVY5), + CODE(CORE_IVY7), + CODE(CORE_HASWELL3), /* 22nm Core-iX, Haswell */ + CODE(CORE_HASWELL5), + CODE(CORE_HASWELL7), + CODE(CORE_BROADWELL3), /* 14nm Core-iX, Broadwell */ + CODE(CORE_BROADWELL5), + CODE(CORE_BROADWELL7), + CODE(CORE_SKYLAKE3), /* 14nm Core-iX, Skylake */ + CODE(CORE_SKYLAKE5), + CODE(CORE_SKYLAKE7), + diff --git a/libcpuid/recog_amd.c b/libcpuid/recog_amd.c index cf6d5fc..668d49b 100644 --- a/libcpuid/recog_amd.c +++ b/libcpuid/recog_amd.c @@ -32,82 +32,16 @@ #include "libcpuid_util.h" enum _amd_code_t { - NA, - NO_CODE, - OPTERON_GENERIC, - OPTERON_800, - ATHLON_XP, - ATHLON_XP_M, - ATHLON_XP_M_LV, - ATHLON, - ATHLON_MP, - MOBILE_ATHLON64, - ATHLON_FX, - DURON, - DURON_MP, - MOBILE_DURON, - MOBILE_SEMPRON, - OPTERON_SINGLE, - OPTERON_DUALCORE, - OPTERON_800_DUALCORE, - MOBILE_TURION, - ATHLON_64, - ATHLON_64_FX, - TURION_64, - TURION_X2, - SEMPRON, - M_SEMPRON, - SEMPRON_DUALCORE, - PHENOM, - PHENOM2, - ATHLON_64_X2, - ATHLON_64_X3, - ATHLON_64_X4, - FUSION_C, - FUSION_E, - FUSION_EA, - FUSION_Z, - FUSION_A, + #define CODE(x) x + #include "amd_code_t.h" + #undef CODE }; typedef enum _amd_code_t amd_code_t; const struct amd_code_str { amd_code_t code; char *str; } amd_code_str[] = { - { NO_CODE, "NO_CODE", }, - { OPTERON_GENERIC, "OPTERON_GENERIC", }, - { OPTERON_800, "OPTERON_800", }, - { ATHLON_XP, "ATHLON_XP", }, - { ATHLON_XP_M, "ATHLON_XP_M", }, - { ATHLON_XP_M_LV, "ATHLON_XP_M_LV", }, - { ATHLON, "ATHLON", }, - { ATHLON_MP, "ATHLON_MP", }, - { MOBILE_ATHLON64, "MOBILE_ATHLON64", }, - { ATHLON_FX, "ATHLON_FX", }, - { DURON, "DURON", }, - { DURON_MP, "DURON_MP", }, - { MOBILE_DURON, "MOBILE_DURON", }, - { MOBILE_SEMPRON, "MOBILE_SEMPRON", }, - { OPTERON_SINGLE, "OPTERON_SINGLE", }, - { OPTERON_DUALCORE, "OPTERON_DUALCORE", }, - { OPTERON_800_DUALCORE, "OPTERON_800_DUALCORE",}, - { MOBILE_TURION, "MOBILE_TURION", }, - { ATHLON_64, "ATHLON_64", }, - { ATHLON_64_FX, "ATHLON_64_FX", }, - { TURION_64, "TURION_64", }, - { TURION_X2, "TURION_X2", }, - { SEMPRON, "SEMPRON", }, - { M_SEMPRON, "M_SEMPRON", }, - { SEMPRON_DUALCORE, "SEMPRON_DUALCORE", }, - { PHENOM, "PHENOM", }, - { PHENOM2, "PHENOM2", }, - { ATHLON_64_X2, "ATHLON_64_X2", }, - { ATHLON_64_X3, "ATHLON_64_X3", }, - { ATHLON_64_X4, "ATHLON_64_X4", }, - { FUSION_C, "FUSION_C", }, - { FUSION_E, "FUSION_E", }, - { FUSION_EA, "FUSION_EA", }, - { FUSION_Z, "FUSION_Z", }, - { FUSION_A, "FUSION_A", }, - { NA, "NA", }, + #define CODE(x) { x, #x } + #include "amd_code_t.h" + #undef CODE }; const struct match_entry_t cpudb_amd[] = { @@ -524,12 +458,11 @@ static void decode_amd_codename(struct cpu_raw_data_t* raw, struct cpu_id_t* dat amd_code_t code = decode_amd_codename_part1(data->brand_str); int i = 0; char* code_str = NULL; - while (amd_code_str[i].code != NA) { + for (i = 0; i < COUNT_OF(amd_code_str); i++) { if (code == amd_code_str[i].code) { code_str = amd_code_str[i].str; break; } - i++; } if (code_str) debugf(2, "Detected AMD brand code: %d (%s)\n", code, code_str); diff --git a/libcpuid/recog_intel.c b/libcpuid/recog_intel.c index aad96a8..8d01c3b 100644 --- a/libcpuid/recog_intel.c +++ b/libcpuid/recog_intel.c @@ -31,117 +31,16 @@ enum _intel_code_t { - NA, - NO_CODE, - PENTIUM = 10, - MOBILE_PENTIUM, - - XEON = 20, - XEON_IRWIN, - XEONMP, - XEON_POTOMAC, - XEON_I7, - XEON_GAINESTOWN, - XEON_WESTMERE, - - MOBILE_PENTIUM_M = 30, - CELERON, - MOBILE_CELERON, - NOT_CELERON, - - - CORE_SOLO = 40, - MOBILE_CORE_SOLO, - CORE_DUO, - MOBILE_CORE_DUO, - - WOLFDALE = 50, - MEROM, - PENRYN, - QUAD_CORE, - DUAL_CORE_HT, - QUAD_CORE_HT, - MORE_THAN_QUADCORE, - PENTIUM_D, - - ATOM = 60, - ATOM_SILVERTHORNE, - ATOM_DIAMONDVILLE, - ATOM_PINEVIEW, - ATOM_CEDARVIEW, - - CORE_I3 = 70, - CORE_I5, - CORE_I7, - CORE_IVY3, /* 22nm Core-iX */ - CORE_IVY5, - CORE_IVY7, - CORE_HASWELL3, /* 22nm Core-iX, Haswell */ - CORE_HASWELL5, - CORE_HASWELL7, - CORE_BROADWELL3, /* 14nm Core-iX, Broadwell */ - CORE_BROADWELL5, - CORE_BROADWELL7, - CORE_SKYLAKE3, /* 14nm Core-iX, Skylake */ - CORE_SKYLAKE5, - CORE_SKYLAKE7, + #define CODE(x) x + #include "intel_code_t.h" + #undef CODE }; typedef enum _intel_code_t intel_code_t; const struct intel_bcode_str { intel_code_t code; char *str; } intel_bcode_str[] = { - { NO_CODE, "NO_CODE", }, - { PENTIUM, "PENTIUM", }, - { MOBILE_PENTIUM, "MOBILE_PENTIUM", }, - - { XEON, "XEON", }, - { XEON_IRWIN, "XEON_IRWIN", }, - { XEONMP, "XEONMP", }, - { XEON_POTOMAC, "XEON_POTOMAC", }, - { XEON_I7, "XEON_I7", }, - { XEON_GAINESTOWN, "XEON_GAINESTOWN", }, - { XEON_WESTMERE, "XEON_WESTMERE", }, - - { MOBILE_PENTIUM_M, "MOBILE_PENTIUM_M", }, - { CELERON, "CELERON", }, - { MOBILE_CELERON, "MOBILE_CELERON", }, - { NOT_CELERON, "NOT_CELERON", }, - - { CORE_SOLO, "CORE_SOLO", }, - { MOBILE_CORE_SOLO, "MOBILE_CORE_SOLO", }, - { CORE_DUO, "CORE_DUO", }, - { MOBILE_CORE_DUO, "MOBILE_CORE_DUO", }, - - { WOLFDALE, "WOLFDALE", }, - { MEROM, "MEROM", }, - { PENRYN, "PENRYN", }, - { QUAD_CORE, "QUAD_CORE", }, - { DUAL_CORE_HT, "DUAL_CORE_HT", }, - { QUAD_CORE_HT, "QUAD_CORE_HT", }, - { MORE_THAN_QUADCORE, "MORE_THAN_QUADCORE", }, - { PENTIUM_D, "PENTIUM_D", }, - - { ATOM, "ATOM", }, - { ATOM_SILVERTHORNE, "ATOM_SILVERTHORNE", }, - { ATOM_DIAMONDVILLE, "ATOM_DIAMONDVILLE", }, - { ATOM_PINEVIEW, "ATOM_PINEVIEW", }, - { ATOM_CEDARVIEW, "ATOM_CEDARVIEW", }, - - { CORE_I3, "CORE_I3", }, - { CORE_I5, "CORE_I5", }, - { CORE_I7, "CORE_I7", }, - { CORE_IVY3, "CORE_IVY3", }, - { CORE_IVY5, "CORE_IVY5", }, - { CORE_IVY7, "CORE_IVY7", }, - { CORE_HASWELL3, "CORE_HASWELL3", }, - { CORE_HASWELL5, "CORE_HASWELL5", }, - { CORE_HASWELL7, "CORE_HASWELL7", }, - { CORE_BROADWELL3, "CORE_BROADWELL3", }, - { CORE_BROADWELL5, "CORE_BROADWELL5", }, - { CORE_BROADWELL7, "CORE_BROADWELL7", }, - { CORE_SKYLAKE3, "CORE_SKYLAKE3", }, - { CORE_SKYLAKE5, "CORE_SKYLAKE5", }, - { CORE_SKYLAKE7, "CORE_SKYLAKE7", }, - { NA, "NA", }, + #define CODE(x) { x, #x } + #include "intel_code_t.h" + #undef CODE }; enum _intel_model_t { @@ -866,14 +765,13 @@ int cpuid_identify_intel(struct cpu_raw_data_t* raw, struct cpu_id_t* data) intel_code_t brand_code = get_brand_code(data); intel_model_t model_code = get_model_code(data); - int i = 0; + int i; char* brand_code_str = NULL; - while (intel_bcode_str[i].code != NA) { + for (i = 0; i < COUNT_OF(intel_bcode_str); i++) { if (brand_code == intel_bcode_str[i].code) { brand_code_str = intel_bcode_str[i].str; break; } - i++; } if (brand_code_str) debugf(2, "Detected Intel brand code: %d (%s)\n", brand_code, brand_code_str);