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FFXSR flag supported
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@16 3b4be424-7ac5-41d7-8526-f4ddcb85d872
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3 changed files with 3 additions and 0 deletions
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@ -452,6 +452,7 @@ const char* cpu_feature_str(cpu_feature_t feature)
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{ CPU_FEATURE_3DNOW, "3dnow" },
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{ CPU_FEATURE_3DNOW, "3dnow" },
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{ CPU_FEATURE_3DNOWEXT, "3dnowext" },
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{ CPU_FEATURE_3DNOWEXT, "3dnowext" },
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{ CPU_FEATURE_NX, "nx" },
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{ CPU_FEATURE_NX, "nx" },
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{ CPU_FEATURE_FXSR_OPT, "fxsr_opt" },
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{ CPU_FEATURE_RDTSCP, "rdtscp" },
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{ CPU_FEATURE_RDTSCP, "rdtscp" },
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{ CPU_FEATURE_LM, "lm" },
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{ CPU_FEATURE_LM, "lm" },
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{ CPU_FEATURE_LAHF_LM, "lahf_lm" },
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{ CPU_FEATURE_LAHF_LM, "lahf_lm" },
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@ -281,6 +281,7 @@ enum _cpu_feature_t {
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CPU_FEATURE_3DNOW, /*!< AMD 3DNow! instructions supported */
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CPU_FEATURE_3DNOW, /*!< AMD 3DNow! instructions supported */
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CPU_FEATURE_3DNOWEXT, /*!< AMD 3DNow! extended instructions supported */
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CPU_FEATURE_3DNOWEXT, /*!< AMD 3DNow! extended instructions supported */
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CPU_FEATURE_NX, /*!< No-execute bit supported */
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CPU_FEATURE_NX, /*!< No-execute bit supported */
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CPU_FEATURE_FXSR_OPT, /*!< FFXSR: FXSAVE and FXRSTOR optimizations */
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CPU_FEATURE_RDTSCP, /*!< RDTSCP instruction supported (AMD-only) */
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CPU_FEATURE_RDTSCP, /*!< RDTSCP instruction supported (AMD-only) */
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CPU_FEATURE_LM, /*!< Long mode (x86_64/EM64T) supported */
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CPU_FEATURE_LM, /*!< Long mode (x86_64/EM64T) supported */
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CPU_FEATURE_LAHF_LM, /*!< LAHF/SAHF supported in 64-bit mode */
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CPU_FEATURE_LAHF_LM, /*!< LAHF/SAHF supported in 64-bit mode */
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@ -159,6 +159,7 @@ static void load_amd_features(struct cpu_raw_data_t* raw, struct cpu_id_t* data)
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const struct feature_map_t matchtable_edx81[] = {
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const struct feature_map_t matchtable_edx81[] = {
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{ 20, CPU_FEATURE_NX },
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{ 20, CPU_FEATURE_NX },
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{ 22, CPU_FEATURE_MMXEXT },
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{ 22, CPU_FEATURE_MMXEXT },
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{ 25, CPU_FEATURE_FXSR_OPT },
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{ 27, CPU_FEATURE_RDTSCP },
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{ 27, CPU_FEATURE_RDTSCP },
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{ 30, CPU_FEATURE_3DNOWEXT },
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{ 30, CPU_FEATURE_3DNOWEXT },
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{ 31, CPU_FEATURE_3DNOW },
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{ 31, CPU_FEATURE_3DNOW },
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