From f60666409c139c1184f2228b785e1cabec56b37f Mon Sep 17 00:00:00 2001 From: The Tumultuous Unicorn Of Darkness Date: Mon, 21 Apr 2025 18:21:50 +0200 Subject: [PATCH] DB: fix detection of Intel CPUs prefixed by 'N' or 'U' --- libcpuid/libcpuid_internal.h | 1 + libcpuid/recog_intel.c | 16 ++++++++++++---- 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/libcpuid/libcpuid_internal.h b/libcpuid/libcpuid_internal.h index ab7e41b..50963d9 100644 --- a/libcpuid/libcpuid_internal.h +++ b/libcpuid/libcpuid_internal.h @@ -166,6 +166,7 @@ enum _intel_bits_t { _V = LBIT( (LAST_COMMON_BIT + 20) ), // Lunar Lake _L = LBIT( (LAST_COMMON_BIT + 21) ), // LGA package (UL = Power efficient, in LGA package / HL = Highest performance, in LGA package) _T = LBIT( (LAST_COMMON_BIT + 22) ), // Power-optimized lifestyle + _U_ = LBIT( (LAST_COMMON_BIT + 23) ), }; typedef enum _intel_bits_t intel_bits_t; diff --git a/libcpuid/recog_intel.c b/libcpuid/recog_intel.c index b9b053e..b4aa348 100644 --- a/libcpuid/recog_intel.c +++ b/libcpuid/recog_intel.c @@ -505,13 +505,13 @@ const struct match_entry_t cpudb_intel[] = { { 6, 10, -1, -1, 154, -1, -1, -1, NC, CORE_|_I_|_7|_H|_L, _12xxx, "Alder Lake-PS (Core i7)" }, { 6, 10, -1, -1, 154, -1, -1, -1, NC, CORE_|_I_|_5|_H|_L, _12xxx, "Alder Lake-PS (Core i5)" }, { 6, 10, -1, -1, 154, -1, -1, -1, NC, CORE_|_I_|_3|_H|_L, _12xxx, "Alder Lake-PS (Core i3)" }, - { 6, 14, -1, -1, 190, -1, -1, -1, NC, CORE_|_I_|_3|_N , 0, "Alder Lake-N (Core i3)" }, + { 6, 14, -1, -1, 190, -1, -1, -1, NC, CORE_|_I_|_3|_N_ , 0, "Alder Lake-N (Core i3)" }, /* Core i3 N300 + Core i3 N305 */ { 6, 14, -1, -1, 190, 4, -1, -1, NC, _N_ , 0, "Alder Lake-N (Intel Processor)" }, - { 6, 14, -1, -1, 190, 2, -1, -1, NC, _N_ , 0, "Alder Lake-N (Intel Processor)" }, + { 6, 14, -1, -1, 190, 2, -1, -1, NC, _N_ , 0, "Alder Lake-N (Intel Processor)" }, /* Intel Processor N50 */ { 6, 14, -1, -1, 190, -1, -1, -1, NC, ATOM_ , 0, "Alder Lake-N (Atom)" }, /* Twin Lake CPUs (2025, Intel 7) => https://en.wikichip.org/wiki/intel/microarchitectures/twin_lake */ - { 6, 14, -1, -1, 190, 8, -1, -1, NC, CORE_|_3|_N_ , _x5x, "Twin Lake-N (Core 3)" }, - { 6, 14, -1, -1, 190, 4, -1, -1, NC, _N , _x5x, "Twin Lake-N (Intel Processor)" }, + { 6, 14, -1, -1, 190, 8, -1, -1, NC, CORE_|_3|_N_ , _x5x, "Twin Lake-N (Core 3)" }, /* Core 3 N350 + Core 3 N355 */ + { 6, 14, -1, -1, 190, 4, -1, -1, NC, _N_ , _x5x, "Twin Lake-N (Intel Processor)" }, /* Intel Processor N150 + Intel Processor N150 */ /* Raptor Lake CPUs (2022, 13th Core i gen, Intel 7) => https://en.wikichip.org/wiki/intel/microarchitectures/raptor_lake */ { 6, 15, -1, -1, 191, -1, -1, -1, NC, CORE_|_I_|_5 , _13xxx, "Raptor Lake-S (Core i5)" }, // "Golden Cove" cores @@ -528,6 +528,7 @@ const struct match_entry_t cpudb_intel[] = { { 6, 10, 3, -1, 186, -1, -1, -1, NC, CORE_|_I_|_7|_U , 0, "Raptor Lake-U (Core i7)" }, { 6, 10, 3, -1, 186, -1, -1, -1, NC, CORE_|_I_|_5|_U , 0, "Raptor Lake-U (Core i5)" }, { 6, 10, 3, -1, 186, -1, -1, -1, NC, CORE_|_I_|_3|_U , 0, "Raptor Lake-U (Core i3)" }, + { 6, 10, 3, -1, 186, -1, -1, -1, NC, _U_ , 0, "Raptor Lake-U (Intel Processor)" }, /* Intel Processor U300 */ { 6, 10, -1, -1, 186, -1, -1, -1, NC, CORE_|_I_|_9|_H , _13xxx, "Raptor Lake-H (Core i9)" }, { 6, 10, -1, -1, 186, -1, -1, -1, NC, CORE_|_I_|_7|_H , _13xxx, "Raptor Lake-H (Core i7)" }, { 6, 10, -1, -1, 186, -1, -1, -1, NC, CORE_|_I_|_5|_H , _13xxx, "Raptor Lake-H (Core i5)" }, @@ -889,6 +890,13 @@ static intel_code_and_bits_t get_brand_code_and_bits(struct cpu_id_t* data) case 'W': bits |= _W_; break; } } + else if ((i = match_pattern(bs, "[NU]##")) != 0) { + i--; + switch (bs[i]) { + case 'N': bits |= _N_; break; + case 'U': bits |= _U_; break; + } + } if (((bits & PENTIUM_) || (bits & CELERON_)) && ((i = match_pattern(bs, "[JN]")) != 0)) { i--;