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Code Issues Releases Wiki Activity

Reorganization of CPU databases, added correct recognition of most Core-based Xeons, fixed a few other misrecognitions

Browse source 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@40 3b4be424-7ac5-41d7-8526-f4ddcb85d872
This commit is contained in:
Veselin Georgiev 2008-12-12 18:56:29 +00:00
commit f986629b65
6 changed files with 1014 additions and 346 deletions
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29
libcpuid/libcpuid_util.c
View file

@ -70,34 +70,35 @@ void debugf(int verboselevel, const char* format, ...)
_warn_fun(buff);
}
static int score(const struct match_entry_t* entry, int family, int model,
int stepping, int xfamily, int xmodel, int code)
static int score(const struct match_entry_t* entry, const struct cpu_id_t* data,
int brand_code, int model_code)
{
int res = 0;
if (entry->family == family ) res += 2;
if (entry->model == model ) res += 2;
if (entry->stepping == stepping) res += 2;
if (entry->ext_family == xfamily ) res += 2;
if (entry->ext_model == xmodel ) res += 2;
if (entry->code == code ) res += 2;
if (entry->family == data->family ) res++;
if (entry->model == data->model ) res++;
if (entry->stepping == data->stepping ) res++;
if (entry->ext_family == data->ext_family) res++;
if (entry->ext_model == data->ext_model ) res++;
if (entry->ncores == data->num_cores ) res++;
if (entry->l2cache == data->l2_cache ) res++;
if (entry->brand_code == brand_code ) res++;
if (entry->model_code == model_code ) res++;
return res;
}
void match_cpu_codename(const struct match_entry_t* matchtable, int count,
struct cpu_id_t* data, int code)
struct cpu_id_t* data, int brand_code, int model_code)
{
int bestscore = -1;
int bestindex = 0;
int i, t;
debugf(3, "Matching cpu f:%d, m:%d, s:%d, xf:%d, xm:%d, code:%d\n",
debugf(3, "Matching cpu f:%d, m:%d, s:%d, xf:%d, xm:%d, ncore:%d, l2:%d, bcode:%d, code:%d\n",
data->family, data->model, data->stepping, data->ext_family,
data->ext_model, code);
data->ext_model, data->num_cores, data->l2_cache, brand_code, model_code);
for (i = 0; i < count; i++) {
t = score(&matchtable[i], data->family, data->model,
data->stepping, data->ext_family,
data->ext_model, code);
t = score(&matchtable[i], data, brand_code, model_code);
debugf(3, "Entry %d, `%s', score %d\n", i, matchtable[i].name, t);
if (t > bestscore) {
debugf(2, "Entry `%s' selected - best score so far (%d)\n", matchtable[i].name, t);

4
libcpuid/libcpuid_util.h
View file

@ -38,12 +38,12 @@ void match_features(const struct feature_map_t* matchtable, int count,
struct match_entry_t {
int family, model, stepping, ext_family, ext_model;
int code;
int ncores, l2cache, brand_code, model_code;
char name[32];
};
void match_cpu_codename(const struct match_entry_t* matchtable, int count,
struct cpu_id_t* data, int code);
struct cpu_id_t* data, int brand_code, int model_code);
void warnf(const char* format, ...)
#ifdef __GNUC__

283
libcpuid/recog_amd.c
View file

@ -36,7 +36,6 @@ enum _amd_code_t {
OPTERON_GENERIC,
OPTERON_800,
ATHLON_XP,
ATHLON_XP_BARTON,
ATHLON_XP_M,
ATHLON_XP_M_LV,
ATHLON,
@ -46,163 +45,150 @@ enum _amd_code_t {
DURON,
DURON_MP,
MOBILE_DURON,
SEMPRON,
MOBILE_SEMPRON,
OPTERON_SINGLE,
OPTERON_DUALCORE,
OPTERON_800_DUALCORE,
MOBILE_TURION,
ATHLON_64_512K,
ATHLON_64_1M,
ATHLON_64_X2_512K,
ATHLON_64_X2_1M,
ATHLON_64,
ATHLON_64_X2,
ATHLON_64_FX,
TURION_64_512K,
TURION_64_1M,
TURION_X2_512K,
TURION_X2_1M,
SEMPRON_64_128K,
SEMPRON_64_256K,
SEMPRON_64_512K,
M_SEMPRON_64_256K,
M_SEMPRON_64_512K,
TURION_64,
TURION_X2,
SEMPRON,
M_SEMPRON,
SEMPRON_DUALCORE,
PHENOM,
PHENOM_X2,
PHENOM_X3,
PHENOM_X4,
};
typedef enum _amd_code_t amd_code_t;
const struct match_entry_t cpudb_amd[] = {
{ -1, -1, -1, -1, -1, NO_CODE , "Unknown AMD CPU" },
{ -1, -1, -1, -1, -1, 1, -1, NO_CODE , 0, "Unknown AMD CPU" },
/* 486 and the likes */
{ 4, -1, -1, -1, -1, NO_CODE , "Unknown AMD 486" },
{ 4, 3, -1, -1, -1, NO_CODE , "AMD 486DX2" },
{ 4, 7, -1, -1, -1, NO_CODE , "AMD 486DX2WB" },
{ 4, 8, -1, -1, -1, NO_CODE , "AMD 486DX4" },
{ 4, 9, -1, -1, -1, NO_CODE , "AMD 486DX4WB" },
{ 4, -1, -1, -1, -1, 1, -1, NO_CODE , 0, "Unknown AMD 486" },
{ 4, 3, -1, -1, -1, 1, -1, NO_CODE , 0, "AMD 486DX2" },
{ 4, 7, -1, -1, -1, 1, -1, NO_CODE , 0, "AMD 486DX2WB" },
{ 4, 8, -1, -1, -1, 1, -1, NO_CODE , 0, "AMD 486DX4" },
{ 4, 9, -1, -1, -1, 1, -1, NO_CODE , 0, "AMD 486DX4WB" },
/* Pentia clones */
{ 5, -1, -1, -1, -1, NO_CODE , "Unknown AMD 586" },
{ 5, 0, -1, -1, -1, NO_CODE , "K5" },
{ 5, 1, -1, -1, -1, NO_CODE , "K5" },
{ 5, 2, -1, -1, -1, NO_CODE , "K5" },
{ 5, 3, -1, -1, -1, NO_CODE , "K5" },
{ 5, -1, -1, -1, -1, 1, -1, NO_CODE , 0, "Unknown AMD 586" },
{ 5, 0, -1, -1, -1, 1, -1, NO_CODE , 0, "K5" },
{ 5, 1, -1, -1, -1, 1, -1, NO_CODE , 0, "K5" },
{ 5, 2, -1, -1, -1, 1, -1, NO_CODE , 0, "K5" },
{ 5, 3, -1, -1, -1, 1, -1, NO_CODE , 0, "K5" },
/* The K6 */
{ 5, 6, -1, -1, -1, NO_CODE , "K6" },
{ 5, 7, -1, -1, -1, NO_CODE , "K6" },
{ 5, 6, -1, -1, -1, 1, -1, NO_CODE , 0, "K6" },
{ 5, 7, -1, -1, -1, 1, -1, NO_CODE , 0, "K6" },
{ 5, 8, -1, -1, -1, NO_CODE , "K6-2" },
{ 5, 9, -1, -1, -1, NO_CODE , "K6-III" },
{ 5, 10, -1, -1, -1, NO_CODE , "Unknown K6" },
{ 5, 11, -1, -1, -1, NO_CODE , "Unknown K6" },
{ 5, 12, -1, -1, -1, NO_CODE , "Unknown K6" },
{ 5, 13, -1, -1, -1, NO_CODE , "K6-2+" },
{ 5, 8, -1, -1, -1, 1, -1, NO_CODE , 0, "K6-2" },
{ 5, 9, -1, -1, -1, 1, -1, NO_CODE , 0, "K6-III" },
{ 5, 10, -1, -1, -1, 1, -1, NO_CODE , 0, "Unknown K6" },
{ 5, 11, -1, -1, -1, 1, -1, NO_CODE , 0, "Unknown K6" },
{ 5, 12, -1, -1, -1, 1, -1, NO_CODE , 0, "Unknown K6" },
{ 5, 13, -1, -1, -1, 1, -1, NO_CODE , 0, "K6-2+" },
/* Athlon et al. */
{ 6, 1, -1, -1, -1, NO_CODE , "Athlon (Slot-A)" },
{ 6, 2, -1, -1, -1, NO_CODE , "Athlon (Slot-A)" },
{ 6, 3, -1, -1, -1, NO_CODE , "Duron (Spitfire)" },
{ 6, 4, -1, -1, -1, NO_CODE , "Athlon (ThunderBird)" },
{ 6, 1, -1, -1, -1, 1, -1, NO_CODE , 0, "Athlon (Slot-A)" },
{ 6, 2, -1, -1, -1, 1, -1, NO_CODE , 0, "Athlon (Slot-A)" },
{ 6, 3, -1, -1, -1, 1, -1, NO_CODE , 0, "Duron (Spitfire)" },
{ 6, 4, -1, -1, -1, 1, -1, NO_CODE , 0, "Athlon (ThunderBird)" },
{ 6, 6, -1, -1, -1, NO_CODE , "Unknown Athlon" },
{ 6, 6, -1, -1, -1, ATHLON , "Athlon (Palomino)" },
{ 6, 6, -1, -1, -1, ATHLON_MP , "Athlon MP (Palomino)" },
{ 6, 6, -1, -1, -1, DURON , "Duron (Palomino)" },
{ 6, 6, -1, -1, -1, ATHLON_XP , "Athlon XP" },
{ 6, 6, -1, -1, -1, 1, -1, NO_CODE , 0, "Unknown Athlon" },
{ 6, 6, -1, -1, -1, 1, -1, ATHLON , 0, "Athlon (Palomino)" },
{ 6, 6, -1, -1, -1, 1, -1, ATHLON_MP , 0, "Athlon MP (Palomino)" },
{ 6, 6, -1, -1, -1, 1, -1, DURON , 0, "Duron (Palomino)" },
{ 6, 6, -1, -1, -1, 1, -1, ATHLON_XP , 0, "Athlon XP" },
{ 6, 7, -1, -1, -1, NO_CODE , "Unknown Athlon XP" },
{ 6, 7, -1, -1, -1, DURON , "Duron (Morgan)" },
{ 6, 7, -1, -1, -1, 1, -1, NO_CODE , 0, "Unknown Athlon XP" },
{ 6, 7, -1, -1, -1, 1, -1, DURON , 0, "Duron (Morgan)" },
{ 6, 8, -1, -1, -1, NO_CODE , "Athlon XP" },
{ 6, 8, -1, -1, -1, ATHLON , "Athlon XP" },
{ 6, 8, -1, -1, -1, ATHLON_XP , "Athlon XP" },
{ 6, 8, -1, -1, -1, DURON , "Duron (Applebred)" },
{ 6, 8, -1, -1, -1, SEMPRON , "Sempron (Thoroughbred)" },
{ 6, 8, -1, -1, -1, SEMPRON_64_128K , "Sempron (Thoroughbred)" },
{ 6, 8, -1, -1, -1, SEMPRON_64_256K , "Sempron (Thoroughbred)" },
{ 6, 8, -1, -1, -1, ATHLON_MP , "Athlon MP (Thoroughbred)" },
{ 6, 8, -1, -1, -1, ATHLON_XP_M , "Mobile Athlon (T-Bred)" },
{ 6, 8, -1, -1, -1, ATHLON_XP_M_LV , "Mobile Athlon (T-Bred)" },
{ 6, 8, -1, -1, -1, 1, -1, NO_CODE , 0, "Athlon XP" },
{ 6, 8, -1, -1, -1, 1, -1, ATHLON , 0, "Athlon XP (Thoroughbred)" },
{ 6, 8, -1, -1, -1, 1, -1, ATHLON_XP , 0, "Athlon XP (Thoroughbred)" },
{ 6, 8, -1, -1, -1, 1, -1, DURON , 0, "Duron (Applebred)" },
{ 6, 8, -1, -1, -1, 1, -1, SEMPRON , 0, "Sempron (Thoroughbred)" },
{ 6, 8, -1, -1, -1, 1, 128, SEMPRON , 0, "Sempron (Thoroughbred)" },
{ 6, 8, -1, -1, -1, 1, 256, SEMPRON , 0, "Sempron (Thoroughbred)" },
{ 6, 8, -1, -1, -1, 1, -1, ATHLON_MP , 0, "Athlon MP (Thoroughbred)" },
{ 6, 8, -1, -1, -1, 1, -1, ATHLON_XP_M , 0, "Mobile Athlon (T-Bred)" },
{ 6, 8, -1, -1, -1, 1, -1, ATHLON_XP_M_LV , 0, "Mobile Athlon (T-Bred)" },
{ 6, 10, -1, -1, -1, NO_CODE , "Athlon XP (Barton)" },
{ 6, 10, -1, -1, -1, ATHLON , "Athlon XP (Barton)" },
{ 6, 10, -1, -1, -1, ATHLON_XP_BARTON , "Athlon XP (Barton)" },
{ 6, 10, -1, -1, -1, SEMPRON , "Sempron (Barton)" },
{ 6, 10, -1, -1, -1, SEMPRON_64_256K , "Sempron (Barton)" },
{ 6, 10, -1, -1, -1, ATHLON_XP , "Athlon XP" },
/* ^^ Actually, Thorton, but it's equivallent to Thoroughbred */
{ 6, 10, -1, -1, -1, ATHLON_MP , "Athlon MP (Barton)" },
{ 6, 10, -1, -1, -1, ATHLON_XP_M , "Mobile Athlon (Barton)" },
{ 6, 10, -1, -1, -1, ATHLON_XP_M_LV , "Mobile Athlon (Barton)" },
{ 6, 10, -1, -1, -1, 1, -1, NO_CODE , 0, "Athlon XP (Barton)" },
{ 6, 10, -1, -1, -1, 1, 512, ATHLON_XP , 0, "Athlon XP (Barton)" },
{ 6, 10, -1, -1, -1, 1, 512, SEMPRON , 0, "Sempron (Barton)" },
{ 6, 10, -1, -1, -1, 1, 256, SEMPRON , 0, "Sempron (Thorton)" },
{ 6, 10, -1, -1, -1, 1, 256, ATHLON_XP , 0, "Athlon XP (Thorton)" },
{ 6, 10, -1, -1, -1, 1, -1, ATHLON_MP , 0, "Athlon MP (Barton)" },
{ 6, 10, -1, -1, -1, 1, -1, ATHLON_XP_M , 0, "Mobile Athlon (Barton)" },
{ 6, 10, -1, -1, -1, 1, -1, ATHLON_XP_M_LV , 0, "Mobile Athlon (Barton)" },
/* K8 Architecture */
{ 15, -1, -1, 15, -1, NO_CODE , "Unknown K8" },
{ 15, -1, -1, 16, -1, NO_CODE , "Unknown K9" },
{ 15, -1, -1, 15, -1, 1, -1, NO_CODE , 0, "Unknown K8" },
{ 15, -1, -1, 16, -1, 1, -1, NO_CODE , 0, "Unknown K9" },
{ 15, -1, -1, 15, -1, NO_CODE , "Unknown A64" },
{ 15, -1, -1, 15, -1, OPTERON_SINGLE , "Opteron" },
{ 15, -1, -1, 15, -1, OPTERON_DUALCORE , "Opteron (Dual Core)" },
{ 15, 3, -1, 15, -1, OPTERON_SINGLE , "Opteron" },
{ 15, 3, -1, 15, -1, OPTERON_DUALCORE , "Opteron (Dual Core)" },
{ 15, -1, -1, 15, -1, ATHLON_64_512K , "Athlon 64 (512K)" },
{ 15, -1, -1, 15, -1, ATHLON_64_1M , "Athlon 64 (1024K)" },
{ 15, -1, -1, 15, -1, ATHLON_FX , "Athlon FX" },
{ 15, -1, -1, 15, -1, ATHLON_64_FX , "Athlon 64 FX" },
{ 15, -1, -1, 15, -1, ATHLON_64_X2_512K , "Athlon 64 X2 (512K)" },
{ 15, -1, -1, 15, -1, ATHLON_64_X2_1M , "Athlon 64 X2 (1024K)" },
{ 15, -1, -1, 15, -1, TURION_64_512K , "Turion 64 (512K)" },
{ 15, -1, -1, 15, -1, TURION_64_1M , "Turion 64 (1024K)" },
{ 15, -1, -1, 15, -1, TURION_X2_512K , "Turion 64 X2 (512K)" },
{ 15, -1, -1, 15, -1, TURION_X2_1M , "Turion 64 X2 (1024K)" },
{ 15, -1, -1, 15, -1, SEMPRON_64_128K , "A64 Sempron (128K)" },
{ 15, -1, -1, 15, -1, SEMPRON_64_256K , "A64 Sempron (256K)" },
{ 15, -1, -1, 15, -1, SEMPRON_64_512K , "A64 Sempron (512K)" },
{ 15, -1, -1, 15, 0x4f, ATHLON_64_512K , "Athlon 64 (Orleans/512K)" },
{ 15, -1, -1, 15, 0x5f, ATHLON_64_512K , "Athlon 64 (Orleans/512K)" },
{ 15, -1, -1, 15, 0x2f, ATHLON_64_512K , "Athlon 64 (Venice/512K)" },
{ 15, -1, -1, 15, 0x2c, ATHLON_64_512K , "Athlon 64 (Venice/512K)" },
{ 15, -1, -1, 15, 0x1f, ATHLON_64_512K , "Athlon 64 (Winchester/512K)" },
{ 15, -1, -1, 15, 0x0c, ATHLON_64_512K , "Athlon 64 (Newcastle/512K)" },
{ 15, -1, -1, 15, 0x27, ATHLON_64_512K , "Athlon 64 (San Diego/512K)" },
{ 15, -1, -1, 15, 0x37, ATHLON_64_512K , "Athlon 64 (San Diego/512K)" },
{ 15, -1, -1, 15, 0x04, ATHLON_64_512K , "Athlon 64 (ClawHammer/512K)" },
{ 15, -1, -1, 15, -1, 1, -1, NO_CODE , 0, "Unknown A64" },
{ 15, -1, -1, 15, -1, 1, -1, OPTERON_SINGLE , 0, "Opteron" },
{ 15, -1, -1, 15, -1, 2, -1, OPTERON_DUALCORE , 0, "Opteron (Dual Core)" },
{ 15, 3, -1, 15, -1, 1, -1, OPTERON_SINGLE , 0, "Opteron" },
{ 15, 3, -1, 15, -1, 2, -1, OPTERON_DUALCORE , 0, "Opteron (Dual Core)" },
{ 15, -1, -1, 15, -1, 1, 512, ATHLON_64 , 0, "Athlon 64 (512K)" },
{ 15, -1, -1, 15, -1, 1, 1024, ATHLON_64 , 0, "Athlon 64 (1024K)" },
{ 15, -1, -1, 15, -1, 1, -1, ATHLON_FX , 0, "Athlon FX" },
{ 15, -1, -1, 15, -1, 1, -1, ATHLON_64_FX , 0, "Athlon 64 FX" },
{ 15, -1, -1, 15, -1, 2, 512, ATHLON_64_X2 , 0, "Athlon 64 X2 (512K)" },
{ 15, -1, -1, 15, -1, 2, 1024, ATHLON_64_X2 , 0, "Athlon 64 X2 (1024K)" },
{ 15, -1, -1, 15, -1, 1, 512, TURION_64 , 0, "Turion 64 (512K)" },
{ 15, -1, -1, 15, -1, 1, 1024, TURION_64 , 0, "Turion 64 (1024K)" },
{ 15, -1, -1, 15, -1, 2, 512, TURION_X2 , 0, "Turion 64 X2 (512K)" },
{ 15, -1, -1, 15, -1, 2, 1024, TURION_X2 , 0, "Turion 64 X2 (1024K)" },
{ 15, -1, -1, 15, -1, 1, 128, SEMPRON , 0, "A64 Sempron (128K)" },
{ 15, -1, -1, 15, -1, 1, 256, SEMPRON , 0, "A64 Sempron (256K)" },
{ 15, -1, -1, 15, -1, 1, 512, SEMPRON , 0, "A64 Sempron (512K)" },
{ 15, -1, -1, 15, 0x4f, 1, 512, ATHLON_64 , 0, "Athlon 64 (Orleans/512K)" },
{ 15, -1, -1, 15, 0x5f, 1, 512, ATHLON_64 , 0, "Athlon 64 (Orleans/512K)" },
{ 15, -1, -1, 15, 0x2f, 1, 512, ATHLON_64 , 0, "Athlon 64 (Venice/512K)" },
{ 15, -1, -1, 15, 0x2c, 1, 512, ATHLON_64 , 0, "Athlon 64 (Venice/512K)" },
{ 15, -1, -1, 15, 0x1f, 1, 512, ATHLON_64 , 0, "Athlon 64 (Winchester/512K)" },
{ 15, -1, -1, 15, 0x0c, 1, 512, ATHLON_64 , 0, "Athlon 64 (Newcastle/512K)" },
{ 15, -1, -1, 15, 0x27, 1, 512, ATHLON_64 , 0, "Athlon 64 (San Diego/512K)" },
{ 15, -1, -1, 15, 0x37, 1, 512, ATHLON_64 , 0, "Athlon 64 (San Diego/512K)" },
{ 15, -1, -1, 15, 0x04, 1, 512, ATHLON_64 , 0, "Athlon 64 (ClawHammer/512K)" },
{ 15, -1, -1, 15, 0x5f, ATHLON_64_1M , "Athlon 64 (Orleans/1024K)" },
{ 15, -1, -1, 15, 0x27, ATHLON_64_1M , "Athlon 64 (San Diego/1024K)" },
{ 15, -1, -1, 15, 0x04, ATHLON_64_1M , "Athlon 64 (ClawHammer/1024K)" },
{ 15, -1, -1, 15, 0x5f, 1, 1024, ATHLON_64 , 0, "Athlon 64 (Orleans/1024K)" },
{ 15, -1, -1, 15, 0x27, 1, 1024, ATHLON_64 , 0, "Athlon 64 (San Diego/1024K)" },
{ 15, -1, -1, 15, 0x04, 1, 1024, ATHLON_64 , 0, "Athlon 64 (ClawHammer/1024K)" },
{ 15, -1, -1, 15, 0x4b, SEMPRON_DUALCORE , "Athlon 64 X2 (Windsor/256K)" },
{ 15, -1, -1, 15, 0x4b, 2, 256, SEMPRON_DUALCORE , 0, "Athlon 64 X2 (Windsor/256K)" },
{ 15, -1, -1, 15, 0x23, ATHLON_64_X2_512K , "Athlon 64 X2 (Toledo/512K)" },
{ 15, -1, -1, 15, 0x4b, ATHLON_64_X2_512K , "Athlon 64 X2 (Windsor/512K)" },
{ 15, -1, -1, 15, 0x43, ATHLON_64_X2_512K , "Athlon 64 X2 (Windsor/512K)" },
{ 15, -1, -1, 15, 0x6b, ATHLON_64_X2_512K , "Athlon 64 X2 (Brisbane/512K)" },
{ 15, -1, -1, 15, 0x2b, ATHLON_64_X2_512K , "Athlon 64 X2 (Manchester/512K)"},
{ 15, -1, -1, 15, 0x23, 2, 512, ATHLON_64_X2 , 0, "Athlon 64 X2 (Toledo/512K)" },
{ 15, -1, -1, 15, 0x4b, 2, 512, ATHLON_64_X2 , 0, "Athlon 64 X2 (Windsor/512K)" },
{ 15, -1, -1, 15, 0x43, 2, 512, ATHLON_64_X2 , 0, "Athlon 64 X2 (Windsor/512K)" },
{ 15, -1, -1, 15, 0x6b, 2, 512, ATHLON_64_X2 , 0, "Athlon 64 X2 (Brisbane/512K)" },
{ 15, -1, -1, 15, 0x2b, 2, 512, ATHLON_64_X2 , 0, "Athlon 64 X2 (Manchester/512K)"},
{ 15, -1, -1, 15, 0x23, ATHLON_64_X2_1M , "Athlon 64 X2 (Toledo/1024K)" },
{ 15, -1, -1, 15, 0x43, ATHLON_64_X2_1M , "Athlon 64 X2 (Windsor/1024K)" },
{ 15, -1, -1, 15, 0x23, 2, 1024, ATHLON_64_X2 , 0, "Athlon 64 X2 (Toledo/1024K)" },
{ 15, -1, -1, 15, 0x43, 2, 1024, ATHLON_64_X2 , 0, "Athlon 64 X2 (Windsor/1024K)" },
{ 15, -1, -1, 15, 0x2c, SEMPRON_64_128K , "Sempron 64 (Palermo/128K)" },
{ 15, -1, -1, 15, 0x2c, SEMPRON_64_256K , "Sempron 64 (Palermo/256K)" },
{ 15, -1, -1, 15, 0x2f, SEMPRON_64_128K , "Sempron 64 (Palermo/128K)" },
{ 15, -1, -1, 15, 0x2f, SEMPRON_64_256K , "Sempron 64 (Palermo/256K)" },
{ 15, -1, -1, 15, 0x4f, SEMPRON_64_128K , "Sempron 64 (Manila/128K)" },
{ 15, -1, -1, 15, 0x4f, SEMPRON_64_256K , "Sempron 64 (Manila/256K)" },
{ 15, -1, -1, 15, 0x7f, SEMPRON_64_256K , "Sempron 64 (Sparta/256K)" },
{ 15, -1, -1, 15, 0x7f, SEMPRON_64_512K , "Sempron 64 (Sparta/512K)" },
{ 15, -1, -1, 15, -1, M_SEMPRON_64_256K , "Mobile Sempron 64 (Keene/256K)"},
{ 15, -1, -1, 15, -1, M_SEMPRON_64_512K , "Mobile Sempron 64 (Keene/512K)"},
{ 15, -1, -1, 15, -1, SEMPRON_DUALCORE , "Sempron Dual Core" },
{ 15, -1, -1, 15, 0x2c, 1, 128, SEMPRON , 0, "Sempron 64 (Palermo/128K)" },
{ 15, -1, -1, 15, 0x2c, 1, 256, SEMPRON , 0, "Sempron 64 (Palermo/256K)" },
{ 15, -1, -1, 15, 0x2f, 1, 128, SEMPRON , 0, "Sempron 64 (Palermo/128K)" },
{ 15, -1, -1, 15, 0x2f, 1, 256, SEMPRON , 0, "Sempron 64 (Palermo/256K)" },
{ 15, -1, -1, 15, 0x4f, 1, 128, SEMPRON , 0, "Sempron 64 (Manila/128K)" },
{ 15, -1, -1, 15, 0x4f, 1, 256, SEMPRON , 0, "Sempron 64 (Manila/256K)" },
{ 15, -1, -1, 15, 0x7f, 1, 256, SEMPRON , 0, "Sempron 64 (Sparta/256K)" },
{ 15, -1, -1, 15, 0x7f, 1, 512, SEMPRON , 0, "Sempron 64 (Sparta/512K)" },
{ 15, -1, -1, 15, -1, 1, 256, M_SEMPRON , 0, "Mobile Sempron 64 (Keene/256K)"},
{ 15, -1, -1, 15, -1, 1, 512, M_SEMPRON , 0, "Mobile Sempron 64 (Keene/512K)"},
{ 15, -1, -1, 15, -1, 2, -1, SEMPRON_DUALCORE , 0, "Sempron Dual Core" },
/* K9 Architecture */
{ 15, -1, -1, 16, -1, PHENOM , "Unknown AMD Phenom" },
{ 15, 2, -1, 16, -1, PHENOM , "Phenom" },
{ 15, 2, -1, 16, -1, PHENOM_X3 , "Phenom X3 (Toliman)" },
{ 15, 2, -1, 16, -1, PHENOM_X4 , "Phenom X4 (Agena)" },
{ 15, -1, -1, 16, -1, 1, -1, PHENOM , 0, "Unknown AMD Phenom" },
{ 15, 2, -1, 16, -1, 1, -1, PHENOM , 0, "Phenom" },
{ 15, 2, -1, 16, -1, 3, -1, PHENOM , 0, "Phenom X3 (Toliman)" },
{ 15, 2, -1, 16, -1, 4, -1, PHENOM , 0, "Phenom X4 (Agena)" },
};
@ -315,30 +301,30 @@ static amd_code_t decode_amd_codename_part1(const char *bs)
if (strstr(bs, "Athlon(tm) 64 FX")) return ATHLON_64_FX;
if (strstr(bs, "Athlon(tm) FX")) return ATHLON_FX;
if (strstr(bs, "Athlon(tm) 64")) {
if (strstr(bs, "Dual Core")) return ATHLON_64_X2_512K;
return ATHLON_64_512K;
if (strstr(bs, "Dual Core")) return ATHLON_64_X2;
return ATHLON_64;
}
if (strstr(bs, "Athlon(tm) X2")) {
return ATHLON_64_X2_512K;
return ATHLON_64_X2;
}
if (strstr(bs, "Turion(tm)")) {
if (strstr(bs, "X2"))
return TURION_X2_512K;
return TURION_X2;
else
return TURION_64_512K;
return TURION_64;
}
if (strstr(bs, "mobile") || strstr(bs, "Mobile")) {
if (strstr(bs, "Athlon(tm) XP-M (LV)")) return ATHLON_XP_M_LV;
if (strstr(bs, "Athlon(tm) XP")) return ATHLON_XP_M;
if (strstr(bs, "Sempron(tm)")) return M_SEMPRON_64_256K;
if (strstr(bs, "Sempron(tm)")) return M_SEMPRON;
if (strstr(bs, "Athlon")) return MOBILE_ATHLON64;
if (strstr(bs, "Duron")) return MOBILE_DURON;
} else {
if (strstr(bs, "Athlon(tm) XP")) return ATHLON_XP;
if (strstr(bs, "Athlon(tm) MP")) return ATHLON_MP;
if (strstr(bs, "Sempron(tm)")) return SEMPRON_64_128K;
if (strstr(bs, "Sempron(tm)")) return SEMPRON;
if (strstr(bs, "Duron")) return DURON;
if (strstr(bs, "Athlon")) return ATHLON;
}
@ -350,42 +336,9 @@ static void decode_amd_codename(struct cpu_raw_data_t* raw, struct cpu_id_t* dat
{
amd_code_t code = decode_amd_codename_part1(data->brand_str);
if (code == ATHLON_XP && data->l2_cache == 512)
code = ATHLON_XP_BARTON;
if (code == ATHLON_64_512K && data->l2_cache > 512)
code = ATHLON_64_1M;
if (code == SEMPRON_64_128K && data->l2_cache > 128) {
if (data->l2_cache == 256)
code = SEMPRON_64_256K;
else
code = SEMPRON_64_512K;
}
if (code == M_SEMPRON_64_256K && data->l2_cache > 256)
code = M_SEMPRON_64_512K;
if (code == TURION_64_512K && data->l2_cache > 512)
code = TURION_64_1M;
if (code == TURION_X2_512K && data->l2_cache > 512)
code = TURION_X2_1M;
if (code == ATHLON_64_X2_512K && data->l2_cache > 512)
code = ATHLON_64_X2_1M;
if (code == ATHLON_64_X2_512K && data->l2_cache < 512)
if (code == ATHLON_64_X2 && data->l2_cache < 512)
code = SEMPRON_DUALCORE;
if (code == PHENOM) {
switch (data->num_cores) {
case 2:
code = PHENOM_X2;
break;
case 3:
code = PHENOM_X3;
break;
case 4:
code = PHENOM_X4;
break;
default:
break;
}
}
match_cpu_codename(cpudb_amd, COUNT_OF(cpudb_amd), data, code);
match_cpu_codename(cpudb_amd, COUNT_OF(cpudb_amd), data, code, 0);
}
int cpuid_identify_amd(struct cpu_raw_data_t* raw, struct cpu_id_t* data)

377
libcpuid/recog_intel.c
View file

@ -24,6 +24,7 @@
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <string.h>
#include <ctype.h>
#include "libcpuid.h"
#include "recog_intel.h"
#include "libcpuid_util.h"
@ -46,17 +47,9 @@ enum _intel_code_t {
MOBILE_CORE_SOLO,
CORE_DUO,
MOBILE_CORE_DUO,
CORE_DUO_512K,
CORE_DUO_1024K,
ALLENDALE,
WOLFDALE_2M,
WOLFDALE_3M,
WOLFDALE_6M,
MEROM_2M,
MEROM_4M,
PENRYN_3M,
PENRYN_6M,
PENRYN_QUAD,
WOLFDALE,
MEROM,
PENRYN,
QUAD_CORE,
DUAL_CORE_HT,
QUAD_CORE_HT,
@ -68,173 +61,199 @@ enum _intel_code_t {
};
typedef enum _intel_code_t intel_code_t;
enum _intel_model_t {
UNKNOWN = -1,
_3000 = 100,
_3100,
_3200,
X3200,
_3300,
X3300,
_5100,
_5200,
_5300,
_5400,
};
typedef enum _intel_model_t intel_model_t;
const struct match_entry_t cpudb_intel[] = {
{ -1, -1, -1, -1, -1, NO_CODE , "Unknown Intel CPU" },
{ -1, -1, -1, -1, -1, 1, -1, NO_CODE , 0, "Unknown Intel CPU" },
/* i486 */
{ 4, -1, -1, -1, -1, NO_CODE , "Unknown i486" },
{ 4, 0, -1, -1, -1, NO_CODE , "i486 DX-25/33" },
{ 4, 1, -1, -1, -1, NO_CODE , "i486 DX-50" },
{ 4, 2, -1, -1, -1, NO_CODE , "i486 SX" },
{ 4, 3, -1, -1, -1, NO_CODE , "i486 DX2" },
{ 4, 4, -1, -1, -1, NO_CODE , "i486 SL" },
{ 4, 5, -1, -1, -1, NO_CODE , "i486 SX2" },
{ 4, 7, -1, -1, -1, NO_CODE , "i486 DX2 WriteBack" },
{ 4, 8, -1, -1, -1, NO_CODE , "i486 DX4" },
{ 4, 9, -1, -1, -1, NO_CODE , "i486 DX4 WriteBack" },
{ 4, -1, -1, -1, -1, 1, -1, NO_CODE , 0, "Unknown i486" },
{ 4, 0, -1, -1, -1, 1, -1, NO_CODE , 0, "i486 DX-25/33" },
{ 4, 1, -1, -1, -1, 1, -1, NO_CODE , 0, "i486 DX-50" },
{ 4, 2, -1, -1, -1, 1, -1, NO_CODE , 0, "i486 SX" },
{ 4, 3, -1, -1, -1, 1, -1, NO_CODE , 0, "i486 DX2" },
{ 4, 4, -1, -1, -1, 1, -1, NO_CODE , 0, "i486 SL" },
{ 4, 5, -1, -1, -1, 1, -1, NO_CODE , 0, "i486 SX2" },
{ 4, 7, -1, -1, -1, 1, -1, NO_CODE , 0, "i486 DX2 WriteBack" },
{ 4, 8, -1, -1, -1, 1, -1, NO_CODE , 0, "i486 DX4" },
{ 4, 9, -1, -1, -1, 1, -1, NO_CODE , 0, "i486 DX4 WriteBack" },
/* All Pentia:
Pentium 1 */
{ 5, -1, -1, -1, -1, NO_CODE , "Unknown Pentium" },
{ 5, 0, -1, -1, -1, NO_CODE , "Pentium A-Step" },
{ 5, 1, -1, -1, -1, NO_CODE , "Pentium 1 (0.8u)" },
{ 5, 2, -1, -1, -1, NO_CODE , "Pentium 1 (0.35u)" },
{ 5, 3, -1, -1, -1, NO_CODE , "Pentium OverDrive" },
{ 5, 4, -1, -1, -1, NO_CODE , "Pentium 1 (0.35u)" },
{ 5, 7, -1, -1, -1, NO_CODE , "Pentium 1 (0.35u)" },
{ 5, 8, -1, -1, -1, NO_CODE , "Pentium MMX (0.25u)" },
{ 5, -1, -1, -1, -1, 1, -1, NO_CODE , 0, "Unknown Pentium" },
{ 5, 0, -1, -1, -1, 1, -1, NO_CODE , 0, "Pentium A-Step" },
{ 5, 1, -1, -1, -1, 1, -1, NO_CODE , 0, "Pentium 1 (0.8u)" },
{ 5, 2, -1, -1, -1, 1, -1, NO_CODE , 0, "Pentium 1 (0.35u)" },
{ 5, 3, -1, -1, -1, 1, -1, NO_CODE , 0, "Pentium OverDrive" },
{ 5, 4, -1, -1, -1, 1, -1, NO_CODE , 0, "Pentium 1 (0.35u)" },
{ 5, 7, -1, -1, -1, 1, -1, NO_CODE , 0, "Pentium 1 (0.35u)" },
{ 5, 8, -1, -1, -1, 1, -1, NO_CODE , 0, "Pentium MMX (0.25u)" },
/* Pentium 2 / 3 / M / Conroe / whatsnext - all P6 based. */
{ 6, -1, -1, -1, -1, NO_CODE , "Unknown P6" },
{ 6, 0, -1, -1, -1, NO_CODE , "Pentium Pro" },
{ 6, 1, -1, -1, -1, NO_CODE , "Pentium Pro" },
{ 6, 3, -1, -1, -1, NO_CODE , "Pentium II (Klamath)" },
{ 6, 5, -1, -1, -1, NO_CODE , "Pentium II (Deschutes)" },
{ 6, 6, -1, -1, -1, NO_CODE , "Pentium II (Dixon)" },
{ 6, -1, -1, -1, -1, 1, -1, NO_CODE , 0, "Unknown P6" },
{ 6, 0, -1, -1, -1, 1, -1, NO_CODE , 0, "Pentium Pro" },
{ 6, 1, -1, -1, -1, 1, -1, NO_CODE , 0, "Pentium Pro" },
{ 6, 3, -1, -1, -1, 1, -1, NO_CODE , 0, "Pentium II (Klamath)" },
{ 6, 5, -1, -1, -1, 1, -1, NO_CODE , 0, "Pentium II (Deschutes)" },
{ 6, 6, -1, -1, -1, 1, -1, NO_CODE , 0, "Pentium II (Dixon)" },
{ 6, 3, -1, -1, -1, XEON , "P-II Xeon" },
{ 6, 5, -1, -1, -1, XEON , "P-II Xeon" },
{ 6, 6, -1, -1, -1, XEON , "P-II Xeon" },
{ 6, 3, -1, -1, -1, 1, -1, XEON , 0, "P-II Xeon" },
{ 6, 5, -1, -1, -1, 1, -1, XEON , 0, "P-II Xeon" },
{ 6, 6, -1, -1, -1, 1, -1, XEON , 0, "P-II Xeon" },
{ 6, 5, -1, -1, -1, CELERON , "P-II Celeron (no L2)" },
{ 6, 6, -1, -1, -1, CELERON , "P-II Celeron (128K)" },
{ 6, 5, -1, -1, -1, 1, -1, CELERON , 0, "P-II Celeron (no L2)" },
{ 6, 6, -1, -1, -1, 1, -1, CELERON , 0, "P-II Celeron (128K)" },
/* -------------------------------------------------- */
{ 6, 7, -1, -1, -1, NO_CODE , "Pentium III (Katmai)" },
{ 6, 8, -1, -1, -1, NO_CODE , "Pentium III (Coppermine)"},
{ 6, 10, -1, -1, -1, NO_CODE , "Pentium III (Coppermine)"},
{ 6, 11, -1, -1, -1, NO_CODE , "Pentium III (Tualatin)" },
{ 6, 7, -1, -1, -1, 1, -1, NO_CODE , 0, "Pentium III (Katmai)" },
{ 6, 8, -1, -1, -1, 1, -1, NO_CODE , 0, "Pentium III (Coppermine)"},
{ 6, 10, -1, -1, -1, 1, -1, NO_CODE , 0, "Pentium III (Coppermine)"},
{ 6, 11, -1, -1, -1, 1, -1, NO_CODE , 0, "Pentium III (Tualatin)" },
{ 6, 7, -1, -1, -1, XEON , "P-III Xeon" },
{ 6, 8, -1, -1, -1, XEON , "P-III Xeon" },
{ 6, 10, -1, -1, -1, XEON , "P-III Xeon" },
{ 6, 11, -1, -1, -1, XEON , "P-III Xeon" },
{ 6, 7, -1, -1, -1, 1, -1, XEON , 0, "P-III Xeon" },
{ 6, 8, -1, -1, -1, 1, -1, XEON , 0, "P-III Xeon" },
{ 6, 10, -1, -1, -1, 1, -1, XEON , 0, "P-III Xeon" },
{ 6, 11, -1, -1, -1, 1, -1, XEON , 0, "P-III Xeon" },
{ 6, 7, -1, -1, -1, CELERON , "P-III Celeron" },
{ 6, 8, -1, -1, -1, CELERON , "P-III Celeron" },
{ 6, 10, -1, -1, -1, CELERON , "P-III Celeron" },
{ 6, 11, -1, -1, -1, CELERON , "P-III Celeron" },
{ 6, 7, -1, -1, -1, 1, -1, CELERON , 0, "P-III Celeron" },
{ 6, 8, -1, -1, -1, 1, -1, CELERON , 0, "P-III Celeron" },
{ 6, 10, -1, -1, -1, 1, -1, CELERON , 0, "P-III Celeron" },
{ 6, 11, -1, -1, -1, 1, -1, CELERON , 0, "P-III Celeron" },
/* -------------------------------------------------- */
{ 6, 9, -1, -1, -1, NO_CODE , "Unknown Pentium M" },
{ 6, 9, -1, -1, -1, MOBILE_PENTIUM_M , "Unknown Pentium M" },
{ 6, 9, -1, -1, -1, PENTIUM , "Pentium M (Banias)" },
{ 6, 9, -1, -1, -1, MOBILE_PENTIUM_M , "Pentium M (Banias)" },
{ 6, 9, -1, -1, -1, CELERON , "Celeron M" },
{ 6, 13, -1, -1, -1, PENTIUM , "Pentium M (Dothan)" },
{ 6, 13, -1, -1, -1, MOBILE_PENTIUM_M , "Pentium M (Dothan)" },
{ 6, 13, -1, -1, -1, CELERON , "Celeron M" },
{ 6, 9, -1, -1, -1, 1, -1, NO_CODE , 0, "Unknown Pentium M" },
{ 6, 9, -1, -1, -1, 1, -1, MOBILE_PENTIUM_M , 0, "Unknown Pentium M" },
{ 6, 9, -1, -1, -1, 1, -1, PENTIUM , 0, "Pentium M (Banias)" },
{ 6, 9, -1, -1, -1, 1, -1, MOBILE_PENTIUM_M , 0, "Pentium M (Banias)" },
{ 6, 9, -1, -1, -1, 1, -1, CELERON , 0, "Celeron M" },
{ 6, 13, -1, -1, -1, 1, -1, PENTIUM , 0, "Pentium M (Dothan)" },
{ 6, 13, -1, -1, -1, 1, -1, MOBILE_PENTIUM_M , 0, "Pentium M (Dothan)" },
{ 6, 13, -1, -1, -1, 1, -1, CELERON , 0, "Celeron M" },
{ 6, 12, -1, -1, -1, NO_CODE , "Unknown Atom" },
{ 6, 12, -1, -1, -1, ATOM_DIAMONDVILLE , "Atom (Diamondville)" },
{ 6, 12, -1, -1, -1, ATOM_DUALCORE , "Atom Dualcore (Diamondville)" },
{ 6, 12, -1, -1, -1, ATOM_SILVERTHORNE , "Atom (Silverthorne)" },
{ 6, 12, -1, -1, -1, 1, -1, NO_CODE , 0, "Unknown Atom" },
{ 6, 12, -1, -1, -1, 1, -1, ATOM_DIAMONDVILLE , 0, "Atom (Diamondville)" },
{ 6, 12, -1, -1, -1, 1, -1, ATOM_DUALCORE , 0, "Atom Dualcore (Diamondville)" },
{ 6, 12, -1, -1, -1, 1, -1, ATOM_SILVERTHORNE , 0, "Atom (Silverthorne)" },
/* -------------------------------------------------- */
{ 6, 14, -1, -1, -1, NO_CODE , "Unknown Yonah" },
{ 6, 14, -1, -1, -1, CORE_SOLO , "Yonah (Core Solo)" },
{ 6, 14, -1, -1, -1, CORE_DUO , "Yonah (Core Duo)" },
{ 6, 14, -1, -1, -1, MOBILE_CORE_SOLO , "Yonah (Core Solo)" },
{ 6, 14, -1, -1, -1, MOBILE_CORE_DUO , "Yonah (Core Duo)" },
{ 6, 14, -1, -1, -1, XEON , "Xeon LV" },
{ 6, 14, -1, -1, -1, CORE_SOLO , "Yonah (Core Solo)" },
{ 6, 14, -1, -1, -1, 1, -1, NO_CODE , 0, "Unknown Yonah" },
{ 6, 14, -1, -1, -1, 1, -1, CORE_SOLO , 0, "Yonah (Core Solo)" },
{ 6, 14, -1, -1, -1, 1, -1, CORE_DUO , 0, "Yonah (Core Duo)" },
{ 6, 14, -1, -1, -1, 1, -1, MOBILE_CORE_SOLO , 0, "Yonah (Core Solo)" },
{ 6, 14, -1, -1, -1, 1, -1, MOBILE_CORE_DUO , 0, "Yonah (Core Duo)" },
{ 6, 14, -1, -1, -1, 1, -1, CORE_SOLO , 0, "Yonah (Core Solo)" },
{ 6, 15, -1, -1, -1, NO_CODE , "Unknown Core 2" },
{ 6, 15, -1, -1, -1, CORE_DUO , "Conroe (Core 2 Duo)" },
{ 6, 15, -1, -1, -1, CORE_DUO_1024K , "Conroe (Core 2 Duo) 1024K" },
{ 6, 15, -1, -1, -1, CORE_DUO_512K , "Conroe (Core 2 Duo) 512K" },
{ 6, 15, -1, -1, -1, QUAD_CORE , "Kentsfield (Core 2 Quad)" },
{ 6, 15, -1, -1, -1, MORE_THAN_QUADCORE, "More than quad-core" },
{ 6, 15, -1, -1, -1, ALLENDALE , "Allendale (Core 2 Duo)" },
{ 6, 15, -1, -1, -1, XEON , "Xeon (Clovertown) Quad" },
{ 6, 15, -1, -1, -1, MOBILE_CORE_DUO , "Merom (Core 2 Duo)" },
{ 6, 15, -1, -1, -1, MEROM_2M , "Merom (Core 2 Duo) 2048K" },
{ 6, 15, -1, -1, -1, MEROM_4M , "Merom (Core 2 Duo) 4096K" },
{ 6, 15, -1, -1, -1, 1, -1, NO_CODE , 0, "Unknown Core 2" },
{ 6, 15, -1, -1, -1, 2, 4096, CORE_DUO , 0, "Conroe (Core 2 Duo)" },
{ 6, 15, -1, -1, -1, 2, 1024, CORE_DUO , 0, "Conroe (Core 2 Duo) 1024K" },
{ 6, 15, -1, -1, -1, 2, 512, CORE_DUO , 0, "Conroe (Core 2 Duo) 512K" },
{ 6, 15, -1, -1, -1, 4, -1, QUAD_CORE , 0, "Kentsfield (Core 2 Quad)" },
{ 6, 15, -1, -1, -1, 400, -1, MORE_THAN_QUADCORE, 0, "More than quad-core" },
{ 6, 15, -1, -1, -1, 2, 2048, CORE_DUO , 0, "Allendale (Core 2 Duo)" },
{ 6, 15, -1, -1, -1, 2, -1, MOBILE_CORE_DUO , 0, "Merom (Core 2 Duo)" },
{ 6, 15, -1, -1, -1, 2, 2048, MEROM , 0, "Merom (Core 2 Duo) 2048K" },
{ 6, 15, -1, -1, -1, 2, 4096, MEROM , 0, "Merom (Core 2 Duo) 4096K" },
{ 6, 15, -1, -1, 15, CELERON , "Conroe-L (Celeron)" },
{ 6, 6, -1, -1, 22, CELERON , "Conroe-L (Celeron)" },
{ 6, 15, -1, -1, 15, 2, -1, CELERON , 0, "Conroe-L (Celeron)" },
{ 6, 6, -1, -1, 22, 2, -1, CELERON , 0, "Conroe-L (Celeron)" },
{ 6, 6, -1, -1, 22, NO_CODE , "Unknown Core ?" },
{ 6, 7, -1, -1, 23, NO_CODE , "Unknown Core ?" },
{ 6, 6, -1, -1, 22, MORE_THAN_QUADCORE, "More than quad-core" },
{ 6, 7, -1, -1, 23, MORE_THAN_QUADCORE, "More than quad-core" },
{ 6, 6, -1, -1, 22, 1, -1, NO_CODE , 0, "Unknown Core ?" },
{ 6, 7, -1, -1, 23, 1, -1, NO_CODE , 0, "Unknown Core ?" },
{ 6, 6, -1, -1, 22, 400, -1, MORE_THAN_QUADCORE, 0, "More than quad-core" },
{ 6, 7, -1, -1, 23, 400, -1, MORE_THAN_QUADCORE, 0, "More than quad-core" },
{ 6, 7, -1, -1, 23, CORE_SOLO , "Unknown Core 45nm" },
{ 6, 7, -1, -1, 23, CORE_DUO , "Unknown Core 45nm" },
{ 6, 7, -1, -1, 23, WOLFDALE_2M , "Wolfdale (Core 2 Duo) 2M" },
{ 6, 7, -1, -1, 23, WOLFDALE_3M , "Wolfdale (Core 2 Duo) 3M" },
{ 6, 7, -1, -1, 23, WOLFDALE_6M , "Wolfdale (Core 2 Duo) 6M" },
{ 6, 7, -1, -1, 23, XEON , "Xeon (Wolfdale)" },
{ 6, 7, -1, -1, 23, MOBILE_CORE_DUO , "Penryn (Core 2 Duo)" },
{ 6, 7, -1, -1, 23, PENRYN_3M , "Penryn (Core 2 Duo) 3M" },
{ 6, 7, -1, -1, 23, PENRYN_6M , "Penryn (Core 2 Duo) 6M" },
{ 6, 7, -1, -1, 23, QUAD_CORE , "Yorkfield (Core 2 Quad)" },
{ 6, 7, -1, -1, 23, 1, -1, CORE_SOLO , 0, "Unknown Core 45nm" },
{ 6, 7, -1, -1, 23, 1, -1, CORE_DUO , 0, "Unknown Core 45nm" },
{ 6, 7, -1, -1, 23, 2, 2048, WOLFDALE , 0, "Wolfdale (Core 2 Duo) 2M" },
{ 6, 7, -1, -1, 23, 2, 3072, WOLFDALE , 0, "Wolfdale (Core 2 Duo) 3M" },
{ 6, 7, -1, -1, 23, 2, 6144, WOLFDALE , 0, "Wolfdale (Core 2 Duo) 6M" },
{ 6, 7, -1, -1, 23, 1, -1, MOBILE_CORE_DUO , 0, "Penryn (Core 2 Duo)" },
{ 6, 7, -1, -1, 23, 2, 3072, PENRYN , 0, "Penryn (Core 2 Duo) 3M" },
{ 6, 7, -1, -1, 23, 2, 6144, PENRYN , 0, "Penryn (Core 2 Duo) 6M" },
{ 6, 7, -1, -1, 23, 1, 3072, QUAD_CORE , 0, "Yorkfield (Core 2 Quad) 3M"},
{ 6, 7, -1, -1, 23, 1, 6144, QUAD_CORE , 0, "Yorkfield (Core 2 Quad) 6M"},
{ 6, 10, -1, -1, 26, NO_CODE , "Intel Core i7" },
{ 6, 10, -1, -1, 26, QUAD_CORE_HT , "Bloomfield (Core i7)" },
{ 6, 10, -1, -1, 26, 1, -1, NO_CODE , 0, "Intel Core i7" },
{ 6, 10, -1, -1, 26, 4, -1, QUAD_CORE_HT , 0, "Bloomfield (Core i7)" },
/* Core microarchitecture-based Xeons: */
{ 6, 14, -1, -1, 14, 1, -1, XEON , 0, "Xeon LV" },
{ 6, 15, -1, -1, 15, 2, 4096, XEON , _5100, "Xeon (Woodcrest)" },
{ 6, 15, -1, -1, 15, 2, 2048, XEON , _3000, "Xeon (Conroe/2M)" },
{ 6, 15, -1, -1, 15, 2, 4096, XEON , _3000, "Xeon (Conroe/4M)" },
{ 6, 15, -1, -1, 15, 4, 4096, XEON , X3200, "Xeon (Kentsfield)" },
{ 6, 15, -1, -1, 15, 4, 4096, XEON , _5300, "Xeon (Clovertown)" },
{ 6, 7, -1, -1, 23, 2, 6144, XEON , _3100, "Xeon (Wolfdale)" },
{ 6, 7, -1, -1, 23, 2, 6144, XEON , _5200, "Xeon (Wolfdale DP)" },
{ 6, 7, -1, -1, 23, 4, 6144, XEON , _5400, "Xeon (Harpertown)" },
{ 6, 7, -1, -1, 23, 4, 3072, XEON , X3300, "Xeon (Yorkfield/3M)" },
{ 6, 7, -1, -1, 23, 4, 6144, XEON , X3300, "Xeon (Yorkfield/6M)" },
/* Itaniums */
{ 7, -1, -1, -1, -1, NO_CODE , "Itanium" },
{ 15, -1, -1, 16, -1, NO_CODE , "Itanium 2" },
{ 7, -1, -1, -1, -1, 1, -1, NO_CODE , 0, "Itanium" },
{ 15, -1, -1, 16, -1, 1, -1, NO_CODE , 0, "Itanium 2" },
/* Netburst based (Pentium 4 and later)
classic P4s */
{ 15, -1, -1, -1, -1, NO_CODE , "Unknown Pentium 4" },
{ 15, -1, -1, 15, -1, CELERON , "Unknown P-4 Celeron" },
{ 15, -1, -1, 15, -1, XEON , "Unknown Xeon" },
{ 15, -1, -1, -1, -1, 1, -1, NO_CODE , 0, "Unknown Pentium 4" },
{ 15, -1, -1, 15, -1, 1, -1, CELERON , 0, "Unknown P-4 Celeron" },
{ 15, -1, -1, 15, -1, 1, -1, XEON , 0, "Unknown Xeon" },
{ 15, 0, -1, 15, -1, NO_CODE , "Pentium 4 (Willamette)" },
{ 15, 1, -1, 15, -1, NO_CODE , "Pentium 4 (Willamette)" },
{ 15, 2, -1, 15, -1, NO_CODE , "Pentium 4 (Northwood)" },
{ 15, 3, -1, 15, -1, NO_CODE , "Pentium 4 (Prescott)" },
{ 15, 4, -1, 15, -1, NO_CODE , "Pentium 4 (Prescott)" },
{ 15, 6, -1, 15, -1, NO_CODE , "Pentium 4 (Cedar Mill)" },
{ 15, 0, -1, 15, -1, MOBILE_PENTIUM , "Mobile P-4 (Willamette)" },
{ 15, 1, -1, 15, -1, MOBILE_PENTIUM , "Mobile P-4 (Willamette)" },
{ 15, 2, -1, 15, -1, MOBILE_PENTIUM , "Mobile P-4 (Northwood)" },
{ 15, 3, -1, 15, -1, MOBILE_PENTIUM , "Mobile P-4 (Prescott)" },
{ 15, 4, -1, 15, -1, MOBILE_PENTIUM , "Mobile P-4 (Prescott)" },
{ 15, 6, -1, 15, -1, MOBILE_PENTIUM , "Mobile P-4 (Cedar Mill)" },
{ 15, 0, -1, 15, -1, 1, -1, NO_CODE , 0, "Pentium 4 (Willamette)" },
{ 15, 1, -1, 15, -1, 1, -1, NO_CODE , 0, "Pentium 4 (Willamette)" },
{ 15, 2, -1, 15, -1, 1, -1, NO_CODE , 0, "Pentium 4 (Northwood)" },
{ 15, 3, -1, 15, -1, 1, -1, NO_CODE , 0, "Pentium 4 (Prescott)" },
{ 15, 4, -1, 15, -1, 1, -1, NO_CODE , 0, "Pentium 4 (Prescott)" },
{ 15, 6, -1, 15, -1, 1, -1, NO_CODE , 0, "Pentium 4 (Cedar Mill)" },
{ 15, 0, -1, 15, -1, 1, -1, MOBILE_PENTIUM , 0, "Mobile P-4 (Willamette)" },
{ 15, 1, -1, 15, -1, 1, -1, MOBILE_PENTIUM , 0, "Mobile P-4 (Willamette)" },
{ 15, 2, -1, 15, -1, 1, -1, MOBILE_PENTIUM , 0, "Mobile P-4 (Northwood)" },
{ 15, 3, -1, 15, -1, 1, -1, MOBILE_PENTIUM , 0, "Mobile P-4 (Prescott)" },
{ 15, 4, -1, 15, -1, 1, -1, MOBILE_PENTIUM , 0, "Mobile P-4 (Prescott)" },
{ 15, 6, -1, 15, -1, 1, -1, MOBILE_PENTIUM , 0, "Mobile P-4 (Cedar Mill)" },
/* server CPUs */
{ 15, 0, -1, 15, -1, XEON , "Xeon (Foster)" },
{ 15, 1, -1, 15, -1, XEON , "Xeon (Foster)" },
{ 15, 2, -1, 15, -1, XEON , "Xeon (Prestonia)" },
{ 15, 2, -1, 15, -1, XEONMP , "Xeon (Gallatin)" },
{ 15, 3, -1, 15, -1, XEON , "Xeon (Nocona)" },
{ 15, 4, -1, 15, -1, XEON , "Xeon (Nocona)" },
{ 15, 4, -1, 15, -1, XEON_IRWIN , "Xeon (Irwindale)" },
{ 15, 4, -1, 15, -1, XEONMP , "Xeon (Cranford)" },
{ 15, 4, -1, 15, -1, XEON_POTOMAC , "Xeon (Potomac)" },
{ 15, 6, -1, 15, -1, XEON , "Xeon 5000" },
{ 15, 0, -1, 15, -1, 1, -1, XEON , 0, "Xeon (Foster)" },
{ 15, 1, -1, 15, -1, 1, -1, XEON , 0, "Xeon (Foster)" },
{ 15, 2, -1, 15, -1, 1, -1, XEON , 0, "Xeon (Prestonia)" },
{ 15, 2, -1, 15, -1, 1, -1, XEONMP , 0, "Xeon (Gallatin)" },
{ 15, 3, -1, 15, -1, 1, -1, XEON , 0, "Xeon (Nocona)" },
{ 15, 4, -1, 15, -1, 1, -1, XEON , 0, "Xeon (Nocona)" },
{ 15, 4, -1, 15, -1, 1, -1, XEON_IRWIN , 0, "Xeon (Irwindale)" },
{ 15, 4, -1, 15, -1, 1, -1, XEONMP , 0, "Xeon (Cranford)" },
{ 15, 4, -1, 15, -1, 1, -1, XEON_POTOMAC , 0, "Xeon (Potomac)" },
{ 15, 6, -1, 15, -1, 1, -1, XEON , 0, "Xeon (Dempsey)" },
/* Pentium Ds */
{ 15, 4, 4, 15, -1, NO_CODE , "Pentium D" },
{ 15, 4, -1, 15, -1, PENTIUM_D , "Pentium D" },
{ 15, 4, 7, 15, -1, NO_CODE , "Pentium D" },
{ 15, 6, -1, 15, -1, PENTIUM_D , "Pentium D" },
{ 15, 4, 4, 15, -1, 1, -1, NO_CODE , 0, "Pentium D" },
{ 15, 4, -1, 15, -1, 1, -1, PENTIUM_D , 0, "Pentium D" },
{ 15, 4, 7, 15, -1, 1, -1, NO_CODE , 0, "Pentium D" },
{ 15, 6, -1, 15, -1, 1, -1, PENTIUM_D , 0, "Pentium D" },
/* Celeron and Celeron Ds */
{ 15, 1, -1, 15, -1, CELERON , "P-4 Celeron (128K)" },
{ 15, 2, -1, 15, -1, CELERON , "P-4 Celeron (128K)" },
{ 15, 3, -1, 15, -1, CELERON , "Celeron D" },
{ 15, 4, -1, 15, -1, CELERON , "Celeron D" },
{ 15, 6, -1, 15, -1, CELERON , "Celeron D" },
{ 15, 1, -1, 15, -1, 1, -1, CELERON , 0, "P-4 Celeron (128K)" },
{ 15, 2, -1, 15, -1, 1, -1, CELERON , 0, "P-4 Celeron (128K)" },
{ 15, 3, -1, 15, -1, 1, -1, CELERON , 0, "Celeron D" },
{ 15, 4, -1, 15, -1, 1, -1, CELERON , 0, "Celeron D" },
{ 15, 6, -1, 15, -1, 1, -1, CELERON , 0, "Celeron D" },
};
@ -467,18 +486,12 @@ static void decode_intel_number_of_cores(struct cpu_raw_data_t* raw,
}
}
static void decode_intel_codename(struct cpu_raw_data_t* raw, struct cpu_id_t* data)
static intel_code_t get_brand_code(struct cpu_id_t* data)
{
intel_code_t code = NO_CODE;
int i;
int L2 = data->l2_cache;
const char* bs = data->brand_str;
const char* s;
const struct { int cache_size; intel_code_t code; } match_cache[] = {
{ 512, CORE_DUO_512K },
{ 1024, CORE_DUO_1024K },
{ 2048, ALLENDALE },
};
const struct { intel_code_t c; const char *search; } matchtable[] = {
{ XEONMP, "Xeon MP" },
{ XEONMP, "Xeon(TM) MP" },
@ -544,34 +557,69 @@ static void decode_intel_codename(struct cpu_raw_data_t* raw, struct cpu_id_t* d
}
}
if (code == CORE_DUO && L2 != 4096) {
for (i = 0; i < COUNT_OF(match_cache); i++) {
if (match_cache[i].cache_size == L2) {
code = match_cache[i].code;
break;
}
}
}
if (code == CORE_DUO && data->ext_model >= 23) {
if (L2 == 3072 || L2 == 6144)
code = (L2 == 3072) ? WOLFDALE_3M : WOLFDALE_6M;
code = WOLFDALE;
}
if (code == PENTIUM_D && data->ext_model >= 23) {
code = WOLFDALE_2M;
code = WOLFDALE;
}
if (code == MOBILE_CORE_DUO && data->model != 14) {
if (data->ext_model < 23) {
if (L2 == 2048 || L2 == 4096)
code = (L2 == 2048) ? MEROM_2M : MEROM_4M;
code = MEROM;
} else {
if (data->num_cores == 2) {
if (L2 == 3072 || L2 == 6144)
code = (L2 == 3072) ? PENRYN_3M : PENRYN_6M;
} else
code = PENRYN_QUAD;
code = PENRYN;
}
}
match_cpu_codename(cpudb_intel, COUNT_OF(cpudb_intel), data, code);
return code;
}
static intel_model_t get_model_code(struct cpu_id_t* data)
{
int i = 0;
int l = (int) strlen(data->brand_str);
const char *bs = data->brand_str;
int mod_flags = 0, model_no = 0, ndigs = 0;
while (i < l - 3) {
if (bs[i] == 'C' && bs[i+1] == 'P' && bs[i+2] == 'U')
break;
i++;
}
if (i >= l - 3) return UNKNOWN;
i += 3;
while (i < l - 4 && bs[i] == ' ') i++;
if (i >= l - 4) return UNKNOWN;
while (i < l - 4 && !isdigit(bs[i])) {
if (bs[i] >= 'A' && bs[i] <= 'Z')
mod_flags |= (1 << (bs[i] - 'A'));
i++;
}
if (i >= l - 4) return UNKNOWN;
while (isdigit(bs[i])) {
ndigs++;
model_no = model_no * 10 + (int) (bs[i] - '0');
i++;
}
if (ndigs != 4) return UNKNOWN;
#define HAVE(ch, flags) ((flags & (1 << ((int)(ch-'A')))) != 0)
switch (model_no / 100) {
case 30: return _3000;
case 31: return _3100;
case 32:
{
return (HAVE('X', mod_flags)) ? X3200 : _3200;
}
case 33:
{
return (HAVE('X', mod_flags)) ? X3300 : _3300;
}
case 51: return _5100;
case 52: return _5200;
case 53: return _5300;
case 54: return _5400;
default:
return UNKNOWN;
}
#undef HAVE
}
int cpuid_identify_intel(struct cpu_raw_data_t* raw, struct cpu_id_t* data)
@ -584,6 +632,7 @@ int cpuid_identify_intel(struct cpu_raw_data_t* raw, struct cpu_id_t* data)
decode_intel_oldstyle_cache_info(raw, data);
}
decode_intel_number_of_cores(raw, data);
decode_intel_codename(raw, data);
match_cpu_codename(cpudb_intel, COUNT_OF(cpudb_intel), data,
get_brand_code(data), get_model_code(data));
return 0;
}