1
0
Fork 0
mirror of https://github.com/anrieff/libcpuid synced 2025-10-03 11:01:30 +00:00
Commit graph

26 commits

Author SHA1 Message Date
Xorg
0c9ef3249c Decode deterministic cache info for AMD CPUs too
Since Zen-based CPUs, cpu_id_t::l3_cache is the size of the total L3 cache for the whole chip, while cpu_id_t::l1_cache and cpu_id_t::l2_cache are size for each instances.
This change provide L3 cache size per instance.
2022-09-22 17:49:38 +02:00
Xorg
ab395f8756
Do not inline util functions
It creates warning with GCC.
2022-09-15 22:15:48 +02:00
Xorg
2b8023f733
Support for hybrid CPU (#166)
* Set CMAKE_C_FLAGS_DEBUG to display warnings during build

CI workflows are reporting warnings. Adding more C flags here help to avoid that.

* Add new types

* Add set_cpu_affinity function

* Add cpu_identify_all function

* Add cpu_request_core_type function

* Add cpuid_get_all_raw_data, cpuid_serialize_all_raw_data and cpuid_deserialize_all_raw_data functions

* Detect hybrid architecture for Intel CPUs

* Update cpuid_tool to detect all CPU logical cores

* Rename tests subdirectories for Intel Core

* Update all tests

Since e4309a6c4bc3ad875711a1599cba01a205b3103e, new fields are reported by cpuid_tool

* Add Intel Alder Lake

Fix #157

* Remove convert_instlatx64.c

This tool is not useful anymore because the cpuid_deserialize_raw_data_internal() function can natively parse them since 5667e1401c

* Fix affinity_mask computation

* Define _GNU_SOURCE in configure.ac

Forgotten in 4f80964db5

* Use dynamic raw array in cpu_raw_data_array_t

* Add cpu_affinity_mask_t type

* Improve set_cpu_affinity function

- Print a warning if logical CPU number is not supported on operating system
- Return a boolean value in case of success instead of an integer

* Improve cpu_identify_all and cpu_request_core_type functions

* Use dynamic array for cpu_types in system_id_t

This commit also adds cleanups, fixes and consistency

* Tests: update Ryzen 5 Matisse with all CPU cores

* Add affinity_mask_str_r function and address other comments

- Fixed cpuid_grow_raw_data_array and cpu_raw_data_array_t.logical_cpu_t with the correct type
- Added a note about hard limit of cpu_raw_data_array_t
- Fixed a typo in cpuid_deserialize_raw_data_internal

* Fix build on Windows
2022-09-15 18:37:08 +02:00
emixa-d
bca7a19279
Report memory allocation failures without segfaulting. (#160) 2022-01-23 02:38:40 +02:00
Alyssa Ross
1acaf9980b
Use popcount64 from libc when available (#152)
* Use popcount64 from libc when available

Without this, we get a compiler error on NetBSD because the one in
libc has a slightly different prototype.

libcpuid_util.c:78:12: error: conflicting types for 'popcount64'
   78 | static int popcount64(uint64_t mask)
      |            ^~~~~~~~~~
In file included from /nix/store/155rj8nqh3xd80vpa8hl35p3hk7pacys-include-netbsd-8.0/include/string.h:98,
                 from libcpuid_util.c:30:
/nix/store/155rj8nqh3xd80vpa8hl35p3hk7pacys-include-netbsd-8.0/include/strings.h:61:14: note: previous declaration of 'popcount64' was here
   61 | unsigned int popcount64(__uint64_t) __constfunc;
      |              ^~~~~~~~~~

* Return unsigned int from popcount64

Matches NetBSD libc, where popcount64 originates.
2021-07-16 01:55:36 +03:00
Xorg
0b05f45e03
Remove all trailling spaces
It is annoying with some text editors
2020-05-09 17:34:07 +02:00
Veselin Georgiev
8179882abb Major refactoring of the Intel match tables.
There were a lot of instances where there was additional code
written to detect certain features from the brand string
(e.g., does it have "Core (TM)"? if it has, does it have "i3"?).
It makes sense to only write code for detecting these features
in isolation, preventing the exponential blowup of possible
intel_code_t values (e.g. previously there were enum values
for CORE_{,IVY,HASWELL,BROADWELL,SKYLAKE}{,M}{3,5,7} - almost
20 separate enums items; these can now be expressed with the
respective bits (CORE_, _I_, _M_, _3, _5 and _7).

The change in matchtables is the addition of an extra field
after brand_code: it is called model_bits. The bits for each
vendor is defined in the beginning of recog_<<vendor>>.c

This is the first part of the overhaul, which handles the bits
detection and proper matchtables for Intel. Refactoring of
AMD detection code coming next...
2017-03-20 01:01:22 +02:00
Veselin Georgiev
50530f7618 Fix issue #51: Undefined behavior. 2016-07-31 17:48:49 +03:00
Veselin Georgiev
a2550463a9 Reorganize library a bit.
- Expose intel_code_t and amd_code_t enums - they are no longer
  limited to just recog_{intel,amd}.c.
- Add libcpuid_internal.h lists those enums and provides the,
  cpu_ident_internal() function, which is the same as cpu_identify(),
  but also has a third parameter - a internal_id_info_t structure,
  which holds detection internals.

All of this is intended to be used in rdmsr, which needs to know
specifics on what CPU it is running.
2016-06-03 03:30:36 +03:00
cosmy1
4dbcaaf47d Update libcpuid_util.c 2015-07-31 14:21:41 +02:00
cosmy1
fe63724d53 MSVC warning fix
using _strdup instead of strdup on Visual C++
2015-07-31 14:20:58 +02:00
Veselin Georgiev
94fc6ae36a Modify the table matcher a bit. Put some weights on the different fields.
Priously all fields in the matchtable were treated equal in importance.
With this change, the cache size a taken with half the weight in the decision.

Also add detection entries for some more recent Haswells, and the respective
tests. These are an i5 Haswell from a Mac Book Pro, and a i7 Haswel from
Thinkpad T540.
2015-04-17 01:21:30 +03:00
Veselin Georgiev
d520a37569 Support for Core i5/i3. The matchtables now have a column for L3 cache
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@87 3b4be424-7ac5-41d7-8526-f4ddcb85d872
2010-10-13 09:18:07 +00:00
Veselin Georgiev
e96082c67f Added support for reading MSRs through dedicated driver on Win32
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@69 3b4be424-7ac5-41d7-8526-f4ddcb85d872
2009-09-30 11:25:14 +00:00
Veselin Georgiev
b089617cca Forgot to include ctype.h
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@66 3b4be424-7ac5-41d7-8526-f4ddcb85d872
2009-09-10 03:47:14 +00:00
Veselin Georgiev
103bb027c6 Support for Nehalem Xeons added
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@60 3b4be424-7ac5-41d7-8526-f4ddcb85d872
2009-08-26 03:57:14 +00:00
Veselin Georgiev
35a9c794b2 Added a Makefile for x86 (commandline build). Using _vsnprintf when _MSC_VER is defined unconditionally, since the MSVC 2003 doesn't have vsnprintf.
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@56 3b4be424-7ac5-41d7-8526-f4ddcb85d872
2009-06-18 15:32:44 +00:00
Veselin Georgiev
94ab2ea0f7 Ported to win64. Assembly bits are taken out to external .asm file. Passes tests on Windows 2003 Server x64
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@53 3b4be424-7ac5-41d7-8526-f4ddcb85d872
2009-01-27 01:42:23 +00:00
Veselin Georgiev
5ae4a8dd8e Added known-cpu-list function. Rearranged Intel CPU list to be better chronologically ordered
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@45 3b4be424-7ac5-41d7-8526-f4ddcb85d872
2008-12-27 15:46:03 +00:00
Veselin Georgiev
f986629b65 Reorganization of CPU databases, added correct recognition of most Core-based Xeons, fixed a few other misrecognitions
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@40 3b4be424-7ac5-41d7-8526-f4ddcb85d872
2008-12-12 18:56:29 +00:00
Veselin Georgiev
8fa280cdbd Ported to strict C
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@37 3b4be424-7ac5-41d7-8526-f4ddcb85d872
2008-12-08 16:53:59 +00:00
Veselin Georgiev
a1395632fa Fixed many bugreports. Correct recognition for some Core2 Xeons, some ConroeLs, Sempron Codenames, some A64 and A64X2 codenames.
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@36 3b4be424-7ac5-41d7-8526-f4ddcb85d872
2008-12-08 16:52:01 +00:00
Veselin Georgiev
4dfb11f699 Ported to Win32 (MSVC 2005), added MSVC solution and project files. Seems to work :)
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@26 3b4be424-7ac5-41d7-8526-f4ddcb85d872
2008-11-20 18:26:46 +00:00
Veselin Georgiev
c5c0539372 * Support for stdin/stdout for (de)serializing cpu_raw_data_t;
* set_warn_function renamed to cpuid_set_warn_function;
* Updated Doxygen documentation: added manpage output, generic mainpage intro, default module named correctly;
* Updated doxy libcpuid.h documentation, fixed some bugs;
* Warnings are now printed to stderr by default, not stdout;
* Some constants in AMD code did not reflected their meaning well, fixed;
* The cpuid_tool utility thoroughly redesigned; now a multiple-function program, perhaps close to the finalized state.

git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@19 3b4be424-7ac5-41d7-8526-f4ddcb85d872
2008-11-19 16:27:31 +00:00
Veselin Georgiev
5c348fd6bd Using set_warn_function() with NULL crashes if warning were to be emitted. Fixed
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@18 3b4be424-7ac5-41d7-8526-f4ddcb85d872
2008-11-18 22:39:14 +00:00
Veselin Georgiev
381a9b07d8 Intel detection is complete, needs debug and research of newest processors
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@8 3b4be424-7ac5-41d7-8526-f4ddcb85d872
2008-11-14 15:06:01 +00:00