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Author SHA1 Message Date
Veselin Georgiev
0f90f77910 Fixed a crash with gcc-4.6.3 in 32-bit mode. The compiler aggressively optimizes exec_cpuid(), making the stack layout not exactly what the assembly expects. Rearranging instructions seems to fix things. The 64-bit changes aren't tested, though. 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@110 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2013-01-18 22:32:44 +00:00
Veselin Georgiev
b175d4d6df VS 2002 also doesn't support long long natively (thanks to Andras Kenez for the pointer) 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@109 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2012-09-19 16:53:09 +00:00
Veselin Georgiev
18d2b9b075 Updated checking scripts 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@108 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2012-09-09 22:29:12 +00:00
Veselin Georgiev
f385bac458 Added support for Intel Atom Cedarview 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@107 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2012-09-09 22:28:55 +00:00
Veselin Georgiev
b65ac8c8e6 Changed code generation to Multithreaded DLL 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@106 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2012-08-26 20:29:44 +00:00
Veselin Georgiev
767c09c57b Ported to Microsoft Visual C 6.0 
It requires MSVC 6.0 with SP5 and Processor Pack 5 installed (for SSE instruction support).

git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@105 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2012-08-25 23:14:59 +00:00
Veselin Georgiev
1344ec1a81 Added support for detecting the following processors: The newer 6 and 8-core Sandy Bridges (termed Sandy Bridge-E), Ivy Bridge, AMD Magny-Cours. Added support for detecting the rdrand instruction. Added tests. 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@104 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2012-05-26 13:00:04 +00:00
Veselin Georgiev
61cd70d90a Proper detection for the Bulldozer. It reports itself as having 8 cores. 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@103 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2011-10-14 09:49:52 +00:00
Veselin Georgiev
23dac9da66 Version of the Windows build upped to 0.2.0 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@102 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2011-10-14 03:02:50 +00:00
Veselin Georgiev
9fafda1bed Added support for Sandy-bridge based celerons 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@101 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2011-10-13 22:46:42 +00:00
Veselin Georgiev
8413e8969a Fixed bogus llano detection, added detection for Bulldozer. Not tested, since I don't have an engineering sample:) 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@100 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2011-10-11 17:39:29 +00:00
Veselin Georgiev
62605fffd8 Added a test with a Zacate CPU. Also, fixed the add_test script 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@99 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2011-10-11 17:33:30 +00:00
Veselin Georgiev
42fc8b4654 Modified the test-stash and the testing code, so that it is aware of the SSE unit size functionality. Also, added support for detecting AMD Llano/Brazos CPUs 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@98 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2011-10-11 17:26:00 +00:00
Veselin Georgiev
fead3f21e3 Use -sse-size instead of --sse_size, to be consistent 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@97 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2011-10-11 16:59:26 +00:00
Veselin Georgiev
3623c5639d Added SSE unit size detection, based on the AMD extended leaf 1a, bit 0. Added a field in cpu_id_t to specify SSE unit size. Also added a hints array, similar to the flags array, which will hold various detection-specific hints. The only currently present hint is about the way the SSE unit size is inferred - whether it is based on the old CPU family/model guesswork (which fails for the AMD Brazos-based cores). Also, added the features XOP, FMA4, TBM and F16C. Changed the library version due to breaking binary compatibility. 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@96 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2011-10-11 16:38:41 +00:00
Veselin Georgiev
2f949b18d9 Support for 2MB L2 Cache Yorkfield added. Also, made the logic a bit more foolproof by adding explicit core count for those Yorkfields. 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@95 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2011-01-16 01:11:00 +00:00
Veselin Georgiev
c3d236ec86 Bumped the version to 0.1.4 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@94 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2011-01-14 05:28:31 +00:00
Veselin Georgiev
49c474f74d Support for Sandy Bridge (Core i7) processors 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@93 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2011-01-13 18:01:51 +00:00
Veselin Georgiev
166445dbd0 Added Celeron Wolfdale (45nm-based 1MB cache C2D CPU) 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@92 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2011-01-13 13:34:13 +00:00
Veselin Georgiev
27e7508e7d Support for Arrandale i7s 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@91 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2011-01-13 13:12:21 +00:00
Veselin Georgiev
f398770f79 Implemented busy_sse_loop for win32. Need to do for x64 though. 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@90 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2011-01-10 13:37:51 +00:00
Veselin Georgiev
f1c250d6cf Support for Lynnfield i7s, and better detection of Athlon Propus. Also, added newer Athlon II X3s (Rana) 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@89 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2010-10-15 08:37:54 +00:00
Veselin Georgiev
6a7854f3b4 Support for Gulftown (westmere-based) Intels, and for AMD X6 (Thuban). Also differentiated the Thuban-derived X4s (Zosma) which I suppose also have ext model 10, but this needs to be verified. 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@88 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2010-10-13 11:59:46 +00:00
Veselin Georgiev
d520a37569 Support for Core i5/i3. The matchtables now have a column for L3 cache 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@87 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2010-10-13 09:18:07 +00:00
Veselin Georgiev
e28b38aa1e The previous fix was bogus on the i7, so now it is fixed to what the previous value was 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@86 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2010-04-20 10:22:10 +00:00
Veselin Georgiev
75934f2538 An erorrneous commit was reverted 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@85 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2010-04-20 10:18:53 +00:00
Veselin Georgiev
23b5b71856 Another minor fix 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@84 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2010-04-20 10:17:21 +00:00
Veselin Georgiev
a7a45d8efb A small correction 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@83 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2010-04-20 10:03:03 +00:00
Veselin Georgiev
b922a5b29c A small correction to account for the non-loop instructions in busy_sse_loop() 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@82 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2010-04-20 09:59:12 +00:00
Veselin Georgiev
4802081283 Apple's GCC wasn't very happy with "eax" in the assembly block operands. However, changing to "a" fixes it 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@81 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2010-04-20 09:52:24 +00:00
Veselin Georgiev
75c7ba17d5 Preliminary code to detect SSE width for proper clock detection with cpu_clock_by_ic() 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@80 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2010-04-20 09:43:17 +00:00
Veselin Georgiev
62ab176334 Forgot one of 32 blocks 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@79 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2010-04-20 09:09:34 +00:00
Veselin Georgiev
828e643549 Forgot to add the new header file for rdtsc.c 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@78 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2010-04-20 09:03:57 +00:00
Veselin Georgiev
44c313126b Added cpu_clock_by_ic() function to measure cpu clock using instruction counting. Still not translated to MSVC, and isn't tested on CPUs other than Core i7 (but there it works beatifully). Bumped version to 0.1.3. 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@77 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2010-04-20 09:01:07 +00:00
Veselin Georgiev
af2c364e85 Ported to OSX 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@76 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2009-10-27 16:47:26 +00:00
Veselin Georgiev
519f984578 Added MPERF and APERF MSR incrementation speed calculation using a 10ms delay loop 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@75 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2009-10-05 01:08:36 +00:00
Veselin Georgiev
b0092bd84e Added support for reading the max multiplier 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@74 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2009-10-02 09:14:45 +00:00
Veselin Georgiev
277eb73da7 Fixed a bug in Linux MSR readout. The address of the MSR is the msr_index, not msr_index*8 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@73 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2009-10-02 07:45:17 +00:00
Veselin Georgiev
4729960411 Basic Linux support, untested 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@72 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2009-10-01 20:55:01 +00:00
Veselin Georgiev
e4920d79b0 Added cpu_msrinfo() function and implemented a few test info entries 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@71 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2009-09-30 17:20:52 +00:00
Veselin Georgiev
0bd7a6d83f The logic behind the big IFDEF at msrdriver.c was wrong. You could compile a 32-bit build and run it on 64-bit windows, and in this case you will still need the 64-bit driver. So the platform detection is made runtime, and the correct driver for the platform is extracted on demand. 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@70 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2009-09-30 15:27:39 +00:00
Veselin Georgiev
e96082c67f Added support for reading MSRs through dedicated driver on Win32 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@69 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2009-09-30 11:25:14 +00:00
Veselin Georgiev
432a585c78 Moved the checking for stdint to the corresponding header 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@68 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2009-09-26 23:51:11 +00:00
Veselin Georgiev
3578314b9b Added support for Athlon II Propus 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@67 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2009-09-24 20:39:04 +00:00
Veselin Georgiev
b089617cca Forgot to include ctype.h 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@66 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2009-09-10 03:47:14 +00:00
Veselin Georgiev
831962cb07 Fix for a few badly detected Yonahs. They read as Unknown Yonah. Added a test-case as well 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@65 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2009-09-10 03:44:19 +00:00
Veselin Georgiev
a8e1da64d3 Fixed a typo for Athlon X2 (Kuma) and added such an entry to the test stash 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@64 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2009-09-10 03:29:06 +00:00
Veselin Georgiev
7251690507 Fixed a regression. Core2 Quad (Q66xx series) incorrectly recognized as a Xeon 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@63 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2009-09-10 03:01:31 +00:00
Veselin Georgiev
69312e9741 Cleared problems with the Phenom/PhenomII line. Now PhenomIIs are recognized as such. Also, Sempron and Athlon II branded derivates of the Phenom line are properly recognized 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@62 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2009-09-10 01:28:33 +00:00
Veselin Georgiev
decdd2e001 Added detection for Xeon (Gainestown) and Conroe-L (Celeron). Dual-core Conroe-L's are renamed to Conroe-L (Allendale). 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@61 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2009-09-10 01:04:10 +00:00