6 commits

Author	SHA1	Message	Date
Xorg	4382796761	DB: add Xeon E3 1275 ... Score for entry 'Bloomfield (Xeon)' is 10 with this CPU So it does not match with entry 'Sandy Bridge (Xeon)' (also score 10) Adding this new entry increase score to 12, and fixing this issue Close X0rg/CPU-X#182	2021-01-28 20:24:06 +01:00
Xorg	fb1deb1fef	Tests: update all tests to add fields for L1I	2020-05-10 17:02:45 +00:00
Veselin Georgiev	f52c02d394	Update all tests: add fields for L4 cache size, assoc. and line size.	2016-07-07 00:44:45 +03:00
Veselin Georgiev	4e3b633bee	Fix tests due to X0rg's codename changes.	2015-09-13 18:38:59 +03:00
Veselin Georgiev	ce02f0bc96	Fix broken tests, where rdtscp in recent Intel chips is missing. ... As described in previous commit.	2014-09-23 15:21:02 +03:00
Veselin Georgiev	019170b65f	Refactor the tests: put each test case in a separate file ... Instead of one big pile of tests in tests_stash.txt, keep each CPU example raw data/parsed data in a file, ordered in a tree by manufacturer and microarchitecture. The 64 .test files have been extracted from tests_stash.txt. The add_test script is changed to create_test and it doesn't append to test_stash.txt, instead it spits out data to be saved in a .test file. run_tests.py is not refactored yet, to be done in a subsequent commit.	2014-07-15 19:59:35 +03:00