mirror of
https://github.com/anrieff/libcpuid
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134 lines
4.6 KiB
C
134 lines
4.6 KiB
C
/*
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* Copyright 2024 Veselin Georgiev,
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* anrieffNOSPAM @ mgail_DOT.com (convert to gmail)
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __LIBCPUID_ARM_DRIVER_H__
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#define __LIBCPUID_ARM_DRIVER_H__
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#define AARCH64_REG_MIDR_EL1 "S3_0_C0_C0_0"
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#define AARCH64_REG_MPIDR_EL1 "S3_0_C0_C0_5"
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#define AARCH64_REG_REVIDR_EL1 "S3_0_C0_C0_6"
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#define AARCH64_REG_ID_AFR0 "S3_0_C0_C1_3"
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#define AARCH64_REG_ID_DFR0 "S3_0_C0_C1_2"
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#define AARCH64_REG_ID_DFR1 "S3_0_C0_C3_5"
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#define AARCH64_REG_ID_ISAR0 "S3_0_C0_C2_0"
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#define AARCH64_REG_ID_ISAR1 "S3_0_C0_C2_1"
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#define AARCH64_REG_ID_ISAR2 "S3_0_C0_C2_2"
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#define AARCH64_REG_ID_ISAR3 "S3_0_C0_C2_3"
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#define AARCH64_REG_ID_ISAR4 "S3_0_C0_C2_4"
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#define AARCH64_REG_ID_ISAR5 "S3_0_C0_C2_5"
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#define AARCH64_REG_ID_ISAR6 "S3_0_C0_C2_7"
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#define AARCH64_REG_ID_MMFR0 "S3_0_C0_C1_4"
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#define AARCH64_REG_ID_MMFR1 "S3_0_C0_C1_5"
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#define AARCH64_REG_ID_MMFR2 "S3_0_C0_C1_6"
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#define AARCH64_REG_ID_MMFR3 "S3_0_C0_C1_7"
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#define AARCH64_REG_ID_MMFR4 "S3_0_C0_C2_6"
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#define AARCH64_REG_ID_MMFR5 "S3_0_C0_C3_6"
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#define AARCH64_REG_ID_PFR0 "S3_0_C0_C1_0"
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#define AARCH64_REG_ID_PFR1 "S3_0_C0_C1_1"
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#define AARCH64_REG_ID_PFR2 "S3_0_C0_C3_4"
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#define AARCH64_REG_ID_AA64AFR0_EL1 "S3_0_C0_C5_4"
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#define AARCH64_REG_ID_AA64AFR1_EL1 "S3_0_C0_C5_5"
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#define AARCH64_REG_ID_AA64DFR0_EL1 "S3_0_C0_C5_0"
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#define AARCH64_REG_ID_AA64DFR1_EL1 "S3_0_C0_C5_1"
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#define AARCH64_REG_ID_AA64DFR2_EL1 "S3_0_C0_C5_2"
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#define AARCH64_REG_ID_AA64FPFR0_EL1 "S3_0_C0_C4_7"
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#define AARCH64_REG_ID_AA64ISAR0_EL1 "S3_0_C0_C6_0"
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#define AARCH64_REG_ID_AA64ISAR1_EL1 "S3_0_C0_C6_1"
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#define AARCH64_REG_ID_AA64ISAR2_EL1 "S3_0_C0_C6_2"
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#define AARCH64_REG_ID_AA64ISAR3_EL1 "S3_0_C0_C6_3"
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#define AARCH64_REG_ID_AA64MMFR0_EL1 "S3_0_C0_C7_0"
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#define AARCH64_REG_ID_AA64MMFR1_EL1 "S3_0_C0_C7_1"
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#define AARCH64_REG_ID_AA64MMFR2_EL1 "S3_0_C0_C7_2"
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#define AARCH64_REG_ID_AA64MMFR3_EL1 "S3_0_C0_C7_3"
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#define AARCH64_REG_ID_AA64MMFR4_EL1 "S3_0_C0_C7_4"
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#define AARCH64_REG_ID_AA64PFR0_EL1 "S3_0_C0_C4_0"
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#define AARCH64_REG_ID_AA64PFR1_EL1 "S3_0_C0_C4_1"
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#define AARCH64_REG_ID_AA64PFR2_EL1 "S3_0_C0_C4_2"
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#define AARCH64_REG_ID_AA64SMFR0_EL1 "S3_0_C0_C4_5"
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#define AARCH64_REG_ID_AA64ZFR0_EL1 "S3_0_C0_C4_4"
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typedef enum {
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REQ_MIDR,
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REQ_MPIDR,
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REQ_REVIDR,
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REQ_ID_AFR0,
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REQ_ID_DFR0,
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REQ_ID_DFR1,
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REQ_ID_ISAR0,
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REQ_ID_ISAR1,
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REQ_ID_ISAR2,
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REQ_ID_ISAR3,
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REQ_ID_ISAR4,
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REQ_ID_ISAR5,
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REQ_ID_ISAR6,
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REQ_ID_MMFR0,
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REQ_ID_MMFR1,
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REQ_ID_MMFR2,
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REQ_ID_MMFR3,
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REQ_ID_MMFR4,
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REQ_ID_MMFR5,
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REQ_ID_PFR0,
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REQ_ID_PFR1,
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REQ_ID_PFR2,
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#if defined(__aarch64__)
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REQ_ID_AA64AFR0,
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REQ_ID_AA64AFR1,
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REQ_ID_AA64DFR0,
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REQ_ID_AA64DFR1,
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REQ_ID_AA64DFR2,
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REQ_ID_AA64FPFR0,
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REQ_ID_AA64ISAR0,
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REQ_ID_AA64ISAR1,
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REQ_ID_AA64ISAR2,
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REQ_ID_AA64ISAR3,
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REQ_ID_AA64MMFR0,
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REQ_ID_AA64MMFR1,
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REQ_ID_AA64MMFR2,
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REQ_ID_AA64MMFR3,
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REQ_ID_AA64MMFR4,
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REQ_ID_AA64PFR0,
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REQ_ID_AA64PFR1,
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REQ_ID_AA64PFR2,
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REQ_ID_AA64SMFR0,
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REQ_ID_AA64ZFR0,
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#endif /* __aarch64__ */
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/* termination: */
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NUM_REG_REQUESTS,
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REQ_INVALID = -1
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} reg_request_t;
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struct read_reg_t {
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reg_request_t request;
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union {
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uint32_t value_32b;
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uint64_t value_64b;
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};
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};
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typedef struct read_reg_t read_reg_t;
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#define ARM_IOC_READ_REG _IOWR('c', 0xB0, read_reg_t)
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#endif /* __LIBCPUID_ARM_DRIVER_H__ */
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