Veselin Georgiev 87f3052a7b Add a test with L4 cache (courtesy of @phprus). ... The test is a snapshot of a Haswell i7 (a.k.a. "Crystalwell") core. This is the only test in the test DB right now which has lines for L4 cache size, associativity and cacheline size different than "-1". Also update create_test.py to accommodate for the new fields.		2016-07-07 00:53:03 +03:00
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atom	Update all tests: add fields for L4 cache size, assoc. and line size.	2016-07-07 00:44:45 +03:00
core2	Update all tests: add fields for L4 cache size, assoc. and line size.	2016-07-07 00:44:45 +03:00
haswell	Add a test with L4 cache (courtesy of @phprus).	2016-07-07 00:53:03 +03:00
ivy	Add support for detecting Xeon Ivy Bridge.	2015-09-03 09:33:38 +03:00
nehalem	Update all tests: add fields for L4 cache size, assoc. and line size.	2016-07-07 00:44:45 +03:00
netburst	Update all tests: add fields for L4 cache size, assoc. and line size.	2016-07-07 00:44:45 +03:00
p2	Update all tests: add fields for L4 cache size, assoc. and line size.	2016-07-07 00:44:45 +03:00
sandy	Update all tests: add fields for L4 cache size, assoc. and line size.	2016-07-07 00:44:45 +03:00
skylake	Update all tests: add fields for L4 cache size, assoc. and line size.	2016-07-07 00:44:45 +03:00