1
0
Fork 0
mirror of https://github.com/anrieff/libcpuid synced 2024-11-10 22:59:13 +00:00
libcpuid/tests/intel
Veselin Georgiev f6e4e23796 Add Xeon CLX (Cascade lake-based) using data from PR #129
Kudos to Leslie-Fang for providing it!
2019-08-09 11:18:20 +03:00
..
atom Fixed issue #54: Intel Atom N450 not recognised properly 2016-08-24 15:06:40 +03:00
broadwell Fixed issue #76: Skylake Core i5 badly recognized 2016-10-25 05:16:44 +03:00
core2 Update all tests: add fields for L4 cache size, assoc. and line size. 2016-07-07 00:44:45 +03:00
haswell Add a test with L4 cache (courtesy of @phprus). 2016-07-07 00:53:03 +03:00
ivy Fixed issue #81: Misdiagnosis microarchitecture for i3-3220T 2017-02-10 03:48:00 +02:00
lakes DB: Add Kaby Lake-U 2018-09-23 22:06:53 +02:00
nehalem Update all tests: add fields for L4 cache size, assoc. and line size. 2016-07-07 00:44:45 +03:00
netburst Update all tests: add fields for L4 cache size, assoc. and line size. 2016-07-07 00:44:45 +03:00
p2 Fix P-III Celeron misdetected as plain P-III (misreport id #8) 2018-05-02 11:05:25 +03:00
qemu virtual machine test 2018-04-21 01:00:30 +00:00
sandy Update all tests: add fields for L4 cache size, assoc. and line size. 2016-07-07 00:44:45 +03:00
skylake Add Xeon CLX (Cascade lake-based) using data from PR #129 2019-08-09 11:18:20 +03:00