oot/asm/entry.s

.include "macro.inc"

# assembler directives
.set noat      # allow manual use of $at
.set noreorder # don't insert nops after branches
.set gp=64     # allow use of 64-bit general purpose registers

.section .text

.set BOOT_STACK_SIZE, 0x400

glabel entrypoint # 0x80000400
    lui   $t0, %hi(_bootSegmentBssStart)
    addiu $t0, %lo(_bootSegmentBssStart)
    li    $t1, %lo(_bootSegmentBssSize)
.L8000040C:
    addi  $t1, $t1, -8
    sw    $zero, ($t0)
    sw    $zero, 4($t0)
    bnez  $t1, .L8000040C
     addi  $t0, $t0, 8
    lui   $t2, %hi(bootproc)
    lui   $sp, %hi(sBootThreadStack + BOOT_STACK_SIZE)
    addiu $t2, %lo(bootproc)
    jr    $t2
     addiu $sp, %lo(sBootThreadStack + BOOT_STACK_SIZE)
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
Disassemble the rom header and entrypoint function (#87) The actual boot code (ipl3) is still only incbin'd. If someone else wants to disassemble it properly, go ahead. I might do it eventually, but for now it doesn't seem required for shiftability or anything interesting. 2020-04-22 17:44:46 +00:00			`.include "macro.inc"`

			`# assembler directives`
			`.set noat # allow manual use of $at`
			`.set noreorder # don't insert nops after branches`
Properly align asm & data (+ minor fixes) (#165) * Add .align 4 directives to all data/ files (+ minor alignment fixes) * Use .balign for everything and fix typo 2020-05-26 22:09:00 +00:00			`.set gp=64 # allow use of 64-bit general purpose registers`
Disassemble the rom header and entrypoint function (#87) The actual boot code (ipl3) is still only incbin'd. If someone else wants to disassemble it properly, go ahead. I might do it eventually, but for now it doesn't seem required for shiftability or anything interesting. 2020-04-22 17:44:46 +00:00
			`.section .text`

Preliminary fixes for boot/libultra (#1032) * Preliminary fixes * Missed a NULL 2021-11-28 12:50:35 +00:00			`.set BOOT_STACK_SIZE, 0x400`

Disassemble the rom header and entrypoint function (#87) The actual boot code (ipl3) is still only incbin'd. If someone else wants to disassemble it properly, go ahead. I might do it eventually, but for now it doesn't seem required for shiftability or anything interesting. 2020-04-22 17:44:46 +00:00			`glabel entrypoint # 0x80000400`
Preliminary fixes for boot/libultra (#1032) * Preliminary fixes * Missed a NULL 2021-11-28 12:50:35 +00:00			`lui $t0, %hi(_bootSegmentBssStart)`
			`addiu $t0, %lo(_bootSegmentBssStart)`
			`li $t1, %lo(_bootSegmentBssSize)`
Disassemble the rom header and entrypoint function (#87) The actual boot code (ipl3) is still only incbin'd. If someone else wants to disassemble it properly, go ahead. I might do it eventually, but for now it doesn't seem required for shiftability or anything interesting. 2020-04-22 17:44:46 +00:00			`.L8000040C:`
			`addi $t1, $t1, -8`
			`sw $zero, ($t0)`
			`sw $zero, 4($t0)`
			`bnez $t1, .L8000040C`
			`addi $t0, $t0, 8`
Preliminary fixes for boot/libultra (#1032) * Preliminary fixes * Missed a NULL 2021-11-28 12:50:35 +00:00			`lui $t2, %hi(bootproc)`
			`lui $sp, %hi(sBootThreadStack + BOOT_STACK_SIZE)`
			`addiu $t2, %lo(bootproc)`
Disassemble the rom header and entrypoint function (#87) The actual boot code (ipl3) is still only incbin'd. If someone else wants to disassemble it properly, go ahead. I might do it eventually, but for now it doesn't seem required for shiftability or anything interesting. 2020-04-22 17:44:46 +00:00			`jr $t2`
Preliminary fixes for boot/libultra (#1032) * Preliminary fixes * Missed a NULL 2021-11-28 12:50:35 +00:00			`addiu $sp, %lo(sBootThreadStack + BOOT_STACK_SIZE)`
Disassemble the rom header and entrypoint function (#87) The actual boot code (ipl3) is still only incbin'd. If someone else wants to disassemble it properly, go ahead. I might do it eventually, but for now it doesn't seem required for shiftability or anything interesting. 2020-04-22 17:44:46 +00:00			`nop`
			`nop`
			`nop`
			`nop`
			`nop`
			`nop`
			`nop`
			`nop`
			`nop`
			`nop`
			`nop`