mirror/oot
1
0
Fork 0
mirror of https://github.com/zeldaret/oot.git synced 2025-02-20 22:05:21 +00:00
Code Issues Projects Releases Wiki Activity

[iQue] Match libultra/mgu (#2406)

Browse source
This commit is contained in:
Tharo 2025-01-07 08:36:34 +00:00 • committed by GitHub
parent aaf9c939a4
commit 727b61aaf8
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
3 changed files with 11 additions and 9 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

14
src/libultra/mgu/mtxf2l.s
View file

@ -13,23 +13,23 @@ LEAF(guMtxF2L)
addu t8, a1, MTX_FRACPART addu t8, a1, MTX_FRACPART
1: 1:
lwc1 ft0, 0(a0) lwc1 ft0, 0(a0)
lwc1 ft3, 4(a0)
mul.s ft1, ft0, fv0 mul.s ft1, ft0, fv0
mul.s ft4, ft3, fv0
trunc.w.s ft2, ft1 trunc.w.s ft2, ft1
lwc1 ft3, 4(a0)
mul.s ft4, ft3, fv0
trunc.w.s ft5, ft4 trunc.w.s ft5, ft4
mfc1 t0, ft2 mfc1 t0, ft2
mfc1 t1, ft5 mfc1 t1, ft5
srl t3, t1, 0x10
and t6, t1, 0xFFFF
and t2, t0, t9 and t2, t0, t9
sll t5, t0, 0x10 srl t3, t1, 0x10
or t4, t2, t3 or t4, t2, t3
or t7, t5, t6
sw t4, (MTX_INTPART)(a1) sw t4, (MTX_INTPART)(a1)
sll t5, t0, 0x10
and t6, t1, 0xFFFF
or t7, t5, t6
sw t7, (MTX_FRACPART)(a1) sw t7, (MTX_FRACPART)(a1)
addu a0, a0, 8
addu a1, a1, 4 addu a1, a1, 4
addu a0, a0, 8
bne a1, t8, 1b bne a1, t8, 1b
jr ra jr ra

4
src/libultra/mgu/normalize.s
View file

@ -8,8 +8,8 @@ LEAF(guNormalize)
lwc1 ft0, (a0) lwc1 ft0, (a0)
lwc1 ft1, (a1) lwc1 ft1, (a1)
lwc1 ft2, (a2) lwc1 ft2, (a2)
li.s t0, 1.0
mul.s ft3, ft0, ft0 mul.s ft3, ft0, ft0
li.s t0, 1.0
mul.s ft4, ft1, ft1 mul.s ft4, ft1, ft1
add.s ft5, ft3, ft4 add.s ft5, ft3, ft4
mul.s ft4, ft2, ft2 mul.s ft4, ft2, ft2
@ -18,7 +18,9 @@ LEAF(guNormalize)
sqrt.s ft4, ft3 sqrt.s ft4, ft3
div.s ft3, ft5, ft4 div.s ft3, ft5, ft4
mul.s ft4, ft0, ft3 mul.s ft4, ft0, ft3
nop
mul.s ft5, ft1, ft3 mul.s ft5, ft1, ft3
nop
mul.s ft0, ft2, ft3 mul.s ft0, ft2, ft3
swc1 ft4, (a0) swc1 ft4, (a0)
swc1 ft5, (a1) swc1 ft5, (a1)

2
src/libultra/mgu/translate.s
View file

@ -23,8 +23,8 @@ LEAF(guTranslate)
or t0, t0, t2 or t0, t0, t2
sw t0, 0x18(a0) sw t0, 0x18(a0)
sll t2, t3, 0x10
sll t0, t1, 0x10 sll t0, t1, 0x10
sll t2, t3, 0x10
srl t2, t2, 0x10 srl t2, t2, 0x10
or t0, t0, t2 or t0, t0, t2
sw t0, 0x38(a0) sw t0, 0x38(a0)