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Improve the state of handwritten assembly files (#865)
* Format all handwritten asm and document some * Use c preprocessor for constants * Fix * Fix PI_STATUS_ERROR, some label improvements * Avoid hi/lo for constants * Some more comments * Properly mark functions as functions and their sizes * Fix merge * Improvements * Review suggestions, rework procedure start/end macros to be more like libreultra * Move IPL3 symbol definitions into ipl3.s * Fix undefined_syms, add include and language guards to asm.h and fix the comment in gbi.h * Consistent hex capitalization, add some MIPS builtin defines to CC_CHECK to behave properly * Add -no-pad-sections assembler option and clean up alignment in gu files and bzero * Further suggestions and improvements * Matrix conversion function clarifications * Fix passing AVOID_UB to gcc * Suggestions * Suggestions, global interrupt mask improvements * Further suggestions, interrupt mask comments * Comments fixes, rdb.h * Switch from # comments to // comments, remove unnecesary .set gp=64 directives * Further review suggestions * Missed one
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62 changed files with 2758 additions and 2083 deletions
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@ -1,61 +1,94 @@
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.include "macro.inc"
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#include "ultra64/asm.h"
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#include "ultra64/r4300.h"
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# assembler directives
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.set noat # allow manual use of $at
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.set noreorder # don't insert nops after branches
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.set gp=64 # allow use of 64-bit general purpose registers
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.set noat
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.set noreorder
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.section .text
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.balign 16
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glabel osInvalDCache
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/* 006E00 80006200 18A0001F */ blez $a1, .L80006280
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/* 006E04 80006204 00000000 */ nop
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/* 006E08 80006208 240B2000 */ li $t3, 8192
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/* 006E0C 8000620C 00AB082B */ sltu $at, $a1, $t3
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/* 006E10 80006210 1020001D */ beqz $at, .L80006288
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/* 006E14 80006214 00000000 */ nop
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/* 006E18 80006218 00804025 */ move $t0, $a0
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/* 006E1C 8000621C 00854821 */ addu $t1, $a0, $a1
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/* 006E20 80006220 0109082B */ sltu $at, $t0, $t1
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/* 006E24 80006224 10200016 */ beqz $at, .L80006280
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/* 006E28 80006228 00000000 */ nop
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/* 006E2C 8000622C 310A000F */ andi $t2, $t0, 0xf
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/* 006E30 80006230 11400007 */ beqz $t2, .L80006250
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/* 006E34 80006234 2529FFF0 */ addiu $t1, $t1, -0x10
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/* 006E38 80006238 010A4023 */ subu $t0, $t0, $t2
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/* 006E3C 8000623C BD150000 */ cache 0x15, ($t0)
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/* 006E40 80006240 0109082B */ sltu $at, $t0, $t1
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/* 006E44 80006244 1020000E */ beqz $at, .L80006280
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/* 006E48 80006248 00000000 */ nop
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/* 006E4C 8000624C 25080010 */ addiu $t0, $t0, 0x10
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.L80006250:
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/* 006E50 80006250 312A000F */ andi $t2, $t1, 0xf
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/* 006E54 80006254 11400006 */ beqz $t2, .L80006270
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/* 006E58 80006258 00000000 */ nop
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/* 006E5C 8000625C 012A4823 */ subu $t1, $t1, $t2
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/* 006E60 80006260 BD350010 */ cache 0x15, 0x10($t1)
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/* 006E64 80006264 0128082B */ sltu $at, $t1, $t0
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/* 006E68 80006268 14200005 */ bnez $at, .L80006280
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/* 006E6C 8000626C 00000000 */ nop
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.L80006270:
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/* 006E70 80006270 BD110000 */ cache 0x11, ($t0)
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/* 006E74 80006274 0109082B */ sltu $at, $t0, $t1
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/* 006E78 80006278 1420FFFD */ bnez $at, .L80006270
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/* 006E7C 8000627C 25080010 */ addiu $t0, $t0, 0x10
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.L80006280:
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/* 006E80 80006280 03E00008 */ jr $ra
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/* 006E84 80006284 00000000 */ nop
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.L80006288:
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/* 006E88 80006288 3C088000 */ lui $t0, 0x8000
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/* 006E8C 8000628C 010B4821 */ addu $t1, $t0, $t3
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/* 006E90 80006290 2529FFF0 */ addiu $t1, $t1, -0x10
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.L80006294:
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/* 006E94 80006294 BD010000 */ cache 1, ($t0)
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/* 006E98 80006298 0109082B */ sltu $at, $t0, $t1
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/* 006E9C 8000629C 1420FFFD */ bnez $at, .L80006294
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/* 006EA0 800062A0 25080010 */ addiu $t0, 0x10
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/* 006EA4 800062A4 03E00008 */ jr $ra
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/* 006EA8 800062A8 00000000 */ nop
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/**
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* void osInvalDCache(void* vaddr, s32 nbytes);
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*
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* Invalidates the CPU Data Cache for `nbytes` at `vaddr`.
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* The cache is not automatically synced with physical memory, so cache
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* lines must be invalidated to ensure old data is not used in place of
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* newly available data supplied by an external agent in a DMA operation.
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*
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* If `vaddr` is not aligned to a cache line boundary, or nbytes is not a
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* multiple of the data cache line size (16 bytes) a larger region is
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* invalidated.
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*
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* If the amount to invalidate is at least the data cache size (DCACHE_SIZE),
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* the entire data cache is invalidated.
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*/
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LEAF(osInvalDCache)
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// If the amount to invalidate is less than or equal to 0, return immediately
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blez $a1, 3f
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nop
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// If the amount to invalidate is as large as or larger than
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// the data cache size, invalidate all
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li $t3, DCACHE_SIZE
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sltu $at, $a1, $t3
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beqz $at, 4f
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nop
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// Ensure end address doesn't wrap around and end up smaller
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// than the start address
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move $t0, $a0
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addu $t1, $a0, $a1
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sltu $at, $t0, $t1
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beqz $at, 3f
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nop
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// Mask start with cache line
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andi $t2, $t0, DCACHE_LINEMASK
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// If mask is not zero, the start is not cache aligned
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beqz $t2, 1f
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addiu $t1, $t1, -DCACHE_LINESIZE
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// Subtract mask result to align to cache line
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subu $t0, $t0, $t2
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// Hit-Writeback-Invalidate unaligned part
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cache (CACH_PD | C_HWBINV), ($t0)
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sltu $at, $t0, $t1
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// If that's all there is to do, return early
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beqz $at, 3f
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nop
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addiu $t0, $t0, DCACHE_LINESIZE
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1:
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// Mask end with cache line
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andi $t2, $t1, DCACHE_LINEMASK
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// If mask is not zero, the end is not cache aligned
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beqz $t2, 1f
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nop
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// Subtract mask result to align to cache line
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subu $t1, $t1, $t2
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// Hit-Writeback-Invalidate unaligned part
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cache (CACH_PD | C_HWBINV), DCACHE_LINESIZE($t1)
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sltu $at, $t1, $t0
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// If that's all there is to do, return early
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bnez $at, 3f
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nop
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// Invalidate the rest
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1:
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// Hit-Invalidate
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cache (CACH_PD | C_HINV), ($t0)
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sltu $at, $t0, $t1
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bnez $at, 1b
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addiu $t0, $t0, DCACHE_LINESIZE
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3:
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jr $ra
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nop
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4:
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li $t0, K0BASE
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addu $t1, $t0, $t3
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addiu $t1, $t1, -DCACHE_LINESIZE
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5:
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// Index-Writeback-Invalidate
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cache (CACH_PD | C_IWBINV), ($t0)
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sltu $at, $t0, $t1
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bnez $at, 5b
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addiu $t0, DCACHE_LINESIZE
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jr $ra
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nop
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END(osInvalDCache)
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