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Improve the state of handwritten assembly files (#865)
* Format all handwritten asm and document some * Use c preprocessor for constants * Fix * Fix PI_STATUS_ERROR, some label improvements * Avoid hi/lo for constants * Some more comments * Properly mark functions as functions and their sizes * Fix merge * Improvements * Review suggestions, rework procedure start/end macros to be more like libreultra * Move IPL3 symbol definitions into ipl3.s * Fix undefined_syms, add include and language guards to asm.h and fix the comment in gbi.h * Consistent hex capitalization, add some MIPS builtin defines to CC_CHECK to behave properly * Add -no-pad-sections assembler option and clean up alignment in gu files and bzero * Further suggestions and improvements * Matrix conversion function clarifications * Fix passing AVOID_UB to gcc * Suggestions * Suggestions, global interrupt mask improvements * Further suggestions, interrupt mask comments * Comments fixes, rdb.h * Switch from # comments to // comments, remove unnecesary .set gp=64 directives * Further review suggestions * Missed one
This commit is contained in:
Tharo
GitHub
parent
b9fded7b4e
commit
7334ffa373
62 changed files with 2758 additions and 2083 deletions
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@ -1,123 +1,168 @@
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.include "macro.inc"
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#include "ultra64/asm.h"
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#include "ultra64/r4300.h"
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#include "ultra64/rcp.h"
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#include "ultra64/exception.h"
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# assembler directives
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.set noat # allow manual use of $at
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.set noreorder # don't insert nops after branches
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.set gp=64 # allow use of 64-bit general purpose registers
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.section .text
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.balign 16
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glabel osSetIntMask
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/* 005B40 80004F40 400C6000 */ mfc0 $t4, $12
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/* 005B44 80004F44 3182FF01 */ andi $v0, $t4, 0xff01
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/* 005B48 80004F48 3C088001 */ lui $t0, %hi(__OSGlobalIntMask) # $t0, 0x8001
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/* 005B4C 80004F4C 2508AD00 */ addiu $t0, %lo(__OSGlobalIntMask) # addiu $t0, $t0, -0x5300
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/* 005B50 80004F50 8D0B0000 */ lw $t3, ($t0)
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/* 005B54 80004F54 2401FFFF */ li $at, -1
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/* 005B58 80004F58 01614026 */ xor $t0, $t3, $at
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/* 005B5C 80004F5C 3108FF00 */ andi $t0, $t0, 0xff00
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/* 005B60 80004F60 00481025 */ or $v0, $v0, $t0
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/* 005B64 80004F64 3C0AA430 */ lui $t2, %hi(D_A430000C) # $t2, 0xa430
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/* 005B68 80004F68 8D4A000C */ lw $t2, %lo(D_A430000C)($t2)
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/* 005B6C 80004F6C 11400005 */ beqz $t2, .L80004F84
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/* 005B70 80004F70 000B4C02 */ srl $t1, $t3, 0x10
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/* 005B74 80004F74 2401FFFF */ li $at, -1
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/* 005B78 80004F78 01214826 */ xor $t1, $t1, $at
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/* 005B7C 80004F7C 3129003F */ andi $t1, $t1, 0x3f
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/* 005B80 80004F80 01495025 */ or $t2, $t2, $t1
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.L80004F84:
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/* 005B84 80004F84 000A5400 */ sll $t2, $t2, 0x10
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/* 005B88 80004F88 004A1025 */ or $v0, $v0, $t2
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/* 005B8C 80004F8C 3C01003F */ lui $at, 0x3f
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/* 005B90 80004F90 00814024 */ and $t0, $a0, $at
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/* 005B94 80004F94 010B4024 */ and $t0, $t0, $t3
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/* 005B98 80004F98 000843C2 */ srl $t0, $t0, 0xf
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/* 005B9C 80004F9C 3C0A8001 */ lui $t2, %hi(__osRcpImTable)
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/* 005BA0 80004FA0 01485021 */ addu $t2, $t2, $t0
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/* 005BA4 80004FA4 954A2160 */ lhu $t2, %lo(__osRcpImTable)($t2)
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/* 005BA8 80004FA8 3C01A430 */ lui $at, %hi(D_A430000C) # $at, 0xa430
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/* 005BAC 80004FAC AC2A000C */ sw $t2, %lo(D_A430000C)($at)
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/* 005BB0 80004FB0 3088FF01 */ andi $t0, $a0, 0xff01
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/* 005BB4 80004FB4 3169FF00 */ andi $t1, $t3, 0xff00
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/* 005BB8 80004FB8 01094024 */ and $t0, $t0, $t1
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/* 005BBC 80004FBC 3C01FFFF */ lui $at, (0xFFFF00FF >> 16) # lui $at, 0xffff
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/* 005BC0 80004FC0 342100FF */ ori $at, (0xFFFF00FF & 0xFFFF) # ori $at, $at, 0xff
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/* 005BC4 80004FC4 01816024 */ and $t4, $t4, $at
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/* 005BC8 80004FC8 01886025 */ or $t4, $t4, $t0
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/* 005BCC 80004FCC 408C6000 */ mtc0 $t4, $12
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/* 005BD0 80004FD0 00000000 */ nop
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/* 005BD4 80004FD4 00000000 */ nop
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/* 005BD8 80004FD8 03E00008 */ jr $ra
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/* 005BDC 80004FDC 00000000 */ nop
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.set noat
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.set noreorder
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.section .rodata
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.balign 16
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glabel __osRcpImTable
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.half 0x0555
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.half 0x0556
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.half 0x0559
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.half 0x055A
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.half 0x0565
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.half 0x0566
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.half 0x0569
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.half 0x056A
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.half 0x0595
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.half 0x0596
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.half 0x0599
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.half 0x059A
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.half 0x05A5
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.half 0x05A6
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.half 0x05A9
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.half 0x05AA
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.half 0x0655
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.half 0x0656
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.half 0x0659
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.half 0x065A
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.half 0x0665
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.half 0x0666
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.half 0x0669
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.half 0x066A
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.half 0x0695
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.half 0x0696
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.half 0x0699
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.half 0x069A
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.half 0x06A5
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.half 0x06A6
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.half 0x06A9
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.half 0x06AA
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.half 0x0955
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.half 0x0956
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.half 0x0959
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.half 0x095A
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.half 0x0965
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.half 0x0966
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.half 0x0969
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.half 0x096A
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.half 0x0995
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.half 0x0996
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.half 0x0999
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.half 0x099A
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.half 0x09A5
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.half 0x09A6
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.half 0x09A9
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.half 0x09AA
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.half 0x0A55
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.half 0x0A56
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.half 0x0A59
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.half 0x0A5A
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.half 0x0A65
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.half 0x0A66
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.half 0x0A69
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.half 0x0A6A
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.half 0x0A95
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.half 0x0A96
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.half 0x0A99
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.half 0x0A9A
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.half 0x0AA5
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.half 0x0AA6
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.half 0x0AA9
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.half 0x0AAA
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/**
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* LUT to convert between an interrupt mask value and a value for MI_INTR_MASK_REG.
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* The interrupt mask value is a single bit 0 = disabled, 1 = enabled, while writes to MI_INTR_MASK_REG has two distinct non-zero
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* values for set and clear, hence the need for a conversion step.
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*/
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DATA(__osRcpImTable)
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.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP
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.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP
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.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP
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.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP
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.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP
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.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP
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.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP
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.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP
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.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP
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.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP
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.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP
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.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP
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.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP
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.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP
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.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP
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.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP
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.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP
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.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP
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.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP
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.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP
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.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP
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.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP
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.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP
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.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP
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.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP
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.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP
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.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP
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.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP
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.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP
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.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP
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.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP
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.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP
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.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP
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.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP
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.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP
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.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP
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.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP
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.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP
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.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP
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.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP
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.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP
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.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP
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.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP
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.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP
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.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP
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.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP
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.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP
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.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP
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.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP
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.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP
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.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP
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.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP
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.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP
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.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP
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.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP
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.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP
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.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP
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.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP
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.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP
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.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP
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.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP
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.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP
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.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP
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.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP
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ENDDATA(__osRcpImTable)
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.section .text
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.balign 16
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/**
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* OSIntMask osSetIntMask(OSIntMask);
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*
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* Sets the interrupt enable mask for the current thread. External interrupts
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* originating either in the CPU or the RCP may be "masked out" so that they
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* are not handled. This is sometimes important for critical code sections
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* that must not be interrupted.
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* Interrupts that are not enabled in the global interrupt mask __OSGlobalIntMask
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||||
* cannot be set here. The global interrupt mask is OS-internal and is not
|
||||
* expected to change during runtime.
|
||||
* The returned value is the previous interrupt enable mask so that it can be
|
||||
* restored later.
|
||||
*
|
||||
* @bug Some usage of the global interrupt mask is broken both in here and in the
|
||||
* exception handler routines.
|
||||
* While a thread is running, the C0_SR interrupt enable bits contain the
|
||||
* interrupt enable bits for the current thread masked by the global
|
||||
* interrupt mask. There is an attempt to recover only the original interrupt
|
||||
* enable bits belonging to the thread itself using the operation
|
||||
* (SR | ~__OSGlobalIntMask).
|
||||
* However, this does not work as intended and can cause interrupts to end
|
||||
* up enabled when not intended to be. The same issue is present for the
|
||||
* RCP interrupt enable bits in MI_INTR_MASK_REG.
|
||||
* This does not cause issues in practice as __OSGlobalIntMask is almost always
|
||||
* OS_IM_ALL, so the operation is usually simply (SR | 0).
|
||||
*/
|
||||
LEAF(osSetIntMask)
|
||||
// Extract interrupt enable bits from current SR
|
||||
mfc0 $t4, C0_SR
|
||||
andi $v0, $t4, (SR_IMASK | SR_IE)
|
||||
// Get value of __OSGlobalIntMask
|
||||
lui $t0, %hi(__OSGlobalIntMask)
|
||||
addiu $t0, %lo(__OSGlobalIntMask)
|
||||
lw $t3, ($t0)
|
||||
// Bitwise-OR in the disabled CPU bits of __OSGlobalIntMask
|
||||
li $at, ~0
|
||||
xor $t0, $t3, $at
|
||||
andi $t0, $t0, SR_IMASK
|
||||
or $v0, $v0, $t0
|
||||
// Fetch MI_INTR_MASK_REG
|
||||
lui $t2, %hi(PHYS_TO_K1(MI_INTR_MASK_REG))
|
||||
lw $t2, %lo(PHYS_TO_K1(MI_INTR_MASK_REG))($t2)
|
||||
// If there are RCP interrupts masked
|
||||
beqz $t2, 1f
|
||||
srl $t1, $t3, RCP_IMASKSHIFT
|
||||
// Bitwise-OR in the disabled RCP bits of __OSGlobalIntMask
|
||||
li $at, ~0
|
||||
xor $t1, $t1, $at
|
||||
andi $t1, $t1, (RCP_IMASK >> RCP_IMASKSHIFT)
|
||||
or $t2, $t2, $t1
|
||||
1:
|
||||
// Shift the RCP bits to not conflict with the CPU bits
|
||||
sll $t2, $t2, RCP_IMASKSHIFT
|
||||
// OR the CPU and RCP bits together
|
||||
or $v0, $v0, $t2
|
||||
// Extract RCP interrupt enable bits from requested mask and mask with __OSGlobalIntMask
|
||||
li $at, RCP_IMASK
|
||||
and $t0, $a0, $at
|
||||
and $t0, $t0, $t3
|
||||
// Convert to a value for MI_INTR_MASK_REG and set it
|
||||
srl $t0, $t0, (RCP_IMASKSHIFT-1)
|
||||
lui $t2, %hi(__osRcpImTable)
|
||||
addu $t2, $t2, $t0
|
||||
lhu $t2, %lo(__osRcpImTable)($t2)
|
||||
lui $at, %hi(PHYS_TO_K1(MI_INTR_MASK_REG))
|
||||
sw $t2, %lo(PHYS_TO_K1(MI_INTR_MASK_REG))($at)
|
||||
// Extract CPU interrupt enable bits from requested mask and mask with __OSGlobalIntMask
|
||||
andi $t0, $a0, OS_IM_CPU
|
||||
andi $t1, $t3, SR_IMASK
|
||||
and $t0, $t0, $t1
|
||||
li $at, ~SR_IMASK
|
||||
and $t4, $t4, $at
|
||||
// Bitwise OR in the remaining bits of SR and set new SR
|
||||
or $t4, $t4, $t0
|
||||
mtc0 $t4, C0_SR
|
||||
nop
|
||||
nop
|
||||
jr $ra
|
||||
nop
|
||||
END(osSetIntMask)
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue