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Use IDO for assembling handwritten asm files in src (#2390)
* as0 * Fix ASOPTFLAGS for src/libc, remove unnecessary noreorder region in kanread * Suggested changes * Use %half to load the boot bss size for matching Co-authored-by: cadmic <cadmic24@gmail.com> * Wrap all of __osProbeTLB in noreorder --------- Co-authored-by: cadmic <cadmic24@gmail.com>
This commit is contained in:
parent
ba6a83533a
commit
7e082f0c4f
54 changed files with 2612 additions and 2653 deletions
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@ -1,40 +1,36 @@
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#include "ultra64/asm.h"
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#include "ultra64/regdef.h"
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.set noat
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.set noreorder
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.section .text
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.balign 32
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.text
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.align 5
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#define MTX_INTPART 0
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#define MTX_FRACPART 0x20
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LEAF(guMtxF2L)
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li $at, 0x47800000 // 65536.0f
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mtc1 $at, $f0
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li $t9, 0xFFFF0000
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addiu $t8, $a1, MTX_FRACPART
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li.s fv0, 65536.0
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li t9, 0xFFFF0000
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addu t8, a1, MTX_FRACPART
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1:
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lwc1 $f4, ($a0)
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lwc1 $f10, 4($a0)
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addiu $a1, $a1, 4
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mul.s $f6, $f4, $f0
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addiu $a0, $a0, 8
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mul.s $f16, $f10, $f0
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trunc.w.s $f8, $f6
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trunc.w.s $f18, $f16
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mfc1 $t0, $f8
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mfc1 $t1, $f18
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and $t2, $t0, $t9
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sll $t5, $t0, 0x10
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srl $t3, $t1, 0x10
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andi $t6, $t1, 0xFFFF
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or $t4, $t2, $t3
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or $t7, $t5, $t6
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sw $t4, (MTX_INTPART-4)($a1)
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bne $a1, $t8, 1b
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sw $t7, (MTX_FRACPART-4)($a1)
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jr $ra
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nop
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lwc1 ft0, 0(a0)
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lwc1 ft3, 4(a0)
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mul.s ft1, ft0, fv0
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mul.s ft4, ft3, fv0
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trunc.w.s ft2, ft1
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trunc.w.s ft5, ft4
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mfc1 t0, ft2
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mfc1 t1, ft5
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srl t3, t1, 0x10
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and t6, t1, 0xFFFF
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and t2, t0, t9
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sll t5, t0, 0x10
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or t4, t2, t3
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or t7, t5, t6
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sw t4, (MTX_INTPART)(a1)
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sw t7, (MTX_FRACPART)(a1)
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addu a0, a0, 8
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addu a1, a1, 4
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bne a1, t8, 1b
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jr ra
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END(guMtxF2L)
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@ -1,29 +1,27 @@
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#include "ultra64/asm.h"
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#include "ultra64/regdef.h"
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.set noreorder
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.section .text
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.balign 32
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.text
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.align 5
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LEAF(guMtxIdent)
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addi $t0, $zero, 1
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sll $t1, $t0, 0x10
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sw $t1, ($a0)
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sw $zero, 4($a0)
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sw $t0, 8($a0)
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sw $zero, 0xc($a0)
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sw $zero, 0x10($a0)
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sw $t1, 0x14($a0)
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sw $zero, 0x18($a0)
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sw $t0, 0x1C($a0)
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sw $zero, 0x20($a0)
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sw $zero, 0x24($a0)
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sw $zero, 0x28($a0)
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sw $zero, 0x2c($a0)
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sw $zero, 0x30($a0)
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sw $zero, 0x34($a0)
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sw $zero, 0x38($a0)
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jr $ra
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sw $zero, 0x3C($a0)
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add t0, zero, 1
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sll t1, t0, 0x10
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sw t1, 0x00(a0)
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sw zero, 0x04(a0)
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sw t0, 0x08(a0)
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sw zero, 0x0C(a0)
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sw zero, 0x10(a0)
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sw t1, 0x14(a0)
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sw zero, 0x18(a0)
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sw t0, 0x1C(a0)
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sw zero, 0x20(a0)
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sw zero, 0x24(a0)
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sw zero, 0x28(a0)
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sw zero, 0x2c(a0)
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sw zero, 0x30(a0)
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sw zero, 0x34(a0)
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sw zero, 0x38(a0)
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sw zero, 0x3C(a0)
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jr ra
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END(guMtxIdent)
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@ -1,28 +1,26 @@
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#include "ultra64/asm.h"
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#include "ultra64/regdef.h"
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.set noreorder
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.section .text
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.balign 32
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.text
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.align 5
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LEAF(guMtxIdentF)
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li $t0, 0x3F800000 // 1.0f
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sw $t0, ($a0)
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sw $zero, 4($a0)
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sw $zero, 8($a0)
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sw $zero, 0xC($a0)
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sw $zero, 0x10($a0)
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sw $t0, 0x14($a0)
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sw $zero, 0x18($a0)
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sw $zero, 0x1C($a0)
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sw $zero, 0x20($a0)
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sw $zero, 0x24($a0)
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sw $t0, 0x28($a0)
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sw $zero, 0x2C($a0)
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sw $zero, 0x30($a0)
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sw $zero, 0x34($a0)
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sw $zero, 0x38($a0)
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jr $ra
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sw $t0, 0x3C($a0)
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li.s t0, 1.0
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sw t0, 0x00(a0)
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sw zero, 0x04(a0)
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sw zero, 0x08(a0)
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sw zero, 0x0C(a0)
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sw zero, 0x10(a0)
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sw t0, 0x14(a0)
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sw zero, 0x18(a0)
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sw zero, 0x1C(a0)
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sw zero, 0x20(a0)
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sw zero, 0x24(a0)
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sw t0, 0x28(a0)
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sw zero, 0x2C(a0)
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sw zero, 0x30(a0)
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sw zero, 0x34(a0)
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sw zero, 0x38(a0)
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sw t0, 0x3C(a0)
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jr ra
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END(guMtxIdentF)
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#include "ultra64/asm.h"
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#include "ultra64/regdef.h"
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.set noat
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.set noreorder
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.section .text
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.balign 32
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.text
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.align 5
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#define MTX_INTPART 0
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#define MTX_FRACPART 0x20
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#define FIXTOF 0.0000152587890625 /* 1.0f / 65536.0f */
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LEAF(guMtxL2F)
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li $at, 0x37800000 // 1.0f / 65536.0f
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mtc1 $at, $f0
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li $t9, 0xFFFF0000
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addiu $t8, $a1, MTX_FRACPART
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li.s fv0, FIXTOF
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li t9, 0xFFFF0000
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addiu t8, a1, MTX_FRACPART
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1:
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lw $t0, MTX_INTPART($a1)
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lw $t1, MTX_FRACPART($a1)
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addiu $a1, $a1, 4
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and $t2, $t0, $t9
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srl $t3, $t1, 0x10
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or $t4, $t2, $t3
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mtc1 $t4, $f4
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sll $t5, $t0, 0x10
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andi $t6, $t1, 0xFFFF
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or $t7, $t5, $t6
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cvt.s.w $f6, $f4
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mtc1 $t7, $f10
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addiu $a0, $a0, 8
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cvt.s.w $f16, $f10
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mul.s $f8, $f6, $f0
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nop
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mul.s $f18, $f16, $f0
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swc1 $f8, -8($a0)
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bne $a1, $t8, 1b
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swc1 $f18, -4($a0)
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jr $ra
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nop
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lw t0, MTX_INTPART(a1)
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lw t1, MTX_FRACPART(a1)
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and t2, t0, t9
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srl t3, t1, 0x10
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or t4, t2, t3
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sll t5, t0, 0x10
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and t6, t1, 0xFFFF
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or t7, t5, t6
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mtc1 t4, ft0
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cvt.s.w ft1, ft0
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mul.s ft2, ft1, fv0
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mtc1 t7, ft3
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cvt.s.w ft4, ft3
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mul.s ft5, ft4, fv0
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swc1 ft2, 0(a0)
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swc1 ft5, 4(a0)
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addu a0, a0, 8
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addu a1, a1, 4
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bne a1, t8, 1b
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jr ra
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END(guMtxL2F)
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#include "ultra64/asm.h"
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#include "ultra64/regdef.h"
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.set noreorder
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.section .text
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.balign 32
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.text
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.align 5
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LEAF(guNormalize)
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lwc1 $f4, ($a0)
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lwc1 $f6, ($a1)
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lwc1 $f8, ($a2)
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mul.s $f10, $f4, $f4
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li $t0, 0x3F800000 // 1.0f
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mul.s $f16, $f6, $f6
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add.s $f18, $f10, $f16
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mul.s $f16, $f8, $f8
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add.s $f10, $f16, $f18
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mtc1 $t0, $f18
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sqrt.s $f16, $f10
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div.s $f10, $f18, $f16
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mul.s $f16, $f4, $f10
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nop
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mul.s $f18, $f6, $f10
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nop
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mul.s $f4, $f8, $f10
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swc1 $f16, ($a0)
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swc1 $f18, ($a1)
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jr $ra
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swc1 $f4, ($a2)
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lwc1 ft0, (a0)
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lwc1 ft1, (a1)
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lwc1 ft2, (a2)
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li.s t0, 1.0
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mul.s ft3, ft0, ft0
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mul.s ft4, ft1, ft1
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add.s ft5, ft3, ft4
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mul.s ft4, ft2, ft2
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add.s ft3, ft4, ft5
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mtc1 t0, ft5
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sqrt.s ft4, ft3
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div.s ft3, ft5, ft4
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mul.s ft4, ft0, ft3
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mul.s ft5, ft1, ft3
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mul.s ft0, ft2, ft3
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swc1 ft4, (a0)
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swc1 ft5, (a1)
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swc1 ft0, (a2)
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jr ra
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END(guNormalize)
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#include "ultra64/asm.h"
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#include "ultra64/regdef.h"
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.set noat
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.set noreorder
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.section .text
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.balign 32
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.text
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.align 5
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LEAF(guScale)
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li $at, 0x47800000 // 65536.0f
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mtc1 $at, $f4
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mtc1 $a1, $f6
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sw $zero, 4($a0)
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sw $zero, 0xC($a0)
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mul.s $f8, $f6, $f4
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mtc1 $a2, $f6
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sw $zero, 0x10($a0)
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sw $zero, 0x18($a0)
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sw $zero, 0x24($a0)
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sw $zero, 0x2C($a0)
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sw $zero, 0x30($a0)
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trunc.w.s $f10, $f8
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mul.s $f8, $f6, $f4
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mtc1 $a3, $f6
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sw $zero, 0x38($a0)
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mfc1 $t1, $f10
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sw $zero, 0x3C($a0)
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srl $t2, $t1, 0x10
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trunc.w.s $f10, $f8
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mul.s $f8, $f6, $f4
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sll $t0, $t2, 0x10
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sll $t2, $t1, 0x10
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mfc1 $t1, $f10
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sw $t0, ($a0)
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sw $t2, 0x20($a0)
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srl $t0, $t1, 0x10
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trunc.w.s $f10, $f8
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andi $t2, $t1, 0xFFFF
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sw $t2, 0x28($a0)
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sw $t0, 8($a0)
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mfc1 $t1, $f10
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nop
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srl $t2, $t1, 0x10
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sll $t0, $t2, 0x10
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sw $t0, 0x14($a0)
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li $t0, 1
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sll $t2, $t1, 0x10
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sw $t2, 0x34($a0)
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jr $ra
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sw $t0, 0x1C($a0)
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li.s ft0, 65536.0
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mtc1 a1, ft1
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mul.s ft2, ft1, ft0
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trunc.w.s ft3, ft2
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mfc1 t1, ft3
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srl t2, t1, 0x10
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sll t0, t2, 0x10
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sw t0, 0x00(a0)
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sll t2, t1, 0x10
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sw t2, 0x20(a0)
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mtc1 a2, ft1
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mul.s ft2, ft1, ft0
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trunc.w.s ft3, ft2
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mfc1 t1, ft3
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srl t0, t1, 0x10
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sw t0, 0x08(a0)
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andi t2, t1, 0xFFFF
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sw t2, 0x28(a0)
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mtc1 a3, ft1
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mul.s ft2, ft1, ft0
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trunc.w.s ft3, ft2
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mfc1 t1, ft3
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srl t2, t1, 0x10
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sll t0, t2, 0x10
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sw t0, 0x14(a0)
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sll t2, t1, 0x10
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sw t2, 0x34(a0)
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li t0, 1
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sw t0, 0x1C(a0)
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sw zero, 0x04(a0)
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sw zero, 0x0C(a0)
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sw zero, 0x10(a0)
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sw zero, 0x18(a0)
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sw zero, 0x24(a0)
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sw zero, 0x2C(a0)
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sw zero, 0x30(a0)
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sw zero, 0x38(a0)
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sw zero, 0x3C(a0)
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jr ra
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END(guScale)
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#include "ultra64/asm.h"
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#include "ultra64/regdef.h"
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.set noat
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.set noreorder
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.section .text
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|
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.balign 32
|
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.text
|
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.align 5
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LEAF(guTranslate)
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li $at, 0x47800000 // 65536.0f
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mtc1 $at, $f4
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mtc1 $a1, $f6
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sw $zero, ($a0)
|
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sw $zero, 0x14($a0)
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mul.s $f8, $f6, $f4
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mtc1 $a2, $f6
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sw $zero, 8($a0)
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sw $zero, 4($a0)
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sw $zero, 0xC($a0)
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sw $zero, 0x10($a0)
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sw $zero, 0x20($a0)
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trunc.w.s $f10, $f8
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mul.s $f8, $f6, $f4
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mtc1 $a3, $f6
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sw $zero, 0x24($a0)
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mfc1 $t1, $f10
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sw $zero, 0x28($a0)
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sw $zero, 0x2C($a0)
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srl $t2, $t1, 0x10
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trunc.w.s $f10, $f8
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mul.s $f8, $f6, $f4
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sll $t0, $t2, 0x10
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sw $zero, 0x30($a0)
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mfc1 $t3, $f10
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sw $zero, 0x34($a0)
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srl $t2, $t3, 0x10
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trunc.w.s $f10, $f8
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or $t0, $t0, $t2
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sw $t0, 0x18($a0)
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sll $t0, $t1, 0x10
|
||||
sll $t2, $t3, 0x10
|
||||
mfc1 $t1, $f10
|
||||
srl $t2, $t2, 0x10
|
||||
or $t0, $t0, $t2
|
||||
sw $t0, 0x38($a0)
|
||||
srl $t2, $t1, 0x10
|
||||
sll $t0, $t2, 0x10
|
||||
addiu $t0, $t0, 1
|
||||
sw $t0, 0x1C($a0)
|
||||
lui $t0, 1
|
||||
ori $t0, $t0, 0
|
||||
sw $t0, ($a0)
|
||||
sw $t0, 0x14($a0)
|
||||
lui $t0, (0x00000001 >> 16)
|
||||
ori $t0, (0x00000001 & 0xFFFF)
|
||||
sll $t2, $t1, 0x10
|
||||
sw $t2, 0x3C($a0)
|
||||
jr $ra
|
||||
sw $t0, 8($a0)
|
||||
li.s ft0, 65536.0
|
||||
|
||||
mtc1 a1, ft1
|
||||
mul.s ft2, ft1, ft0
|
||||
trunc.w.s ft3, ft2
|
||||
mfc1 t1, ft3
|
||||
|
||||
mtc1 a2, ft1
|
||||
mul.s ft2, ft1, ft0
|
||||
trunc.w.s ft3, ft2
|
||||
mfc1 t3, ft3
|
||||
|
||||
srl t2, t1, 0x10
|
||||
sll t0, t2, 0x10
|
||||
srl t2, t3, 0x10
|
||||
or t0, t0, t2
|
||||
sw t0, 0x18(a0)
|
||||
|
||||
sll t2, t3, 0x10
|
||||
sll t0, t1, 0x10
|
||||
srl t2, t2, 0x10
|
||||
or t0, t0, t2
|
||||
sw t0, 0x38(a0)
|
||||
|
||||
mtc1 a3, ft1
|
||||
mul.s ft2, ft1, ft0
|
||||
trunc.w.s ft3, ft2
|
||||
mfc1 t1, ft3
|
||||
|
||||
srl t2, t1, 0x10
|
||||
sll t0, t2, 0x10
|
||||
addiu t0, t0, 1
|
||||
sw t0, 0x1C(a0)
|
||||
|
||||
sll t2, t1, 0x10
|
||||
sw t2, 0x3C(a0)
|
||||
|
||||
sw zero, 0x00(a0)
|
||||
sw zero, 0x04(a0)
|
||||
sw zero, 0x08(a0)
|
||||
sw zero, 0x0C(a0)
|
||||
sw zero, 0x10(a0)
|
||||
sw zero, 0x14(a0)
|
||||
sw zero, 0x20(a0)
|
||||
sw zero, 0x24(a0)
|
||||
sw zero, 0x28(a0)
|
||||
sw zero, 0x2C(a0)
|
||||
sw zero, 0x30(a0)
|
||||
sw zero, 0x34(a0)
|
||||
|
||||
lui t0, (0x00010000 >> 16)
|
||||
ori t0, (0x00010000 & 0xFFFF)
|
||||
sw t0, (a0)
|
||||
sw t0, 0x14(a0)
|
||||
|
||||
lui t0, (0x00000001 >> 16)
|
||||
ori t0, (0x00000001 & 0xFFFF)
|
||||
sw t0, 8(a0)
|
||||
|
||||
jr ra
|
||||
END(guTranslate)
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue