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167 lines
8.2 KiB
C
167 lines
8.2 KiB
C
/**
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* @file relocation.c
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*
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* This file contains the routine responsible for runtime relocation of dynamically loadable code segments (overlays),
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* see the description of Overlay_Relocate for details.
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*
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* @see Overlay_Relocate
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*/
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#include "global.h"
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// Extract MIPS register rs from an instruction word
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#define MIPS_REG_RS(insn) (((insn) >> 0x15) & 0x1F)
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// Extract MIPS register rt from an instruction word
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#define MIPS_REG_RT(insn) (((insn) >> 0x10) & 0x1F)
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// Extract MIPS jump target from an instruction word
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#define MIPS_JUMP_TARGET(insn) (((insn)&0x03FFFFFF) << 2)
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/**
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* Performs runtime relocation of overlay files, loadable code segments.
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*
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* Overlays are expected to be loadable anywhere in direct-mapped cached (KSEG0) memory, with some appropriate
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* alignment requirements; memory addresses in such code must be updated once loaded in order to execute properly.
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* When compiled, overlays are given 'fake' KSEG0 RAM addresses larger than the total possible available main memory
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* (>= 0x80800000), such addresses are referred to as Virtual RAM (VRAM) to distinguish them. When loading the overlay
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* the relocation table produced at compile time is consulted to determine where and how to update these VRAM addresses
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* to correct RAM addresses based on the location the overlay was loaded at, enabling the code to execute at this
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* address as if it were compiled to run at this address.
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*
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* Each relocation is represented by a packed 32-bit value, formatted in the following way:
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* - [31:30] 2-bit section id, taking values from the `RelocSectionId` enum.
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* - [29:24] 6-bit relocation type describing which relocation operation should be performed. Same as ELF32 MIPS.
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* - [23: 0] 24-bit section-relative offset indicating where in the section to apply this relocation.
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*
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* @param allocatedRamAddress Memory address the binary was loaded at.
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* @param ovlRelocs Overlay relocation section containing overlay section layout and runtime relocations.
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* @param vramStart Virtual RAM address that the overlay was compiled at.
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*/
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void Overlay_Relocate(void* allocatedRamAddress, OverlayRelocationSection* ovlRelocs, void* vramStart) {
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uintptr_t sections[RELOC_SECTION_MAX];
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u32 relocatedValue;
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u32 dbg;
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u32 relocOffset;
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u32 relocData;
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uintptr_t unrelocatedAddress;
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u32 i;
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u32* relocDataP;
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//! MIPS ELF relocation does not generally require tracking register values, so at first glance it appears this
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//! register tracking was an unnecessary complication. However there is a bug in the IDO compiler that can cause
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//! relocations to be emitted in the wrong order under rare circumstances when the compiler attempts to reuse a
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//! previous HI16 relocation for a different LO16 relocation as an optimization. This register tracking is likely
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//! a workaround to prevent improper matching of unrelated HI16 and LO16 relocations that would otherwise arise
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//! due to the incorrect ordering.
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u32* luiRefs[32];
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u32 luiVals[32];
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uintptr_t relocatedAddress;
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u32 reloc;
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u32* luiInstRef;
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uintptr_t allocu32 = (uintptr_t)allocatedRamAddress;
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u32* regValP;
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u32 isLoNeg;
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s32 pad;
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relocOffset = 0;
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relocatedValue = 0;
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unrelocatedAddress = 0;
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relocatedAddress = 0;
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if (gOverlayLogSeverity >= 3) {
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PRINTF("DoRelocation(%08x, %08x, %08x)\n", allocatedRamAddress, ovlRelocs, vramStart);
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PRINTF("text=%08x, data=%08x, rodata=%08x, bss=%08x\n", ovlRelocs->textSize, ovlRelocs->dataSize,
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ovlRelocs->rodataSize, ovlRelocs->bssSize);
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}
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sections[RELOC_SECTION_NULL] = 0;
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sections[RELOC_SECTION_TEXT] = allocu32;
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sections[RELOC_SECTION_DATA] = allocu32 + ovlRelocs->textSize;
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sections[RELOC_SECTION_RODATA] = sections[RELOC_SECTION_DATA] + ovlRelocs->dataSize;
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for (i = 0; i < ovlRelocs->nRelocations; i++) {
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reloc = ovlRelocs->relocations[i];
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// This will always resolve to a 32-bit aligned address as each section containing code or pointers must be
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// aligned to at least 4 bytes and the MIPS ABI defines the offset of both 16-bit and 32-bit relocations to
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// be the start of the 32-bit word containing the target.
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relocDataP = (u32*)(sections[RELOC_SECTION(reloc)] + RELOC_OFFSET(reloc));
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relocData = *relocDataP;
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switch (RELOC_TYPE_MASK(reloc)) {
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case R_MIPS_32 << RELOC_TYPE_SHIFT:
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// Handles 32-bit address relocation, used for things such as jump tables and pointers in data.
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// Just relocate the full address.
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// Check address is valid for relocation
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if ((*relocDataP & 0x0F000000) == 0) {
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relocOffset = *relocDataP - (uintptr_t)vramStart;
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relocatedValue = relocOffset + allocu32;
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relocatedAddress = relocatedValue;
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unrelocatedAddress = relocData;
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*relocDataP = relocatedAddress;
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}
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break;
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case R_MIPS_26 << RELOC_TYPE_SHIFT:
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// Handles 26-bit address relocation, used for jumps and jals.
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// Extract the address from the target field of the J-type MIPS instruction.
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// Relocate the address and update the instruction.
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unrelocatedAddress = PHYS_TO_K0(MIPS_JUMP_TARGET(*relocDataP));
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relocOffset = unrelocatedAddress - (uintptr_t)vramStart;
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relocatedValue = (*relocDataP & 0xFC000000) | (((allocu32 + relocOffset) & 0x0FFFFFFF) >> 2);
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relocatedAddress = PHYS_TO_K0(MIPS_JUMP_TARGET(relocatedValue));
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*relocDataP = relocatedValue;
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break;
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case R_MIPS_HI16 << RELOC_TYPE_SHIFT:
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// Handles relocation for a hi/lo pair, part 1.
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// Store the reference to the LUI instruction (hi) using the `rt` register of the instruction.
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// This will be updated later in the `R_MIPS_LO16` section.
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luiRefs[MIPS_REG_RT(*relocDataP)] = relocDataP;
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luiVals[MIPS_REG_RT(*relocDataP)] = *relocDataP;
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break;
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case R_MIPS_LO16 << RELOC_TYPE_SHIFT:
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// Handles relocation for a hi/lo pair, part 2.
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// Grab the stored LUI (hi) from the `R_MIPS_HI16` section using the `rs` register of the instruction.
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// The full address is calculated, relocated, and then used to update both the LUI and lo instructions.
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// If the lo part is negative, add 1 to the LUI value.
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// Note: The lo instruction is assumed to have a signed immediate.
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luiInstRef = luiRefs[MIPS_REG_RS(*relocDataP)];
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regValP = &luiVals[MIPS_REG_RS(*relocDataP)];
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// Check address is valid for relocation
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if ((((*regValP << 0x10) + (s16)*relocDataP) & 0x0F000000) == 0) {
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relocOffset = ((*regValP << 0x10) + (s16)*relocDataP) - (uintptr_t)vramStart;
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isLoNeg = ((relocOffset + allocu32) & 0x8000) ? 1 : 0; // adjust for signed immediate
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unrelocatedAddress = (*luiInstRef << 0x10) + (s16)relocData;
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*luiInstRef =
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(*luiInstRef & 0xFFFF0000) | ((((relocOffset + allocu32) >> 0x10) & 0xFFFF) + isLoNeg);
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relocatedValue = (*relocDataP & 0xFFFF0000) | ((relocOffset + allocu32) & 0xFFFF);
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relocatedAddress = (*luiInstRef << 0x10) + (s16)relocatedValue;
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*relocDataP = relocatedValue;
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}
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break;
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}
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dbg = 16;
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switch (RELOC_TYPE_MASK(reloc)) {
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case R_MIPS_32 << RELOC_TYPE_SHIFT:
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dbg += 6;
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FALLTHROUGH;
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case R_MIPS_26 << RELOC_TYPE_SHIFT:
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dbg += 10;
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FALLTHROUGH;
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case R_MIPS_LO16 << RELOC_TYPE_SHIFT:
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if (gOverlayLogSeverity >= 3) {
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PRINTF("%02d %08x %08x %08x ", dbg, relocDataP, relocatedValue, relocatedAddress);
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PRINTF(" %08x %08x %08x %08x\n", (uintptr_t)relocDataP + (uintptr_t)vramStart - allocu32, relocData,
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unrelocatedAddress, relocOffset);
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}
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// Adding a break prevents matching
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}
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}
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}
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