mirror of
https://github.com/zeldaret/oot.git
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7334ffa373
* Format all handwritten asm and document some * Use c preprocessor for constants * Fix * Fix PI_STATUS_ERROR, some label improvements * Avoid hi/lo for constants * Some more comments * Properly mark functions as functions and their sizes * Fix merge * Improvements * Review suggestions, rework procedure start/end macros to be more like libreultra * Move IPL3 symbol definitions into ipl3.s * Fix undefined_syms, add include and language guards to asm.h and fix the comment in gbi.h * Consistent hex capitalization, add some MIPS builtin defines to CC_CHECK to behave properly * Add -no-pad-sections assembler option and clean up alignment in gu files and bzero * Further suggestions and improvements * Matrix conversion function clarifications * Fix passing AVOID_UB to gcc * Suggestions * Suggestions, global interrupt mask improvements * Further suggestions, interrupt mask comments * Comments fixes, rdb.h * Switch from # comments to // comments, remove unnecesary .set gp=64 directives * Further review suggestions * Missed one
140 lines
5.2 KiB
C
140 lines
5.2 KiB
C
#ifndef ULTRA64_RCP_H
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#define ULTRA64_RCP_H
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#ifdef _LANGUAGE_C
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#define HW_REG(reg, type) *(volatile type*)((reg) | 0xA0000000)
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#endif
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#define AI_DRAM_ADDR_REG 0x04500000
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#define AI_LEN_REG 0x04500004
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#define AI_CONTROL_REG 0x04500008
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#define AI_STATUS_REG 0x0450000C
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#define AI_DACRATE_REG 0x04500010
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#define AI_BITRATE_REG 0x04500014
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#define AI_STATUS_AI_FULL (1 << 31)
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#define AI_STATUS_AI_BUSY (1 << 30)
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#define VI_STATUS_REG 0x04400000
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#define VI_CONTROL_REG VI_STATUS_REG
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#define VI_ORIGIN_REG 0x04400004
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#define VI_DRAM_ADDR_REG VI_ORIGIN_REG
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#define VI_WIDTH_REG 0x04400008
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#define VI_H_WIDTH_REG VI_WIDTH_REG
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#define VI_INTR_REG 0x0440000C
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#define VI_V_INTER_REG VI_INTR_REG
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#define VI_CURRENT_REG 0x04400010
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#define VI_V_CURRENT_LINE_REG VI_CURRENT_REG
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#define VI_BURST_REG 0x04400014
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#define VI_TIMING_REG VI_BURST_REG
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#define VI_V_SYNC_REG 0x04400018 //VI vertical sync
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#define VI_H_SYNC_REG 0x0440001C //VI horizontal sync
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#define VI_LEAP_REG 0x04400020 //VI horizontal sync leap
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#define VI_H_SYNC_LEAP_REG VI_LEAP_REG
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#define VI_H_START_REG 0x04400024 //VI horizontal video
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#define VI_H_VIDEO_REG VI_H_START_REG
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#define VI_V_START_REG 0x04400028 //VI vertical video
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#define VI_V_VIDEO_REG VI_V_START_REG
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#define VI_V_BURST_REG 0x0440002C //VI vertical burst
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#define VI_X_SCALE_REG 0x04400030 //VI x-scale
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#define VI_Y_SCALE_REG 0x04400034 //VI y-scale
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#define SP_IMEM_START 0x04001000
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#define SP_DMEM_START 0x04000000
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#define SP_MEM_ADDR_REG 0x04040000
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#define SP_DRAM_ADDR_REG 0x04040004
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#define SP_RD_LEN_REG 0x04040008
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#define SP_WR_LEN_REG 0x0404000C
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#define SP_STATUS_REG 0x04040010
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#define SP_PC_REG 0x04080000
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#define PI_DRAM_ADDR_REG 0x04600000 //PI DRAM address
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#define PI_CART_ADDR_REG 0x04600004 //PI pbus (cartridge) address
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#define PI_RD_LEN_REG 0x04600008 //PI read length
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#define PI_WR_LEN_REG 0x0460000C //PI write length
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#define PI_STATUS_REG 0x04600010 //PI status
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#define PI_BSD_DOM1_LAT_REG 0x04600014 //PI dom1 latency
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#define PI_DOMAIN1_REG 0x04600014
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#define PI_BSD_DOM1_PWD_REG 0x04600018 //PI dom1 pulse width
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#define PI_BSD_DOM1_PGS_REG 0x0460001C //PI dom1 page size
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#define PI_BSD_DOM1_RLS_REG 0x04600020 //PI dom1 release
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#define PI_BSD_DOM2_LAT_REG 0x04600024 //PI dom2 latency
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#define PI_DOMAIN2_REG 0x04600024
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#define PI_BSD_DOM2_PWD_REG 0x04600028 //PI dom2 pulse width
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#define PI_BSD_DOM2_PGS_REG 0x0460002C //PI dom2 page size
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#define PI_BSD_DOM2_RLS_REG 0x04600030 //PI dom2 release
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// PI_STATUS (read) bits
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#define PI_STATUS_BUSY (1 << 0)
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#define PI_STATUS_IOBUSY (1 << 1)
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#define PI_STATUS_ERROR (1 << 2)
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// PI_STATUS (write) bits
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#define PI_STATUS_RESET (1 << 0)
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#define PI_STATUS_CLR_INTR (1 << 1)
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#define SI_DRAM_ADDR_REG 0x04800000
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#define SI_PIF_ADDR_RD64B_REG 0x04800004
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#define SI_PIF_ADDR_WR64B_REG 0x04800010
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#define SI_STATUS_REG 0x04800018
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// SI_STATUS (read) bits
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#define SI_STATUS_DMA_BUSY (1 << 0)
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#define SI_STATUS_IO_READ_BUSY (1 << 1)
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#define SI_STATUS_DMA_ERROR (1 << 3)
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#define SI_STATUS_INTERRUPT (1 << 12)
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#define PIF_RAM_START 0x1FC007C0
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#define MI_INIT_MODE_REG 0x04300000
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#define MI_MODE_REG MI_INIT_MODE_REG
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#define MI_VERSION_REG 0x04300004
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#define MI_INTR_REG 0x04300008
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#define MI_INTR_MASK_REG 0x0430000C
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// MI_INIT_MODE_REG bits (write)
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#define MI_CLR_INIT (1 << 7)
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#define MI_SET_INIT (1 << 8)
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#define MI_CLR_EBUS (1 << 9)
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#define MI_SET_EBUS (1 << 10)
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#define MI_CLR_DP_INTR (1 << 11)
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#define MI_CLR_RDRAM (1 << 12)
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#define MI_SET_RDRAM (1 << 13)
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// MI_INTR_REG bits
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#define MI_INTR_SP (1 << 0)
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#define MI_INTR_SI (1 << 1)
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#define MI_INTR_AI (1 << 2)
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#define MI_INTR_VI (1 << 3)
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#define MI_INTR_PI (1 << 4)
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#define MI_INTR_DP (1 << 5)
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// MI_INTR_MASK_REG masks (read)
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#define MI_INTR_MASK_SP 0x01
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#define MI_INTR_MASK_SI 0x02
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#define MI_INTR_MASK_AI 0x04
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#define MI_INTR_MASK_VI 0x08
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#define MI_INTR_MASK_PI 0x10
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#define MI_INTR_MASK_DP 0x20
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// MI_INTR_MASK_REG masks (write)
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#define MI_INTR_MASK_CLR_SP 0x0001
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#define MI_INTR_MASK_SET_SP 0x0002
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#define MI_INTR_MASK_CLR_SI 0x0004
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#define MI_INTR_MASK_SET_SI 0x0008
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#define MI_INTR_MASK_CLR_AI 0x0010
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#define MI_INTR_MASK_SET_AI 0x0020
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#define MI_INTR_MASK_CLR_VI 0x0040
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#define MI_INTR_MASK_SET_VI 0x0080
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#define MI_INTR_MASK_CLR_PI 0x0100
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#define MI_INTR_MASK_SET_PI 0x0200
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#define MI_INTR_MASK_CLR_DP 0x0400
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#define MI_INTR_MASK_SET_DP 0x0800
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#define VI_NTSC_CLOCK 48681812 /* Hz = 48.681812 MHz */
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#define VI_PAL_CLOCK 49656530 /* Hz = 49.656530 MHz */
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#define VI_MPAL_CLOCK 48628316 /* Hz = 48.628316 MHz */
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#endif
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