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56 lines
2.1 KiB
C
56 lines
2.1 KiB
C
#include "ultra64.h"
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#include "global.h"
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typedef struct {
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/* 0x00 */ OSPiHandle piHandle;
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/* 0x74 */ OSIoMesg ioMesg;
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/* 0x8C */ OSMesgQueue msgQueue;
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} SsSramContext; // size = 0xA4
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SsSramContext sSsSramContext = { 0 };
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void SsSram_Init(u32 addr, u8 handleType, u8 handleDomain, u8 handleLatency, u8 handlePageSize, u8 handleRelDuration,
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u8 handlePulse, u32 handleSpeed) {
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u32 prevInt;
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OSPiHandle* handle = &sSsSramContext.piHandle;
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if ((u32)OS_PHYSICAL_TO_K1(addr) != (*handle).baseAddress) {
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sSsSramContext.piHandle.type = handleType;
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(*handle).baseAddress = (u32)OS_PHYSICAL_TO_K1(addr);
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sSsSramContext.piHandle.latency = handleLatency;
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sSsSramContext.piHandle.pulse = handlePulse;
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sSsSramContext.piHandle.pageSize = handlePageSize;
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sSsSramContext.piHandle.relDuration = handleRelDuration;
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sSsSramContext.piHandle.domain = handleDomain;
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sSsSramContext.piHandle.speed = handleSpeed;
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bzero(&sSsSramContext.piHandle.transferInfo, sizeof(__OSTranxInfo));
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prevInt = __osDisableInt();
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sSsSramContext.piHandle.next = __osPiTable;
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__osPiTable = &sSsSramContext.piHandle;
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__osRestoreInt(prevInt);
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sSsSramContext.ioMesg.hdr.pri = OS_MESG_PRI_NORMAL;
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sSsSramContext.ioMesg.hdr.retQueue = &sSsSramContext.msgQueue;
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sSsSramContext.ioMesg.devAddr = addr;
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}
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}
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void SsSram_Dma(void* dramAddr, size_t size, s32 direction) {
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OSMesg msg;
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osCreateMesgQueue(&sSsSramContext.msgQueue, &msg, 1);
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sSsSramContext.ioMesg.dramAddr = dramAddr;
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sSsSramContext.ioMesg.size = size;
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osWritebackDCache(dramAddr, size);
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osEPiStartDma(&sSsSramContext.piHandle, &sSsSramContext.ioMesg, direction);
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osRecvMesg(&sSsSramContext.msgQueue, &msg, OS_MESG_BLOCK);
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osInvalDCache(dramAddr, size);
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}
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void SsSram_ReadWrite(u32 addr, void* dramAddr, size_t size, s32 direction) {
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PRINTF("ssSRAMReadWrite:%08x %08x %08x %d\n", addr, dramAddr, size, direction);
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SsSram_Init(addr, DEVICE_TYPE_SRAM, PI_DOMAIN2, 5, 0xD, 2, 0xC, 0);
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SsSram_Dma(dramAddr, size, direction);
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}
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